From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B9E73AEF53; Wed, 13 May 2026 19:09:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778699380; cv=none; b=PqDUPrT1OePB9NOP4lmzlrUQJvgaeD3XEt3JnwoSOYQwBSOL7BEeKnclV0P6bTflag9rV7E18/yOIphstng9AE0VBptzMzSGdab4lyjDbyilXOkbLtpX6+B9jifmgjaWdo2N2h9odDEPkndNkfQxmsxd8G/Ij/fOtxwIrOvFrfI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778699380; c=relaxed/simple; bh=GjXTErhWfgaViTlNzBXlqACYyaRYirJ3JqvibeBV9eU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LsfpLfREHvoZPfFRLSYbtcU3smkhzGIZiGuuX2b9PQ6Zl9o25TID4OxgRpee+Xp6JrEMv9DI9rhKNdQN8pEw78pIdfaRpk8Mo3rKZoVrOyJb6NJk/azz58+V91lM8BER2Z6keSCfEKgcR4djzA+/SON+NnBEoNQy8rChBDf6FY8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RDx8LXVd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RDx8LXVd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D5ECFC19425; Wed, 13 May 2026 19:09:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778699379; bh=GjXTErhWfgaViTlNzBXlqACYyaRYirJ3JqvibeBV9eU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RDx8LXVdyCWSk60gIZ8HyyGN9yWDKYQgTJG8nYiO/eDtE/ijvo+vO4hiucPUE03jx +h2G1sDuxi0Y3sTkIlR0JB/xbZF7rRX5AIZBbDlh+yC3XYsbwiffBbYeS0j5Fz18vF J+AXDuf2FzgMDwmpWcqoau0IN6JtXCiKVFTBJ6sLDXsQvAxUKNApz4Ucb+S04vwQqF WrYSFO0xbAlnyp5u6+HEvl734RYD3XoTMNPD51As/uKRXGoUw5wLvIFTrxlOBfvqfS hgzNuf9dli5Mi5LvUsY7i5dayjKHfB1/HJyEjBwoN61y001LSnasOc+RFnaGo1IAYh FpP6zATEVOumw== From: Bjorn Andersson To: Michael Turquette , Stephen Boyd , Konrad Dybcio , Luo Jie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Luo Jie Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_pavir@quicinc.com, quic_suruchia@quicinc.com, Krzysztof Kozlowski Subject: Re: (subset) [PATCH v2 0/5] Add CMN PLL clock controller support for IPQ5332 Date: Wed, 13 May 2026 14:09:20 -0500 Message-ID: <177869936432.1496622.9030891427127725229.b4-ty@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260106-qcom_ipq5332_cmnpll-v2-0-f9f7e4efbd79@oss.qualcomm.com> References: <20260106-qcom_ipq5332_cmnpll-v2-0-f9f7e4efbd79@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Tue, 06 Jan 2026 21:35:09 -0800, Luo Jie wrote: > This patch series adds support for the CMN PLL block on the IPQ5332 SoC. > The CMN PLL implementation in IPQ5332 is largely similar to that of > IPQ9574, which is already supported by the driver. The primary difference > is that the fixed output clocks to PPE from the CMN PLL operate at 200 MHz. > > Additionally, IPQ5332 provides a single 50 MHz clock to both UNIPHY (PCS) > instances, which in turn supply either 25 MHz or 50 MHz to the connected > Ethernet PHY or switch. > > [...] Applied, thanks! [1/5] clk: qcom: cmnpll: Account for reference clock divider commit: 88c543fff756450bcd04ec4560c4440be36c9e75 [3/5] clk: qcom: cmnpll: Add IPQ5332 SoC support commit: 1dcbf4195a262d57f4da812248cdbbcdc81bf8d8 Best regards, -- Bjorn Andersson