From: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Georgi Djakov <djakov@kernel.org>,
Sibi Sankar <sibi.sankar@oss.qualcomm.com>,
Aaron Kling <webgeek1234@gmail.com>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
Neil Armstrong <neil.armstrong@linaro.org>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Subject: Re: [PATCH v4] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
Date: Wed, 13 May 2026 14:09:28 -0500 [thread overview]
Message-ID: <177869936438.1496622.896099724549747289.b4-ty@kernel.org> (raw)
In-Reply-To: <20260330-sm8550-ddr-bw-scaling-v4-1-5020c06983a0@gmail.com>
On Mon, 30 Mar 2026 16:50:20 -0500, Aaron Kling wrote:
> Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
> to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
> frequency by aggregating bandwidth requests of all CPU core with referenc
> to the current OPP they are configured in by the LMH/EPSS hardware.
>
> The effect is a proper caches & DDR frequency scaling when CPU cores
> changes frequency.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
commit: 3f5dcc05cd33e85e897571b4e44feb06f5399b68
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
prev parent reply other threads:[~2026-05-13 19:09 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-30 21:50 [PATCH v4] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths Aaron Kling via B4 Relay
2026-05-13 19:09 ` Bjorn Andersson [this message]
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