From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BEC4221D96; Sun, 31 May 2026 00:30:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780187447; cv=none; b=AeKN72fSKJrIGuYcns+/8YJlCrDwKLwEvtXgYx+p2e3Jz1jrXP6L5XeAIbmUEzp37KZCW5hRjmlqv6jo578ncMIvUmAcbhbRaT5p8jrLQ2JER02net3+TlDFEZaNxei8jERigdIZrBgAcN+v/Er5lCATgHzl0tLmcUNAGic6i/c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780187447; c=relaxed/simple; bh=jSFeqCxhpAgUeKIN5+HzsMPjbOZVdbultPoaOB+VNKs=; h=MIME-Version:Content-Type:Subject:From:To:Cc:In-Reply-To: References:Date:Message-Id; b=oin46krD30v0qem6w5trXXZef93nJLrrcGMI8qVsmdHgmrpm5N3RQn/WD9SdFSoPE0l//EmPEcYwAxwY5lHIYCC9Dk7NByCJAN/oLdngKsKc4Uk/ZLSbCcZ5+iWIQwDnGRZN4Qdic7zYZDp0Gs7g4Rl8iKXSXEtqWNy58bFLxHk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CoDMvB29; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CoDMvB29" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4717B1F00893; Sun, 31 May 2026 00:30:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780187445; bh=l5u1p0SOG2ZfNLguQTLAV6ODJE3LV9lpkqMO6ERPGXo=; h=Subject:From:To:Cc:In-Reply-To:References:Date; b=CoDMvB29YJbJi0dOpnotFHOOsGhmkxGCUMwkBkoWfP76SdsGnE6xrbOooawVynZu6 5G1Lg0dUBsnKL9Ml/pG8NGaJ1Wi4kZ1ZtZpDILDivbD1UE+aET4LamSFgeZLx4Vkpi 6Ouq6q6NNX4c3QTQcOJXve3a7lxY4v4xWKHkEQ5HEIxZ5Fn4TIs21PgyGXXbgYTuei Y3jLl53FCmyOXvQj6Bx9KnqcZM/2wsdvmID7c5FwWRiXZapgqEloxCKdRblLC5dYj5 Xq2rNdk6jFi2G268gXiKY+cIzYq9GcAjy2Y+krl5DQSYWwNCbx3C7vmS1+kutsAlmH NLPgNmdk51ReQ== Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: Re: [PATCH v13 4/5] media: qcom: camss: csid: Add support for CSID gen4 From: bod@kernel.org To: Hangxiang Ma Cc: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Atiya Kailany In-Reply-To: <20260508-kaanapali-camss-v13-4-2541d8e55651@oss.qualcomm.com> References: <20260508-kaanapali-camss-v13-0-2541d8e55651@oss.qualcomm.com> <20260508-kaanapali-camss-v13-4-2541d8e55651@oss.qualcomm.com> Date: Sun, 31 May 2026 01:30:37 +0100 Message-Id: <178018743790.17481.3674704182245202392.b4-reply@b4> X-Mailer: b4 0.16-dev-d5d98 X-Developer-Signature: v=1; a=openpgp-sha256; l=19600; i=bod@kernel.org; h=from:subject:message-id; bh=jSFeqCxhpAgUeKIN5+HzsMPjbOZVdbultPoaOB+VNKs=; b=owEBbQKS/ZANAwAKASJxO7Ohjcg6AcsmYgBqG4EvxlWlwIA7if48Lgz/nuxWAxriSa9dgYM+7 txlc6B6lM6JAjMEAAEKAB0WIQTmk/sqq6Nt4Rerb7QicTuzoY3IOgUCahuBLwAKCRAicTuzoY3I Ov/1D/45ChD5mgs91TjPpFo9tgs1NRjSHzc3kaUBOvi55p190Hr8EP6W7mCv5Y2m5yR5D7rwT2e lzJpNJVEHGRwcAMi0s3+PTi56FzGjFkyDwapSP1FNdO9ofEE1sobSB/gK4pukIoaGBlPVJ3Dleg RVuOSfpShuSzq+4WWVWxb11ooaxAZ+qdDoeKJqP73rZeERzR1ReM7FxsfiFdn4oppcTUSbHcxhW CdONPFAi0fBn73z/U21UaruTK/dCL10zfAAnK45KZ4ayXEBfCElzwXpYSuG2WJaB/eLewBqhp4O OLPr/jmRfwLD9p5KUllmJnDTGomhOGBa2WJIML4KtPwettAIVHmmIA8znxx23Nbu5y2KKnMC9D/ hBg0GvOKJ6SC0JjXYtqsuO0Phgb8nBjAUGIC6VEat4/SGfeElV9LXWbheY+ymRp2vtnKif8g45k gxDcJe6g2edogOnNW8IV0cPovfMw6Ap/p1ZV+jyKohDQ3xeU3gBHg8E3J36UkEpIy6Dw7cj+VCX iBFS4UAU+F4SSkAwy28QnwWNYNQsil3r+tu40DSB/K2bfjo0elM70JljGupy1qLNhhHqqBQKM+C auQEezNYCjNSQV6rgg9ecICwsZOirpwWV2GgfotiO6Et5bYb5DS7FD1fGnoNDRdgtB1tVQ6E7mw n3zEC6HhFedx43w== X-Developer-Key: i=bod@kernel.org; a=openpgp; fpr=E693FB2AABA36DE117AB6FB422713BB3A18DC83A On 2026-05-08 01:05 -0700, Hangxiang Ma wrote: > Add more detailed resource information for CSID devices along with the > driver for CSID gen4 that is responsible for CSID register configuration, > module reset and IRQ handling for BUF_DONE events. And aggregate a common > definition 'CSI2_RX_CFG0_PHY_SEL_BASE_IDX' into csid header file. Don't conflate two patches into one. - Common defintition is one patch - Adding your new thing is another patch Because bisectability, logical coherence, good practice. > In this CSID version, RUP and AUP update values are split into two > registers along with a SET register. Accordingly, enhance the CSID > interface to accommodate both the legacy combined reg_update and the > split RUP and AUP updates. > > Co-developed-by: Atiya Kailany > Signed-off-by: Atiya Kailany > Signed-off-by: Hangxiang Ma > --- > drivers/media/platform/qcom/camss/Makefile | 1 + > drivers/media/platform/qcom/camss/camss-csid-680.c | 1 - > .../media/platform/qcom/camss/camss-csid-gen3.c | 1 - > .../media/platform/qcom/camss/camss-csid-gen4.c | 376 +++++++++++++++++++++ > drivers/media/platform/qcom/camss/camss-csid.h | 11 +- > drivers/media/platform/qcom/camss/camss.c | 75 ++++ > 6 files changed, 462 insertions(+), 3 deletions(-) > > diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile > index 5e349b491513..ba9faa635bd7 100644 > --- a/drivers/media/platform/qcom/camss/Makefile > +++ b/drivers/media/platform/qcom/camss/Makefile > @@ -10,6 +10,7 @@ qcom-camss-objs += \ > camss-csid-680.o \ > camss-csid-gen2.o \ > camss-csid-gen3.o \ > + camss-csid-gen4.o \ > camss-csiphy-2ph-1-0.o \ > camss-csiphy-3ph-1-0.o \ > camss-csiphy.o \ > diff --git a/drivers/media/platform/qcom/camss/camss-csid-680.c b/drivers/media/platform/qcom/camss/camss-csid-680.c > index 3ad3a174bcfb..86134a23cd4e 100644 > --- a/drivers/media/platform/qcom/camss/camss-csid-680.c > +++ b/drivers/media/platform/qcom/camss/camss-csid-680.c > @@ -101,7 +101,6 @@ > #define CSI2_RX_CFG0_DL2_INPUT_SEL 12 > #define CSI2_RX_CFG0_DL3_INPUT_SEL 16 > #define CSI2_RX_CFG0_PHY_NUM_SEL 20 > -#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 > #define CSI2_RX_CFG0_PHY_TYPE_SEL 24 > > #define CSID_CSI2_RX_CFG1 0x204 > diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/media/platform/qcom/camss/camss-csid-gen3.c > index bd059243790e..76a4b62eca1b 100644 > --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c > +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c > @@ -103,7 +103,6 @@ > #define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\ > (0x34C + 0x100 * (rdi)) :\ > (0x54C + 0x100 * (rdi))) > -#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 > > static void __csid_configure_rx(struct csid_device *csid, > struct csid_phy_config *phy, int vc) > diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen4.c b/drivers/media/platform/qcom/camss/camss-csid-gen4.c > new file mode 100644 > index 000000000000..41035352c4bb > --- /dev/null > +++ b/drivers/media/platform/qcom/camss/camss-csid-gen4.c > @@ -0,0 +1,376 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * camss-csid-gen4.c > + * > + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module > + * > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "camss.h" > +#include "camss-csid.h" > +#include "camss-csid-gen3.h" > + > +/* Reset and Command Registers */ > +#define CSID_RST_CFG 0x108 > +#define RST_MODE BIT(0) > +#define RST_LOCATION BIT(4) > + > +/* Reset and Command Registers */ > +#define CSID_RST_CMD 0x10C > +#define SELECT_HW_RST BIT(0) > +#define SELECT_IRQ_RST BIT(2) > +#define CSID_IRQ_CMD 0x110 > +#define IRQ_CMD_CLEAR BIT(0) > + > +/* Register Update Commands, RUP/AUP */ > +#define CSID_RUP_CMD 0x114 > +#define CSID_AUP_CMD 0x118 > +#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi)) > +#define CSID_RUP_AUP_CMD 0x11C > +#define RUP_SET BIT(0) > +#define MUP BIT(4) > + > +/* Top level interrupt registers */ > +#define CSID_TOP_IRQ_STATUS 0x180 > +#define CSID_TOP_IRQ_MASK 0x184 > +#define CSID_TOP_IRQ_CLEAR 0x188 > +#define INFO_RST_DONE BIT(0) > +#define CSI2_RX_IRQ_STATUS BIT(2) > +#define BUF_DONE_IRQ_STATUS BIT(3) > + > +/* Buffer done interrupt registers */ > +#define CSID_BUF_DONE_IRQ_STATUS 0x1A0 > +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET 16 > +#define CSID_BUF_DONE_IRQ_MASK 0x1A4 > +#define CSID_BUF_DONE_IRQ_CLEAR 0x1A8 > +#define CSID_BUF_DONE_IRQ_SET 0x1AC > + > +/* CSI2 RX interrupt registers */ > +#define CSID_CSI2_RX_IRQ_STATUS 0x1B0 > +#define CSID_CSI2_RX_IRQ_MASK 0x1B4 > +#define CSID_CSI2_RX_IRQ_CLEAR 0x1B8 > +#define CSID_CSI2_RX_IRQ_SET 0x1BC > + > +/* CSI2 RX Configuration */ > +#define CSID_CSI2_RX_CFG0 0x880 > +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 > +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4 > +#define CSI2_RX_CFG0_PHY_NUM_SEL 20 > +#define CSID_CSI2_RX_CFG1 0x884 > +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) > +#define CSI2_RX_CFG1_VC_MODE BIT(2) > + > +#define MSM_CSID_MAX_SRC_STREAMS_GEN4 (csid_is_lite(csid) ? 4 : 5) > + > +/* RDI Configuration */ > +#define CSID_RDI_CFG0(rdi) \ > + ((csid_is_lite(csid) ? 0x3080 : 0x5480) + 0x200 * (rdi)) > +#define RDI_CFG0_RETIME_BS BIT(5) > +#define RDI_CFG0_TIMESTAMP_EN BIT(6) > +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) > +#define RDI_CFG0_DECODE_FORMAT 12 > +#define RDI_CFG0_DT 16 > +#define RDI_CFG0_VC 22 > +#define RDI_CFG0_EN BIT(31) > + > +/* RDI Control and Configuration */ > +#define CSID_RDI_CTRL(rdi) \ > + ((csid_is_lite(csid) ? 0x3088 : 0x5488) + 0x200 * (rdi)) > +#define RDI_CTRL_START_CMD BIT(0) > + > +#define CSID_RDI_CFG1(rdi) \ > + ((csid_is_lite(csid) ? 0x3094 : 0x5494) + 0x200 * (rdi)) > +#define RDI_CFG1_DROP_H_EN BIT(5) > +#define RDI_CFG1_DROP_V_EN BIT(6) > +#define RDI_CFG1_CROP_H_EN BIT(7) > +#define RDI_CFG1_CROP_V_EN BIT(8) > +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) > + > +/* RDI Pixel Store Configuration */ > +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0x5498 + 0x200 * (rdi)) Inconsistent indentation > +#define RDI_PIX_STORE_CFG0_EN BIT(0) > +#define RDI_PIX_STORE_CFG0_MIN_HBI 1 > + > +/* RDI IRQ Status in wrapper */ > +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) (0x224 + (0x10 * (rdi))) > +#define CSID_CSI2_RDIN_IRQ_MASK(rdi) (0x228 + (0x10 * (rdi))) And again here. > +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) (0x22C + (0x10 * (rdi))) > +#define INFO_RUP_DONE BIT(23) > + > +static void __csid_aup_rup_trigger(struct csid_device *csid) > +{ > + /* trigger SET in combined register */ > + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD); > +} > + > +static void __csid_aup_rup_clear(struct csid_device *csid, int port_id) > +{ > + /* Hardware clears the registers upon consuming the settings */ > + csid->aup_update &= ~CSID_RUP_AUP_RDI(port_id); > + csid->rup_update &= ~CSID_RUP_AUP_RDI(port_id); > +} > + > +static void __csid_aup_update(struct csid_device *csid, int port_id) > +{ > + csid->aup_update |= CSID_RUP_AUP_RDI(port_id); > + writel(csid->aup_update, csid->base + CSID_AUP_CMD); > + > + __csid_aup_rup_trigger(csid); > +} > + > +static void __csid_reg_update(struct csid_device *csid, int port_id) > +{ > + csid->rup_update |= CSID_RUP_AUP_RDI(port_id); > + writel(csid->rup_update, csid->base + CSID_RUP_CMD); > + > + __csid_aup_rup_trigger(csid); > +} > + > +static void __csid_configure_rx(struct csid_device *csid, > + struct csid_phy_config *phy) > +{ > + int val; > + > + val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; > + val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; > + val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) > + << CSI2_RX_CFG0_PHY_NUM_SEL; > + writel(val, csid->base + CSID_CSI2_RX_CFG0); > + > + val = CSI2_RX_CFG1_ECC_CORRECTION_EN; > + writel(val, csid->base + CSID_CSI2_RX_CFG1); > +} > + > +static void __csid_configure_rx_vc(struct csid_device *csid, int vc) > +{ > + int val; > + > + if (vc > 3) { > + val = readl(csid->base + CSID_CSI2_RX_CFG1); > + val |= CSI2_RX_CFG1_VC_MODE; > + writel(val, csid->base + CSID_CSI2_RX_CFG1); > + } > +} > + > +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi) > +{ > + int val = 0; > + > + if (enable) > + val = RDI_CTRL_START_CMD; > + > + writel(val, csid->base + CSID_RDI_CTRL(rdi)); > +} > + > +static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rdi) > +{ > + u32 val; > + > + /* > + * Configure pixel store to allow absorption of hblanking or idle time. > + * This helps with horizontal crop and prevents line buffer conflicts. > + * Reset state is 0x8 which has MIN_HBI=4, we keep the default MIN_HBI > + * and just enable the pixel store functionality. > + */ > + val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN; > + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi)); > +} > + > +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc) > +{ > + u32 val; > + u8 lane_cnt = csid->phy.lane_cnt; > + > + /* Source pads matching RDI channels on hardware. > + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. > + */ > + struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + port]; > + const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats, > + csid->res->formats->nformats, > + input_format->code); > + > + if (!lane_cnt) > + lane_cnt = 4; > + > + val = RDI_CFG0_TIMESTAMP_EN; > + val |= RDI_CFG0_TIMESTAMP_STB_SEL; > + val |= RDI_CFG0_RETIME_BS; > + > + /* note: for non-RDI path, this should be format->decode_format */ > + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; > + val |= vc << RDI_CFG0_VC; > + val |= format->data_type << RDI_CFG0_DT; > + writel(val, csid->base + CSID_RDI_CFG0(port)); > + > + val = RDI_CFG1_PACKING_FORMAT_MIPI; > + writel(val, csid->base + CSID_RDI_CFG1(port)); > + > + /* Configure pixel store using dedicated register in gen4 */ > + if (!csid_is_lite(csid)) > + __csid_configure_rdi_pix_store(csid, port); > + > + val = 0; > + writel(val, csid->base + CSID_RDI_CTRL(port)); > + > + val = readl(csid->base + CSID_RDI_CFG0(port)); > + > + if (enable) > + val |= RDI_CFG0_EN; > + > + writel(val, csid->base + CSID_RDI_CFG0(port)); > +} > + > +static void csid_configure_stream(struct csid_device *csid, u8 enable) > +{ > + u8 i, k; > + > + __csid_configure_rx(csid, &csid->phy); > + > + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { > + if (csid->phy.en_vc & BIT(i)) { > + __csid_configure_rdi_stream(csid, enable, i, 0); > + __csid_configure_rx_vc(csid, 0); > + > + for (k = 0; k < CAMSS_INIT_BUF_COUNT; k++) > + __csid_aup_update(csid, i); > + > + __csid_reg_update(csid, i); > + > + __csid_ctrl_rdi(csid, enable, i); > + } > + } > +} > + > +static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val) > +{ > + return 0; > +} > + > +static void csid_subdev_reg_update(struct csid_device *csid, int port_id, > + bool clear) > +{ > + if (clear) > + __csid_aup_rup_clear(csid, port_id); > + else > + __csid_aup_update(csid, port_id); > +} > + > +/** > + * csid_isr - CSID module interrupt service routine > + * @irq: Interrupt line > + * @dev: CSID device > + * > + * Return IRQ_HANDLED on success > + */ > +static irqreturn_t csid_isr(int irq, void *dev) > +{ > + struct csid_device *csid = dev; > + u32 val, buf_done_val; > + u8 reset_done; > + int i; > + > + val = readl(csid->base + CSID_TOP_IRQ_STATUS); > + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); > + > + reset_done = val & INFO_RST_DONE; > + > + buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); > + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); > + > + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { > + if (csid->phy.en_vc & BIT(i)) { > + val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); > + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); > + > + if (val & INFO_RUP_DONE) > + csid_subdev_reg_update(csid, i, true); > + > + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) > + camss_buf_done(csid->camss, csid->id, i); > + } > + } > + > + val = IRQ_CMD_CLEAR; > + writel(val, csid->base + CSID_IRQ_CMD); > + > + if (reset_done) > + complete(&csid->reset_complete); > + > + return IRQ_HANDLED; > +} > + > +/** > + * csid_reset - Trigger reset on CSID module and wait to complete > + * @csid: CSID device > + * > + * Return 0 on success or a negative error code otherwise > + */ > +static int csid_reset(struct csid_device *csid) > +{ > + unsigned long time; > + u32 val; > + int i; > + > + reinit_completion(&csid->reset_complete); > + > + val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS; > + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); > + writel(val, csid->base + CSID_TOP_IRQ_MASK); > + > + val = 0; > + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { > + if (csid->phy.en_vc & BIT(i)) { > + /* > + * Only need to clear buf done IRQ status here, > + * RUP done IRQ status will be cleared once isr > + * strobe generated by CSID_RST_CMD > + */ > + val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i); > + } > + } > + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); > + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK); > + > + /* Clear all IRQ status with CLEAR bits set */ > + val = IRQ_CMD_CLEAR; > + writel(val, csid->base + CSID_IRQ_CMD); > + > + val = RST_LOCATION | RST_MODE; > + writel(val, csid->base + CSID_RST_CFG); > + > + val = SELECT_HW_RST | SELECT_IRQ_RST; > + writel(val, csid->base + CSID_RST_CMD); > + > + time = wait_for_completion_timeout(&csid->reset_complete, > + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); > + > + if (!time) { > + dev_err(csid->camss->dev, "CSID reset timeout\n"); > + return -EIO; > + } > + > + return 0; > +} > + > +static void csid_subdev_init(struct csid_device *csid) > +{ > + csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED; > +} > + > +const struct csid_hw_ops csid_ops_gen4 = { > + .configure_stream = csid_configure_stream, > + .configure_testgen_pattern = csid_configure_testgen_pattern, > + .hw_version = csid_hw_version, > + .isr = csid_isr, > + .reset = csid_reset, > + .src_pad_code = csid_src_pad_code, > + .subdev_init = csid_subdev_init, > + .reg_update = csid_subdev_reg_update, > +}; > diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h > index aedc96ed84b2..75a113050eb1 100644 > --- a/drivers/media/platform/qcom/camss/camss-csid.h > +++ b/drivers/media/platform/qcom/camss/camss-csid.h > @@ -27,6 +27,8 @@ > /* CSID hardware can demultiplex up to 4 outputs */ > #define MSM_CSID_MAX_SRC_STREAMS 4 > > +/* CSIPHY to hardware PHY selector mapping */ > +#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 > #define CSID_RESET_TIMEOUT_MS 500 > > enum csid_testgen_mode { > @@ -154,7 +156,13 @@ struct csid_device { > void __iomem *base; > u32 irq; > char irq_name[30]; > - u32 reg_update; > + union { > + u32 reg_update; > + struct { > + u32 rup_update; > + u32 aup_update; > + }; > + }; > struct camss_clock *clock; > int nclocks; > struct regulator_bulk_data *supplies; > @@ -217,6 +225,7 @@ extern const struct csid_hw_ops csid_ops_340; > extern const struct csid_hw_ops csid_ops_680; > extern const struct csid_hw_ops csid_ops_gen2; > extern const struct csid_hw_ops csid_ops_gen3; > +extern const struct csid_hw_ops csid_ops_gen4; > > /* > * csid_is_lite - Check if CSID is CSID lite. > diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c > index b74d172a5f2d..e9342b9c8801 100644 > --- a/drivers/media/platform/qcom/camss/camss.c > +++ b/drivers/media/platform/qcom/camss/camss.c > @@ -157,6 +157,79 @@ static const struct camss_subdev_resources csiphy_res_kaanapali[] = { > }, > }; > > +static const struct camss_subdev_resources csid_res_kaanapali[] = { > + /* CSID0 */ > + { > + .clock = { "csid", "csid_csiphy_rx" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000, 480000000 } }, > + .reg = { "csid0" }, > + .interrupt = { "csid0" }, > + .csid = { > + .is_lite = false, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .hw_ops = &csid_ops_gen4, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID1 */ > + { > + .clock = { "csid", "csid_csiphy_rx" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000, 480000000 } }, > + .reg = { "csid1" }, > + .interrupt = { "csid1" }, > + .csid = { > + .is_lite = false, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .hw_ops = &csid_ops_gen4, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID2 */ > + { > + .clock = { "csid", "csid_csiphy_rx" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000, 480000000 } }, > + .reg = { "csid2" }, > + .interrupt = { "csid2" }, > + .csid = { > + .is_lite = false, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .hw_ops = &csid_ops_gen4, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID_LITE0 */ > + { > + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000, 480000000 } }, > + .reg = { "csid_lite0" }, > + .interrupt = { "csid_lite0" }, > + .csid = { > + .is_lite = true, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .hw_ops = &csid_ops_gen4, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID_LITE1 */ > + { > + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000, 480000000 } }, > + .reg = { "csid_lite1" }, > + .interrupt = { "csid_lite1" }, > + .csid = { > + .is_lite = true, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .hw_ops = &csid_ops_gen4, > + .formats = &csid_formats_gen2 > + } > + } > +}; > + > static const struct resources_icc icc_res_kaanapali[] = { > { > .name = "ahb", > @@ -5243,9 +5316,11 @@ static const struct camss_resources kaanapali_resources = { > .version = CAMSS_KAANAPALI, > .pd_name = "top", > .csiphy_res = csiphy_res_kaanapali, > + .csid_res = csid_res_kaanapali, > .icc_res = icc_res_kaanapali, > .icc_path_num = ARRAY_SIZE(icc_res_kaanapali), > .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali), > + .csid_num = ARRAY_SIZE(csid_res_kaanapali), > }; > > static const struct camss_resources msm8916_resources = { > > -- > 2.34.1 > > I can fix those minor issues for you. Reviewed-by: Bryan O'Donoghue --- bod