From: Vinod Koul <vkoul@kernel.org>
To: Neil Armstrong <neil.armstrong@linaro.org>,
Heiko Stuebner <heiko@sntech.de>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Gerald Loacker <gerald.loacker@wolfvision.net>
Cc: linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Michael Riesch <michael.riesch@collabora.com>
Subject: Re: [PATCH v4 0/3] phy: rockchip: inno-csidphy: fix 2500 Mbps support and add clock lane phase tuning
Date: Thu, 06 Aug 2026 21:56:27 +0530 [thread overview]
Message-ID: <178603358793.674490.17206086804451771679.b4-ty@kernel.org> (raw)
In-Reply-To: <20260725-feature-mipi-csi-dphy-4k60-v4-0-5b2c4626d31e@wolfvision.net>
On Sat, 25 Jul 2026 18:56:02 +0200, Gerald Loacker wrote:
> This series fixes and extends the Rockchip Innosilicon CSI D-PHY driver
> to support data rates up to 2500 Mbps and adds optional board-specific
> clock lane phase tuning for signal integrity.
>
> Patch 1 fixes an off-by-one error in the rk1808 hsfreq range table:
> the final entry was capped at 2499 Mbps, causing a rejection of the
> maximum supported rate of 2500 Mbps.
>
> [...]
Applied, thanks!
[1/3] phy: rockchip: phy-rockchip-inno-csidphy: fix rk1808 hsfreq table
commit: 4fae43e33a7c10951fbdc6baf409d51bd66aaefb
[2/3] dt-bindings: phy: rockchip-inno-csi-dphy: add rockchip,clk-lane-phase property
commit: f82ff8609f582ca5105e45f18dfc3e949dfeaef1
[3/3] phy: rockchip: phy-rockchip-inno-csidphy: add clock lane phase tuning
commit: 333c23c31696dbddd7dad28e82bd34e37a67d5ff
Best regards,
--
~Vinod
prev parent reply other threads:[~2026-08-06 16:26 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-25 16:56 [PATCH v4 0/3] phy: rockchip: inno-csidphy: fix 2500 Mbps support and add clock lane phase tuning Gerald Loacker
2026-07-25 16:56 ` [PATCH v4 1/3] phy: rockchip: phy-rockchip-inno-csidphy: fix rk1808 hsfreq table Gerald Loacker
2026-07-25 17:04 ` sashiko-bot
2026-07-25 16:56 ` [PATCH v4 2/3] dt-bindings: phy: rockchip-inno-csi-dphy: add rockchip,clk-lane-phase property Gerald Loacker
2026-07-25 16:56 ` [PATCH v4 3/3] phy: rockchip: phy-rockchip-inno-csidphy: add clock lane phase tuning Gerald Loacker
2026-08-03 11:04 ` Michael Riesch
2026-08-06 16:26 ` Vinod Koul [this message]
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