From: Jerome Brunet <jbrunet@baylibre.com>
To: Changhuang Liang <changhuang.liang@starfivetech.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Alexey Charkov <alchark@gmail.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Keguang Zhang <keguang.zhang@gmail.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Hal Feng <hal.feng@starfivetech.com>
Subject: Re: [PATCH v5 3/8] clk: starfive: Add peripheral-0 domain PLL clock driver
Date: Wed, 30 Sep 2026 11:45:24 +0200 [thread overview]
Message-ID: <179076152492.1471718.9285719072832956935.b4-reply@b4> (raw)
In-Reply-To: <20260828095608.19955-4-changhuang.liang@starfivetech.com>
On 2026-08-28 02:56 -0700, Changhuang Liang wrote:
> Add peripheral-0 domain PLL clock driver support for StarFive JHB100
> SoC.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> Reviewed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
> .../clk/starfive/clk-starfive-jhb100-pll.c | 60 +++++++++++++++----
> 1 file changed, 50 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/clk/starfive/clk-starfive-jhb100-pll.c b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
> index e23365164497..f6ebaaf5aa18 100644
> --- a/drivers/clk/starfive/clk-starfive-jhb100-pll.c
> +++ b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
> @@ -30,6 +30,9 @@
> #define JHB100_PLL4_OFFSET 0x18
> #define JHB100_PLL5_OFFSET 0x24
>
> +/* Peripheral-0 domain PLL */
> +#define JHB100_PLL6_OFFSET 0x00
> +
> #define JHB100_PLL_CFG0_OFFSET 0x0
> #define JHB100_PLL_CFG1_OFFSET 0x4
> #define JHB100_PLL_CFG2_OFFSET 0x8
> @@ -417,16 +420,21 @@ static int jhb100_pll_probe(struct platform_device *pdev)
> unsigned int idx;
> int ret;
>
> - id = platform_get_device_id(pdev);
> - if (!id)
> - return dev_err_probe(dev, -EINVAL, "no match data\n");
> -
> - /*
> - * Instantiated as an MFD cell of the sys0 system controller,
> - * which owns the DT node describing the PLL registers.
> - */
> - match_data = (const struct jhb100_pll_match_data *)id->driver_data;
> - np = dev_of_node(dev->parent);
> + match_data = device_get_match_data(dev);
> + if (match_data) {
> + np = dev_of_node(dev);
> + } else {
> + id = platform_get_device_id(pdev);
> + if (!id)
> + return dev_err_probe(dev, -EINVAL, "no match data\n");
> +
> + /*
> + * Instantiated as an MFD cell of the sys0 system controller,
> + * which owns the DT node describing the PLL registers.
> + */
> + match_data = (const struct jhb100_pll_match_data *)id->driver_data;
> + np = dev_of_node(dev->parent);
> + }
This is quite ugly.
It looks like your PLL is a building block you'll be re-using.
Just make a module out it and re-use it is different platform drivers rather
than trying to fit all your devices in the same platform driver.
>
> priv = devm_kzalloc(&pdev->dev, struct_size(priv, pll, match_data->num_pll),
> GFP_KERNEL);
> @@ -504,6 +512,28 @@ static const struct jhb100_pll_match_data jhb100_sys0_pll = {
> .num_pll = ARRAY_SIZE(jhb100_sys0_pll_info),
> };
>
> +static const struct jhb100_pll_preset jhb100_pll6_presets[] = {
> + {
> + .freq = 2400000000,
> + .fbdiv = 192,
> + .frac = 0,
> + .refdiv = 1,
> + .postdiv = 0,
> + .foutpostdiv_en = 1,
> + .foutvcop_en = 0,
> + },
> +};
> +
> +static const struct jhb100_pll_info jhb100_per0_pll_info[] = {
> + JHB100_PLL(JHB100_PER0PLL_PLL6_OUT, "pll6_out", jhb100_pll6_presets,
> + ARRAY_SIZE(jhb100_pll6_presets), JHB100_PLL6_OFFSET, false),
> +};
> +
> +static const struct jhb100_pll_match_data jhb100_per0_pll = {
> + .pll_info = jhb100_per0_pll_info,
> + .num_pll = ARRAY_SIZE(jhb100_per0_pll_info),
> +};
> +
> static const struct platform_device_id jhb100_pll_ids[] = {
> {
> .name = "jhb100-sys0-pll",
> @@ -513,11 +543,21 @@ static const struct platform_device_id jhb100_pll_ids[] = {
> };
> MODULE_DEVICE_TABLE(platform, jhb100_pll_ids);
>
> +static const struct of_device_id jhb100_pll_match[] = {
> + {
> + .compatible = "starfive,jhb100-per0-syscon",
> + .data = &jhb100_per0_pll,
> + },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, jhb100_pll_match);
> +
> static struct platform_driver jhb100_pll_driver = {
> .probe = jhb100_pll_probe,
> .id_table = jhb100_pll_ids,
> .driver = {
> .name = "clk-starfive-jhb100-pll",
> + .of_match_table = jhb100_pll_match,
> .suppress_bind_attrs = true,
> },
> };
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2026-09-30 9:45 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-28 9:56 [PATCH v5 0/8] Add StarFive JHB100 syscon modules Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 1/8] dt-bindings: soc: starfive: " Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 2/8] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
2026-09-30 8:56 ` Jerome Brunet
2026-10-03 11:02 ` Changhuang Liang
2026-10-05 9:20 ` Jerome Brunet
2026-10-08 2:57 ` Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 3/8] clk: starfive: Add peripheral-0 " Changhuang Liang
2026-09-30 9:45 ` Jerome Brunet [this message]
2026-10-03 11:29 ` Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 4/8] clk: starfive: Add Peripheral-1 " Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 5/8] reset: starfive: Introduce active_low Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 6/8] reset: starfive: Add syscon reset driver support Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 7/8] soc: starfive: Add socinfo driver for JHB100 SoC Changhuang Liang
2026-08-28 9:56 ` [PATCH v5 8/8] riscv: dts: starfive: jhb100: Add syscon nodes Changhuang Liang
2026-09-08 20:06 ` [PATCH v5 0/8] Add StarFive JHB100 syscon modules Conor Dooley
2026-09-09 1:06 ` Changhuang Liang
2026-10-02 20:29 ` Conor Dooley
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