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[91.210.24.215]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de09693c7sm23470807f8f.4.2026.10.15.06.25.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 06:25:15 -0700 (PDT) From: Fil Dunsky To: Thomas Gleixner Cc: Fil Dunsky via B4 Relay , Radu Rendec , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Andi Shyti , Wim Van Sebroeck , Guenter Roeck , Russell King , Arnd Bergmann , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH v3 02/11] irqchip: Add Cortina Systems CS75xx peripheral interrupt controller In-Reply-To: <87tsmndu0p.ffs@fw13> References: <20261013-b4-cs75xx-s2-v3-0-181bb0d23f4c@gmail.com> <20261013-b4-cs75xx-s2-v3-2-181bb0d23f4c@gmail.com> <87tsmndu0p.ffs@fw13> Date: Thu, 15 Oct 2026 16:25:06 +0300 Message-ID: <179207070645.418589.10399440167204506807@gmail.com> Content-Transfer-Encoding: 8bit Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format="fixed" On Thu, Oct 15 2026 at 14:32, Thomas Gleixner wrote: > On Tue, Oct 13 2026 at 09:07, Fil Dunsky via B4 Relay wrote: >> +static int __init cs75xx_intc_init(struct device_node *np, >> + struct device_node *parent) > > No line break required. You have 100 characters. Please fix that all > over the place. Done for the next version, the declaration and the calls in the init function are on one or two lines now. > Other than that this looks good. Thanks for the review. The next version will come after v7.4-rc1, with the interrupt controller as a series of its own (binding and driver), split from the GPIO, I2C and watchdog patches. Fil