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Mon, 09 Dec 2024 04:30:18 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B94UHt0005868 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Dec 2024 04:30:17 GMT Received: from [10.216.4.234] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 8 Dec 2024 20:30:10 -0800 Message-ID: <17c9839d-c61e-3c2f-4d77-5e8813f3a9c8@quicinc.com> Date: Mon, 9 Dec 2024 10:00:06 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 2/3] PCI: dwc: Add ECAM support with iATU configuration To: Bjorn Helgaas CC: , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jingoo Han , "Manivannan Sadhasivam" , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , , , , , , , , , , , References: <20241204221714.GA3023492@bhelgaas> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20241204221714.GA3023492@bhelgaas> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 8DbU83nimCF42SVCvQNf9-IrGLpTh27j X-Proofpoint-GUID: 8DbU83nimCF42SVCvQNf9-IrGLpTh27j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 clxscore=1015 suspectscore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412090034 On 12/5/2024 3:47 AM, Bjorn Helgaas wrote: > On Wed, Dec 04, 2024 at 07:45:29AM +0530, Krishna Chaitanya Chundru wrote: >> On 12/4/2024 12:25 AM, Bjorn Helgaas wrote: >>> On Sun, Nov 17, 2024 at 03:30:19AM +0530, Krishna chaitanya chundru wrote: >>>> The current implementation requires iATU for every configuration >>>> space access which increases latency & cpu utilization. >>>> >>>> Configuring iATU in config shift mode enables ECAM feature to access the >>>> config space, which avoids iATU configuration for every config access. > >>>> +static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp) >>>> +{ >>>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >>>> + struct dw_pcie_ob_atu_cfg atu = {0}; >>>> + struct resource_entry *bus; >>>> + int ret, bus_range_max; >>>> + >>>> + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); >>>> + >>>> + /* >>>> + * Bus 1 config space needs type 0 atu configuration >>>> + * Remaining buses need type 1 atu configuration >>> >>> I'm confused about the bus numbering; you refer to "bus 1" and "bus >>> 2". Is bus 1 the root bus, i.e., the primary bus of a Root Port? >>> >>> The root bus number would typically be 0, not 1, and is sometimes >>> programmable. I don't know how the DesignWare core works, but since >>> you have "bus" here, referring to "bus 1" and "bus 2" here seems >>> overly specific. >>> >> root bus is bus 0 and we don't need any iATU configuration for it as >> its config space is accessible from the system memory, for usp port of >> the switch or the direct the endpoint i.e bus 1 we need to send >> Configuration Type 0 requests and for other buses we need to send >> Configuration Type 1 requests this is as per PCIe spec, I will try to >> include PCIe spec details in next patch. > > I understand the Type 0/Type 1 differences. The question is whether > the root bus number is hard-wired to 0. > It is not hard-wired to 0, we can configure it though bus-range property > I don't think specifying "bus 1" really adds anything. The point is > that we need Type 0 accesses for anything directly below a Root Port > (regardless of what the RP's secondary bus number is), and Type 1 for > things deeper. > I will update the comment without mentioning the buses as suggested. > When DWC supports multiple Root Ports in a Root Complex, they will not > all have a secondary bus number of 1. mostly they should be in bus number 0 with different device numbers, but it mostly depends upon the design, currently we don't have any multiple root ports. - Krishna Chaitanya. > > Bjorn