From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH 10/11] irqchip: bcm7120-l2: Extend driver to support 64+ bit controllers Date: Thu, 30 Oct 2014 10:10:03 +0100 Message-ID: <1819614.RKinL4RR5c@wuerfel> References: <1414555138-6500-1-git-send-email-cernekee@gmail.com> <7518897.LmfE2WsusV@wuerfel> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Kevin Cernekee Cc: Florian Fainelli , Thomas Gleixner , Jason Cooper , Ralf Baechle , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Maxime Bizon , Jonas Gorski , Linux MIPS Mailing List List-Id: devicetree@vger.kernel.org On Wednesday 29 October 2014 16:22:31 Kevin Cernekee wrote: > > This uses one domain per bcm7120-l2 DT node. If the DT node defines > multiple enable/status pairs (i.e. >=64 IRQs) then the driver will > create a single IRQ domain with 2+ generic chips. > > Multiple generic chips are required because the generic-chip code can > only handle one enable/status register pair per instance. > Makes sense. Just make sure you have that explanation in the patch description. Arnd