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[178.79.73.218]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-427f009a96asm16569602f8f.31.2025.10.20.11.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Oct 2025 11:22:57 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: wens@kernel.org Cc: Jernej Skrabec , Samuel Holland , Mark Brown , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , linux-sunxi@lists.linux.dev, linux-sound@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 06/11] clk: sunxi-ng: sun55i-a523-ccu: Lower audio0 pll minimum rate Date: Mon, 20 Oct 2025 20:22:55 +0200 Message-ID: <1837721.VLH7GnMWUR@jernej-laptop> In-Reply-To: References: <20251020171059.2786070-1-wens@kernel.org> <8591609.T7Z3S40VBb@jernej-laptop> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne ponedeljek, 20. oktober 2025 ob 20:09:18 Srednjeevropski poletni =C4=8D= as je Chen-Yu Tsai napisal(a): > On Tue, Oct 21, 2025 at 1:52=E2=80=AFAM Jernej =C5=A0krabec wrote: > > > > Dne ponedeljek, 20. oktober 2025 ob 19:10:52 Srednjeevropski poletni = =C4=8Das je Chen-Yu Tsai napisal(a): > > > While the user manual states that the PLL's rate should be between 180 > > > MHz and 3 GHz in the register defninition section, it also says the > > > actual operating frequency is 22.5792*4 MHz in the PLL features table. > > > > > > 22.5792*4 MHz is one of the actual clock rates that we want and is > > > is available in the SDM table. Lower the minimum clock rate to 90 MHz > > > so that both rates in the SDM table can be used. > > > > So factor of 2 could be missed somewhere? >=20 > Not sure what you mean? This PLL only gives *4 and *1 outputs. Right. Nevermind then. Best regards, Jernej >=20 > > > > > > Fixes: 7cae1e2b5544 ("clk: sunxi-ng: Add support for the A523/T527 CC= U PLLs") > > > Signed-off-by: Chen-Yu Tsai > > > > Reviewed-by: Jernej Skrabec > > > > Best regards, > > Jernej > > > > > --- > > > drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sun= xi-ng/ccu-sun55i-a523.c > > > index acb532f8361b..20dad06b37ca 100644 > > > --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c > > > +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c > > > @@ -300,7 +300,7 @@ static struct ccu_nm pll_audio0_4x_clk =3D { > > > .m =3D _SUNXI_CCU_DIV(16, 6), > > > .sdm =3D _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24= ), > > > 0x178, BIT(31)), > > > - .min_rate =3D 180000000U, > > > + .min_rate =3D 90000000U, > > > .max_rate =3D 3000000000U, > > > .common =3D { > > > .reg =3D 0x078, > > > > > > > > > > > >=20