Re: [PATCH] bindings: PCI: artpec: correct pci binding example

[Arnd Bergmann <arnd@arndb.de>]

On Friday, July 8, 2016 1:28:10 AM CEST Niklas Cassel wrote:
> From: Niklas Cassel <niklas.cassel@axis.com>
> 
>  - Increase config size. When using a PCIe switch,
>    the previous config size only had room for one device.
>  - Add bus range. Inherited optional property.
>  - Map downstream I/O to PCI address 0. We can map it to any
>    address, but let's be consistent with other drivers.
> 
> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
> ---
>  Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
> index 330a45b..5ecaea1 100644
> --- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
> @@ -24,16 +24,17 @@ Example:
>  		compatible = "axis,artpec6-pcie", "snps,dw-pcie";
>  		reg = <0xf8050000 0x2000
>  		       0xf8040000 0x1000
> -		       0xc0000000 0x1000>;
> +		       0xc0000000 0x2000>;

If this is your config space size

>  		num-lanes = <2>;
> +		bus-range = <0x00 0xff>;

then the bus range looks too large. These two are typically connected.
I couldn't immediately see which config space access function is
used, but if you have 0x1000 bytes per bus, then the bus range matching
a 0x2000 byte config space would be either <0x00 0x01> or <0x00 0x02>
depending whether the root bus is part of that range.

	Arnd