From: Ivan Vecera <ivecera@redhat.com>
To: Jiri Pirko <jiri@resnulli.us>
Cc: netdev@vger.kernel.org,
Prathosh Satish <Prathosh.Satish@microchip.com>,
Vadim Fedorenko <vadim.fedorenko@linux.dev>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Simon Horman <horms@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
Jason Gunthorpe <jgg@ziepe.ca>,
Shannon Nelson <shannon.nelson@amd.com>,
Dave Jiang <dave.jiang@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, Michal Schmidt <mschmidt@redhat.com>,
Petr Oros <poros@redhat.com>
Subject: Re: [PATCH net-next v12 09/14] dpll: zl3073x: Register DPLL devices and pins
Date: Wed, 2 Jul 2025 13:49:22 +0200 [thread overview]
Message-ID: <1848e2f6-a0bb-48e6-9bfc-5ea6cbea2e5c@redhat.com> (raw)
In-Reply-To: <ne36b7ky5cg2g3juejcah7bnvsajihncmpzag3vpjnb3gabz2m@xtxhpfhvfmwl>
On 02. 07. 25 12:57 odp., Jiri Pirko wrote:
> Sun, Jun 29, 2025 at 09:10:44PM +0200, ivecera@redhat.com wrote:
>
> [...]
>
>> +/**
>> + * zl3073x_dpll_device_register - register DPLL device
>> + * @zldpll: pointer to zl3073x_dpll structure
>> + *
>> + * Registers given DPLL device into DPLL sub-system.
>> + *
>> + * Return: 0 on success, <0 on error
>> + */
>> +static int
>> +zl3073x_dpll_device_register(struct zl3073x_dpll *zldpll)
>> +{
>> + struct zl3073x_dev *zldev = zldpll->dev;
>> + u8 dpll_mode_refsel;
>> + int rc;
>> +
>> + /* Read DPLL mode and forcibly selected reference */
>> + rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id),
>> + &dpll_mode_refsel);
>> + if (rc)
>> + return rc;
>> +
>> + /* Extract mode and selected input reference */
>> + zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE,
>> + dpll_mode_refsel);
>
> Who sets this?
WDYM? refsel_mode register? If so this register is populated from
configuration stored in flash inside the chip. And the configuration
is prepared by vendor/OEM.
>> + zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF,
>> + dpll_mode_refsel);
>> +
>> + zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id,
>> + THIS_MODULE);
>> + if (IS_ERR(zldpll->dpll_dev)) {
>> + rc = PTR_ERR(zldpll->dpll_dev);
>> + zldpll->dpll_dev = NULL;
>> +
>> + return rc;
>> + }
>> +
>> + rc = dpll_device_register(zldpll->dpll_dev,
>> + zl3073x_prop_dpll_type_get(zldev, zldpll->id),
>> + &zl3073x_dpll_device_ops, zldpll);
>> + if (rc) {
>> + dpll_device_put(zldpll->dpll_dev);
>> + zldpll->dpll_dev = NULL;
>> + }
>> +
>> + return rc;
>> +}
>
> [...]
>
next prev parent reply other threads:[~2025-07-02 11:49 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-29 19:10 [PATCH net-next v12 00/14] Add Microchip ZL3073x support (part 1) Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 01/14] dt-bindings: dpll: Add DPLL device and pin Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 02/14] dt-bindings: dpll: Add support for Microchip Azurite chip family Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 03/14] dpll: Add basic Microchip ZL3073x support Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 04/14] dpll: zl3073x: Add support for devlink device info Ivan Vecera
2025-07-02 10:25 ` Jiri Pirko
2025-07-02 11:38 ` Ivan Vecera
2025-07-02 11:41 ` Jiri Pirko
2025-07-02 11:52 ` Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 05/14] dpll: zl3073x: Protect operations requiring multiple register accesses Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 06/14] dpll: zl3073x: Fetch invariants during probe Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 07/14] dpll: zl3073x: Add clock_id field Ivan Vecera
2025-07-02 10:31 ` Jiri Pirko
2025-07-02 11:43 ` Ivan Vecera
2025-07-02 12:01 ` Jiri Pirko
2025-07-02 14:51 ` Ivan Vecera
2025-07-03 10:09 ` Jiri Pirko
2025-07-03 10:45 ` Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 08/14] dpll: zl3073x: Read DPLL types and pin properties from system firmware Ivan Vecera
2025-07-02 10:41 ` Jiri Pirko
2025-07-02 11:47 ` Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 09/14] dpll: zl3073x: Register DPLL devices and pins Ivan Vecera
2025-07-02 10:57 ` Jiri Pirko
2025-07-02 11:49 ` Ivan Vecera [this message]
2025-07-02 12:02 ` Jiri Pirko
2025-07-02 12:16 ` Ivan Vecera
2025-07-02 14:12 ` Jiri Pirko
2025-06-29 19:10 ` [PATCH net-next v12 10/14] dpll: zl3073x: Implement input pin selection in manual mode Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 11/14] dpll: zl3073x: Add support to get/set priority on input pins Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 12/14] dpll: zl3073x: Implement input pin state setting in automatic mode Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 13/14] dpll: zl3073x: Add support to get/set frequency on input pins Ivan Vecera
2025-06-29 19:10 ` [PATCH net-next v12 14/14] dpll: zl3073x: Add support to get/set frequency on output pins Ivan Vecera
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