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AJvYcCVQMykha2l/mrLLi0HdAdry9g0gPMFKHUuWOTbfdzduIDp+M/211r5QO0mQRXoXPLxT+wDIWyagZI82yAfzh2HP2NUxGiplo+D5iA== X-Gm-Message-State: AOJu0Yxp3fIOwQrbxKKOnl1AdIelV7ZYh1AUyd8FWFW/3kw8wA+JdkvZ 62yym730FPz+A0pLr8jkXGpHetoEl3fB6E8p5zPiO9YQZO9vOD5ZC7dJoGlskko= X-Google-Smtp-Source: AGHT+IEL9BKhdhIVjKmro2+K35KM05pC7dvn53IR+o/01gtD6rpiQa7LHmKF00AWVjh8Nm0NJ+w8Eg== X-Received: by 2002:adf:d009:0:b0:33e:152a:6b3d with SMTP id t9-20020adfd009000000b0033e152a6b3dmr4871168wrh.31.1709396002115; Sat, 02 Mar 2024 08:13:22 -0800 (PST) Received: from [192.168.0.58] ([176.61.106.68]) by smtp.gmail.com with ESMTPSA id bu28-20020a056000079c00b0033dc7e50488sm7796549wrb.96.2024.03.02.08.13.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 02 Mar 2024 08:13:21 -0800 (PST) Message-ID: <18567989-fb60-49ae-92e6-94e1bc2fa1c7@linaro.org> Date: Sat, 2 Mar 2024 16:13:19 +0000 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] clk: qcom: Add camera clock controller driver for SM8150 Content-Language: en-US To: Satya Priya Kakitapalli , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Abhishek Sahu , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Ajit Pandey , Imran Shaik , Taniya Das , Jagadeesh Kona References: <20240229-camcc-support-sm8150-v1-0-8c28c6c87990@quicinc.com> <20240229-camcc-support-sm8150-v1-4-8c28c6c87990@quicinc.com> From: Bryan O'Donoghue In-Reply-To: <20240229-camcc-support-sm8150-v1-4-8c28c6c87990@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 29/02/2024 5:38 a.m., Satya Priya Kakitapalli wrote: > Add support for the camera clock controller for camera clients > to be able to request for camcc clocks on SM8150 platform. > > Signed-off-by: Satya Priya Kakitapalli > --- > +static int cam_cc_sm8150_probe(struct platform_device *pdev) > +{ > + struct regmap *regmap; > + int ret; > + > + ret = devm_pm_runtime_enable(&pdev->dev); > + if (ret) > + return ret; > + > + ret = pm_runtime_resume_and_get(&pdev->dev); > + if (ret) > + return ret; > + > + regmap = qcom_cc_map(pdev, &cam_cc_sm8150_desc); > + if (IS_ERR(regmap)) { > + pm_runtime_put(&pdev->dev); > + return PTR_ERR(regmap); > + } > + > + clk_trion_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); > + clk_trion_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); > + clk_regera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); > + clk_trion_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); > + clk_trion_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); > + > + /* Keep the critical clock always-on */ > + qcom_branch_set_clk_en(regmap, 0xc1e4); /* cam_cc_gdsc_clk */ Does this clock need to be specified this way ? drivers/clk/qcom/camcc-sc8280xp.c::camcc_gdsc_clk specifies the gdsc clock as a shared op clock. Actually it looks to be register compatible, please try defining titan_top_gdsc as per the example in 8280xp. > + > + ret = qcom_cc_really_probe(pdev, &cam_cc_sm8150_desc, regmap); > + > + pm_runtime_put(&pdev->dev); > + > + return ret; > +} So this is a pattern we keep repeating in the clock probe() functions which I am writing a series to address. There's no need to continue to replicate the bug in new code though. Only switch on always-on clocks if probe succeeds. ret = qcom_cc_really_probe(pdev, &cam_cc_sm8150_desc, regmap); if (ret) goto probe_err; qcom_branch_set_clk_en(regmap, 0xc1e4); /* cam_cc_gdsc_clk */ pm_runtime_put(&pdev->dev); return 0; probe_err: pm_runtime_put_sync(&pdev->dev); Alternatively switch on the always-on clocks before the really_probe() but then roll back in a probe_err: goto probe_err: remap_bits_update(regmap, 0xc1e4, BIT(0), 0); pm_runtime_put_sync(&pdev->dev); There may be corner cases where always-on has to happen before really_probe() I suppose but as a general pattern the above should be how we go. Anyway I suspect the right thing to do is to define a titan_top_gdsc_clk with shared ops to "park" the GDSC clock to 19.2 MHz instead of turning it off. You can get rid of the hard-coded always-on and indeed represent the clock in /sysfs - which is preferable IMO to just whacking registers to keep clocks always-on in probe anyway. Please try to define the titan_top_gdsc_clk as a shared_ops clock instead of hard coding to always on. If that doesn't work for some reason, then please fix your always-on logic in probe() to only make the clock fixed on, if really_probe() succeeds. --- bod