[PATCH v2 00/10] Support for Allwinner V853 SoC

[PATCH v2 00/10] Support for Allwinner V853 SoC

[Andras Szemzo]

V85x is a SoC from Allwinner with video encoding targeted for the field of
IP Camera. It integrates the single CA7 core, and a T-Head E907 RISC-V mcu.
The SoC has the usual Allwinner peripherals and a Vivante NPU.
V853 is a BGA package without DRAM, V851s/V851s3 has the same die with
co-packaged 64MB/128MB DRAM (in a QFN88 package).

This patchset tries to add basical support for the V853 device family.

Changelog - v2:
 - rebased on 6.14-rc1
 - add a needed gate with key support to sunxi clk
 - rewrite the ccu-r driver
 - fix license issues
 - remove the pinctrl binding, as it has beed applied
 - rework the pinctrl driver, use the new sunxi dt based mux support. This new pinctrl
   driver depends on the new sunxi device-tree based mux support patch series [1].
 - remove the new usb phy binding, as the v853's usb phy is very close to d1/a64
 - add a board dts
 - ccu: add module description
 - ccu: fix PLL enable bits, and min multipliers
 - ccu: change PLL flags to CLK_SET_RATE_GATE
 - ccu: use SUNXI_CCU_M_HWS at peripheral PLLs
 - ccu: convert the VIDEO and CSI PLLs from nm type to nkmp according to BSP
 - ccu: cpu axi clk use pointer
 - ccu: fix comments
 - ccu: swap i2s1 and i2s0 bus clocks
 - ccu: fix indentation
 - ccu: fix RST_BUS_SPIF order
 - ccu: convert RST_RISCV_CLK_GATING from reset to gate

[1]: https://lore.kernel.org/linux-sunxi/20241111005750.13071-1-andre.przywara@arm.com/T/

Andras Szemzo (10):
  clk: sunxi-ng: allow key feature in ccu reset and gate
  pinctrl: sunxi: add driver for Allwinner V853
  dt-bindings: clock: sunxi-ng: add compatibles for V853
  clk: sunxi-ng: add CCU drivers for V853
  dt-bindings: power: add V853 ppu bindings
  pmdomain: sunxi: add V853 ppu support
  dt-bindings: phy: allwinner: add v853 usb phy
  phy: allwinner: add v853 usb phy compatible
  ARM: dts: sun8i: add DTSI file for V853
  ARM: dts: sun8i: add DTS file for yuzuki-lizard V851s

 .../clock/allwinner,sun4i-a10-ccu.yaml        |    3 +
 .../phy/allwinner,sun50i-a64-usb-phy.yaml     |    2 +
 .../power/allwinner,sun20i-d1-ppu.yaml        |    1 +
 arch/arm/boot/dts/allwinner/Makefile          |    1 +
 .../boot/dts/allwinner/sun8i-v851s-lizard.dts |  196 +++
 arch/arm/boot/dts/allwinner/sun8i-v853.dtsi   |  656 ++++++++++
 drivers/clk/sunxi-ng/Kconfig                  |   10 +
 drivers/clk/sunxi-ng/Makefile                 |    4 +
 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c       |  120 ++
 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h       |   14 +
 drivers/clk/sunxi-ng/ccu-sun8i-v853.c         | 1145 +++++++++++++++++
 drivers/clk/sunxi-ng/ccu-sun8i-v853.h         |   14 +
 drivers/clk/sunxi-ng/ccu_common.h             |    2 +
 drivers/clk/sunxi-ng/ccu_gate.c               |    6 +
 drivers/clk/sunxi-ng/ccu_gate.h               |   14 +
 drivers/clk/sunxi-ng/ccu_mux.c                |    4 +-
 drivers/clk/sunxi-ng/ccu_reset.c              |    7 +
 drivers/clk/sunxi-ng/ccu_reset.h              |    2 +-
 drivers/phy/allwinner/phy-sun4i-usb.c         |   10 +
 drivers/pinctrl/sunxi/Kconfig                 |    5 +
 drivers/pinctrl/sunxi/Makefile                |    1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c    |   53 +
 drivers/pmdomain/sunxi/sun20i-ppu.c           |   15 +
 .../clock/allwinner,sun8i-v853-ccu.h          |  132 ++
 .../clock/allwinner,sun8i-v853-r-ccu.h        |   16 +
 .../power/allwinner,sun8i-v853-ppu.h          |   10 +
 .../reset/allwinner,sun8i-v853-ccu.h          |   60 +
 .../reset/allwinner,sun8i-v853-r-ccu.h        |   14 +
 28 files changed, 2513 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dts
 create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.h
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c
 create mode 100644 include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h
 create mode 100644 include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h
 create mode 100644 include/dt-bindings/power/allwinner,sun8i-v853-ppu.h
 create mode 100644 include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h
 create mode 100644 include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h

-- 
2.39.5

[PATCH v2 01/10] clk: sunxi-ng: allow key feature in ccu reset and gate

[Andras Szemzo]

Some newer SoCs, like V853 has reset and gate registers, what can be write only
with fixed key value. Move this value from ccu_mux and reuse
in the reset code, and also introduce a new macro to support writing gate
registers with a key.

Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
---
 drivers/clk/sunxi-ng/ccu_common.h |  2 ++
 drivers/clk/sunxi-ng/ccu_gate.c   |  6 ++++++
 drivers/clk/sunxi-ng/ccu_gate.h   | 14 ++++++++++++++
 drivers/clk/sunxi-ng/ccu_mux.c    |  4 +---
 drivers/clk/sunxi-ng/ccu_reset.c  |  7 +++++++
 drivers/clk/sunxi-ng/ccu_reset.h  |  2 +-
 6 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index dd330426a6e5..36132cb8b920 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -23,6 +23,8 @@
 /* MMC timing mode switch bit */
 #define CCU_MMC_NEW_TIMING_MODE		BIT(30)
 
+#define CCU_KEY_VALUE			0x16aa0000
+
 struct device_node;
 
 struct ccu_common {
diff --git a/drivers/clk/sunxi-ng/ccu_gate.c b/drivers/clk/sunxi-ng/ccu_gate.c
index ac52fd6bff67..a7ffaa8d3cb6 100644
--- a/drivers/clk/sunxi-ng/ccu_gate.c
+++ b/drivers/clk/sunxi-ng/ccu_gate.c
@@ -20,6 +20,9 @@ void ccu_gate_helper_disable(struct ccu_common *common, u32 gate)
 	spin_lock_irqsave(common->lock, flags);
 
 	reg = readl(common->base + common->reg);
+	if (common->features & CCU_FEATURE_KEY_FIELD)
+		reg |= CCU_KEY_VALUE;
+
 	writel(reg & ~gate, common->base + common->reg);
 
 	spin_unlock_irqrestore(common->lock, flags);
@@ -44,6 +47,9 @@ int ccu_gate_helper_enable(struct ccu_common *common, u32 gate)
 	spin_lock_irqsave(common->lock, flags);
 
 	reg = readl(common->base + common->reg);
+	if (common->features & CCU_FEATURE_KEY_FIELD)
+		reg |= CCU_KEY_VALUE;
+
 	writel(reg | gate, common->base + common->reg);
 
 	spin_unlock_irqrestore(common->lock, flags);
diff --git a/drivers/clk/sunxi-ng/ccu_gate.h b/drivers/clk/sunxi-ng/ccu_gate.h
index dc05ce06737a..37e21fcdd931 100644
--- a/drivers/clk/sunxi-ng/ccu_gate.h
+++ b/drivers/clk/sunxi-ng/ccu_gate.h
@@ -68,6 +68,20 @@ struct ccu_gate {
 		}							\
 	}
 
+#define SUNXI_CCU_GATE_HWS_WITH_KEY(_struct, _name, _parent, _reg,	\
+				       _gate, _flags)			\
+	struct ccu_gate _struct = {					\
+		.enable	= _gate,					\
+		.common	= {						\
+			.reg		= _reg,				\
+			.features	= CCU_FEATURE_KEY_FIELD,	\
+			.hw.init	= CLK_HW_INIT_HWS(_name,	\
+							  _parent,	\
+							  &ccu_gate_ops, \
+							  _flags),	\
+		}							\
+	}
+
 #define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg,	\
 				       _gate, _prediv, _flags)		\
 	struct ccu_gate _struct = {					\
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index d7ffbdeee9e0..127269ab20ea 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -12,8 +12,6 @@
 #include "ccu_gate.h"
 #include "ccu_mux.h"
 
-#define CCU_MUX_KEY_VALUE		0x16aa0000
-
 static u16 ccu_mux_get_prediv(struct ccu_common *common,
 			      struct ccu_mux_internal *cm,
 			      int parent_index)
@@ -196,7 +194,7 @@ int ccu_mux_helper_set_parent(struct ccu_common *common,
 
 	/* The key field always reads as zero. */
 	if (common->features & CCU_FEATURE_KEY_FIELD)
-		reg |= CCU_MUX_KEY_VALUE;
+		reg |= CCU_KEY_VALUE;
 
 	reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift);
 	writel(reg | (index << cm->shift), common->base + common->reg);
diff --git a/drivers/clk/sunxi-ng/ccu_reset.c b/drivers/clk/sunxi-ng/ccu_reset.c
index 55bc7c7cda0f..a9aee35c6617 100644
--- a/drivers/clk/sunxi-ng/ccu_reset.c
+++ b/drivers/clk/sunxi-ng/ccu_reset.c
@@ -9,6 +9,7 @@
 #include <linux/reset-controller.h>
 
 #include "ccu_reset.h"
+#include "ccu_common.h"
 
 static int ccu_reset_assert(struct reset_controller_dev *rcdev,
 			    unsigned long id)
@@ -21,6 +22,9 @@ static int ccu_reset_assert(struct reset_controller_dev *rcdev,
 	spin_lock_irqsave(ccu->lock, flags);
 
 	reg = readl(ccu->base + map->reg);
+	if (map->features & CCU_FEATURE_KEY_FIELD)
+		reg |= CCU_KEY_VALUE;
+
 	writel(reg & ~map->bit, ccu->base + map->reg);
 
 	spin_unlock_irqrestore(ccu->lock, flags);
@@ -39,6 +43,9 @@ static int ccu_reset_deassert(struct reset_controller_dev *rcdev,
 	spin_lock_irqsave(ccu->lock, flags);
 
 	reg = readl(ccu->base + map->reg);
+	if (map->features & CCU_FEATURE_KEY_FIELD)
+		reg |= CCU_KEY_VALUE;
+
 	writel(reg | map->bit, ccu->base + map->reg);
 
 	spin_unlock_irqrestore(ccu->lock, flags);
diff --git a/drivers/clk/sunxi-ng/ccu_reset.h b/drivers/clk/sunxi-ng/ccu_reset.h
index 941276a8ec2e..8da721ac3a7d 100644
--- a/drivers/clk/sunxi-ng/ccu_reset.h
+++ b/drivers/clk/sunxi-ng/ccu_reset.h
@@ -12,9 +12,9 @@
 struct ccu_reset_map {
 	u16	reg;
 	u32	bit;
+	u32	features;
 };
 
-
 struct ccu_reset {
 	void __iomem			*base;
 	const struct ccu_reset_map	*reset_map;
-- 
2.39.5

[PATCH v2 02/10] pinctrl: sunxi: add driver for Allwinner V853

[Andras Szemzo]

The V853 family has multiple package variants, from BGA to QFN88.
The latter has co-packaged DRAM and fewer pins, and less features (pin muxes).
All family members can be supported by a single driver, as the available pins
with allowed muxes is the same across the devices.

This new pinctrl driver depends on the new sunxi device-tree based mux support
patch series [1].

[1]: https://lore.kernel.org/linux-sunxi/20241111005750.13071-1-andre.przywara@arm.com/T/

Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
---
 drivers/pinctrl/sunxi/Kconfig              |  5 ++
 drivers/pinctrl/sunxi/Makefile             |  1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c | 53 ++++++++++++++++++++++
 3 files changed, 59 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index a78fdbbdfc0c..fac9c61039e2 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -81,6 +81,11 @@ config PINCTRL_SUN9I_A80_R
 	default MACH_SUN9I
 	select PINCTRL_SUNXI
 
+config PINCTRL_SUN8I_V853
+	bool "Support for the Allwinner V853/V851S/V851SE PIO"
+	default MACH_SUN8I
+	select PINCTRL_SUNXI
+
 config PINCTRL_SUN20I_D1
 	bool "Support for the Allwinner D1 PIO"
 	default MACH_SUN8I || (RISCV && ARCH_SUNXI)
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 2ff5a55927ad..8937b56b2ef4 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A83T_R)	+= pinctrl-sun8i-a83t-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3_R)	+= pinctrl-sun8i-h3-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_V3S)		+= pinctrl-sun8i-v3s.o
+obj-$(CONFIG_PINCTRL_SUN8I_V853)	+= pinctrl-sun8i-v853.o
 obj-$(CONFIG_PINCTRL_SUN20I_D1)		+= pinctrl-sun20i-d1.o
 obj-$(CONFIG_PINCTRL_SUN50I_H5)		+= pinctrl-sun50i-h5.o
 obj-$(CONFIG_PINCTRL_SUN50I_H6)		+= pinctrl-sun50i-h6.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c
new file mode 100644
index 000000000000..fb2112ee12d0
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner V853 SoC pinctrl driver.
+ *
+ * Copyright (c) 2025 Andras Szemzo <szemzo.andras@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const u8 v853_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] =
+/*	  PA  PB  PC  PD  PE  PF  PG  PH  PI  */
+	{ 22,  0, 12, 23, 18,  7,  8, 16,  5 };
+
+static const unsigned int v853_irq_bank_map[] = { 0, 2, 3, 4, 5, 6, 7, 8 };
+
+static const u8 v853_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
+/*	  PA  PB  PC  PD  PE  PF  PG  PH  PI */
+	{ 14,  0, 14, 14, 14, 14, 14, 14, 14 };
+
+static struct sunxi_pinctrl_desc v853_pinctrl_data = {
+	.irq_banks = ARRAY_SIZE(v853_irq_bank_map),
+	.irq_bank_map = v853_irq_bank_map,
+	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
+};
+
+static int v853_pinctrl_probe(struct platform_device *pdev)
+{
+	return sunxi_pinctrl_dt_table_init(pdev, v853_nr_bank_pins,
+					   v853_irq_bank_muxes,
+					   &v853_pinctrl_data,
+					   SUNXI_PINCTRL_NEW_REG_LAYOUT |
+					   SUNXI_PINCTRL_ELEVEN_BANKS);
+}
+
+static const struct of_device_id v853_pinctrl_match[] = {
+	{ .compatible = "allwinner,sun8i-v853-pinctrl", },
+	{}
+};
+
+static struct platform_driver v853_pinctrl_driver = {
+	.probe	= v853_pinctrl_probe,
+	.driver	= {
+		.name		= "sun8i-v853-pinctrl",
+		.of_match_table	= v853_pinctrl_match,
+	},
+};
+builtin_platform_driver(v853_pinctrl_driver);
-- 
2.39.5

[PATCH v2 03/10] dt-bindings: clock: sunxi-ng: add compatibles for V853

[Andras Szemzo]

V853 has 2 CCUs, add compatible strings for it.

Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
---
 .../clock/allwinner,sun4i-a10-ccu.yaml        |   3 +
 .../clock/allwinner,sun8i-v853-ccu.h          | 132 ++++++++++++++++++
 .../clock/allwinner,sun8i-v853-r-ccu.h        |  16 +++
 .../reset/allwinner,sun8i-v853-ccu.h          |  60 ++++++++
 .../reset/allwinner,sun8i-v853-r-ccu.h        |  14 ++
 5 files changed, 225 insertions(+)
 create mode 100644 include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h
 create mode 100644 include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h
 create mode 100644 include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h
 create mode 100644 include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h

diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
index 1690b9d99c3d..9369d62284ed 100644
--- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
+++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
@@ -33,6 +33,8 @@ properties:
       - allwinner,sun8i-r40-ccu
       - allwinner,sun8i-v3-ccu
       - allwinner,sun8i-v3s-ccu
+      - allwinner,sun8i-v853-ccu
+      - allwinner,sun8i-v853-r-ccu
       - allwinner,sun9i-a80-ccu
       - allwinner,sun20i-d1-ccu
       - allwinner,sun20i-d1-r-ccu
@@ -103,6 +105,7 @@ else:
       compatible:
         enum:
           - allwinner,sun20i-d1-ccu
+          - allwinner,sun8i-v853-ccu
           - allwinner,sun50i-a100-ccu
           - allwinner,sun50i-h6-ccu
           - allwinner,sun50i-h616-ccu
diff --git a/include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h b/include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h
new file mode 100644
index 000000000000..cf56c168e1cd
--- /dev/null
+++ b/include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h
@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ALLWINNER_SUN8I_V85X_CCU_H_
+#define _DT_BINDINGS_CLK_ALLWINNER_SUN8I_V85X_CCU_H_
+
+#define CLK_OSC12M		0
+#define CLK_PLL_CPU		1
+#define CLK_PLL_DDR		2
+#define CLK_PLL_PERIPH_4X	3
+#define CLK_PLL_PERIPH_2X	4
+#define CLK_PLL_PERIPH_800M	5
+#define CLK_PLL_PERIPH_480M	6
+#define CLK_PLL_PERIPH_600M	7
+#define CLK_PLL_PERIPH_400M	8
+#define CLK_PLL_PERIPH_300M	9
+#define CLK_PLL_PERIPH_200M	10
+#define CLK_PLL_PERIPH_160M	11
+#define CLK_PLL_PERIPH_150M	12
+#define CLK_PLL_VIDEO_4X	13
+#define CLK_PLL_VIDEO_2X	14
+#define CLK_PLL_VIDEO_1X	15
+#define CLK_PLL_CSI_4X		16
+#define CLK_PLL_AUDIO_DIV2	17
+#define CLK_PLL_AUDIO_DIV5	18
+#define CLK_PLL_AUDIO_4X	19
+#define CLK_PLL_AUDIO_1X	20
+#define CLK_PLL_NPU_4X		21
+#define CLK_CPU			22
+#define CLK_CPU_AXI		23
+#define CLK_CPU_APB		24
+#define CLK_AHB			25
+#define CLK_APB0		26
+#define CLK_APB1		27
+#define CLK_MBUS		28
+#define CLK_DE			29
+#define CLK_BUS_DE		30
+#define CLK_G2D			31
+#define CLK_BUS_G2D		32
+#define CLK_CE			33
+#define CLK_BUS_CE		34
+#define CLK_VE			35
+#define CLK_BUS_VE		36
+#define CLK_NPU			37
+#define CLK_BUS_NPU		38
+#define CLK_BUS_DMA		39
+#define CLK_BUS_MSGBOX0		40
+#define CLK_BUS_MSGBOX1		41
+#define CLK_BUS_SPINLOCK	42
+#define CLK_BUS_HSTIMER		43
+#define CLK_AVS			44
+#define CLK_BUS_DBG		45
+#define CLK_BUS_PWM		46
+#define CLK_BUS_IOMMU		47
+#define CLK_DRAM		48
+#define CLK_MBUS_DMA		49
+#define CLK_MBUS_VE		50
+#define CLK_MBUS_CE		51
+#define CLK_MBUS_CSI		52
+#define CLK_MBUS_ISP		53
+#define CLK_MBUS_G2D		54
+#define CLK_BUS_DRAM		55
+#define CLK_MMC0		56
+#define CLK_MMC1		57
+#define CLK_MMC2		58
+#define CLK_BUS_MMC0		59
+#define CLK_BUS_MMC1		60
+#define CLK_BUS_MMC2		61
+#define CLK_BUS_UART0		62
+#define CLK_BUS_UART1		63
+#define CLK_BUS_UART2		64
+#define CLK_BUS_UART3		65
+#define CLK_BUS_I2C0		66
+#define CLK_BUS_I2C1		67
+#define CLK_BUS_I2C2		68
+#define CLK_BUS_I2C3		69
+#define CLK_BUS_I2C4		70
+#define CLK_SPI0		71
+#define CLK_SPI1		72
+#define CLK_SPI2		73
+#define CLK_SPI3		74
+#define CLK_BUS_SPI0		75
+#define CLK_BUS_SPI1		76
+#define CLK_BUS_SPI2		77
+#define CLK_BUS_SPI3		78
+#define CLK_SPIF		79
+#define CLK_BUS_SPIF		80
+#define CLK_EMAC_25M		81
+#define CLK_BUS_EMAC		82
+#define CLK_BUS_GPADC		83
+#define CLK_BUS_THS		84
+#define CLK_I2S0		85
+#define CLK_I2S1		86
+#define CLK_BUS_I2S0		87
+#define CLK_BUS_I2S1		88
+#define CLK_DMIC		89
+#define CLK_BUS_DMIC		90
+#define CLK_AUDIO_CODEC_DAC	91
+#define CLK_AUDIO_CODEC_ADC	92
+#define CLK_BUS_AUDIO_CODEC	93
+#define CLK_USB_OHCI		94
+#define CLK_BUS_OHCI		95
+#define CLK_BUS_EHCI		96
+#define CLK_BUS_OTG		97
+#define CLK_BUS_DPSS_TOP	98
+#define CLK_MIPI_DSI		99
+#define CLK_BUS_MIPI_DSI	100
+#define CLK_TCON_LCD		101
+#define CLK_BUS_TCON_LCD	102
+#define CLK_CSI_TOP		103
+#define CLK_CSI_MCLK0		104
+#define CLK_CSI_MCLK1		105
+#define CLK_CSI_MCLK2		106
+#define CLK_BUS_CSI		107
+#define CLK_BUS_WIEGAND		108
+#define CLK_RISCV		109
+#define CLK_RISCV_AXI		110
+#define CLK_RISCV_CORE_GATE	111
+#define CLK_RISCV_CFG_GATE	112
+#define CLK_FANOUT_24M		113
+#define CLK_FANOUT_12M		114
+#define CLK_FANOUT_16M		115
+#define CLK_FANOUT_25M		116
+#define CLK_FANOUT_27M		117
+#define CLK_FANOUT_PCLK		118
+#define CLK_FANOUT0		119
+#define CLK_FANOUT1		120
+#define CLK_FANOUT2		121
+
+#endif
diff --git a/include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h b/include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h
new file mode 100644
index 000000000000..48fe598b7bd8
--- /dev/null
+++ b/include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ALLWINNER_SUN8I_V853_R_CCU_H_
+#define _DT_BINDINGS_CLK_ALLWINNER_SUN8I_V853_R_CCU_H_
+
+#define CLK_R_AHB		0
+#define CLK_R_APB0		1
+#define CLK_BUS_R_TWD		2
+#define CLK_BUS_R_PPU		3
+#define CLK_BUS_R_RTC		4
+#define CLK_BUS_R_CPUCFG	5
+
+#endif
diff --git a/include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h b/include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h
new file mode 100644
index 000000000000..e258117518aa
--- /dev/null
+++ b/include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_RST_ALLWINNER_SUN8I_V85X_CCU_H_
+#define _DT_BINDINGS_RST_ALLWINNER_SUN8I_V85X_CCU_H_
+
+#define RST_MBUS		0
+#define RST_BUS_DE		1
+#define RST_BUS_G2D		2
+#define RST_BUS_CE		3
+#define RST_BUS_VE		4
+#define RST_BUS_NPU		5
+#define RST_BUS_DMA		6
+#define RST_BUS_MSGBOX0		7
+#define RST_BUS_MSGBOX1		8
+#define RST_BUS_SPINLOCK	9
+#define RST_BUS_HSTIMER		10
+#define RST_BUS_DBG		11
+#define RST_BUS_PWM		12
+#define RST_BUS_DRAM		13
+#define RST_BUS_MMC0		14
+#define RST_BUS_MMC1		15
+#define RST_BUS_MMC2		16
+#define RST_BUS_UART0		17
+#define RST_BUS_UART1		18
+#define RST_BUS_UART2		19
+#define RST_BUS_UART3		20
+#define RST_BUS_I2C0		21
+#define RST_BUS_I2C1		22
+#define RST_BUS_I2C2		23
+#define RST_BUS_I2C3		24
+#define RST_BUS_I2C4		25
+#define RST_BUS_SPI0		26
+#define RST_BUS_SPI1		27
+#define RST_BUS_SPI2		28
+#define RST_BUS_SPI3		29
+#define RST_BUS_SPIF		30
+#define RST_BUS_EMAC		31
+#define RST_BUS_GPADC		32
+#define RST_BUS_THS		33
+#define RST_BUS_I2S0		34
+#define RST_BUS_I2S1		35
+#define RST_BUS_DMIC		36
+#define RST_BUS_AUDIO_CODEC	37
+#define RST_USB_PHY		38
+#define RST_BUS_OHCI		39
+#define RST_BUS_EHCI		40
+#define RST_BUS_OTG		41
+#define RST_BUS_DPSS_TOP	42
+#define RST_BUS_MIPI_DSI	43
+#define RST_BUS_TCON_LCD	44
+#define RST_BUS_CSI		45
+#define RST_BUS_WIEGAND		46
+#define RST_RISCV_SYS_APB	47
+#define RST_RISCV_SOFT		48
+#define RST_RISCV_CFG		49
+
+#endif
diff --git a/include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h b/include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h
new file mode 100644
index 000000000000..57629d635115
--- /dev/null
+++ b/include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_RST_ALLWINNER_SUN8I_V853_R_CCU_H_
+#define _DT_BINDINGS_RST_ALLWINNER_SUN8I_V853_R_CCU_H_
+
+#define RST_BUS_R_TWD		0
+#define RST_BUS_R_PPU		1
+#define RST_BUS_R_RTC		2
+#define RST_BUS_R_CPUCFG	3
+
+#endif
-- 
2.39.5

[PATCH v2 04/10] clk: sunxi-ng: add CCU drivers for V853

[Andras Szemzo]

V853 has similar gates/resets like existing Allwinner SOCs. Add support for it's CCU and PRCM CCU.

Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
---
 drivers/clk/sunxi-ng/Kconfig            |   10 +
 drivers/clk/sunxi-ng/Makefile           |    4 +
 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c |  120 +++
 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h |   14 +
 drivers/clk/sunxi-ng/ccu-sun8i-v853.c   | 1145 +++++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-sun8i-v853.h   |   14 +
 6 files changed, 1307 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.h

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index b547198a2c65..e257373177e0 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -12,6 +12,16 @@ config SUNIV_F1C100S_CCU
 	default y
 	depends on MACH_SUNIV || COMPILE_TEST
 
+config SUN8I_V853_CCU
+	tristate "Support for the Allwinner V853/V851s/V851SE CCU"
+	default MACH_SUN8I
+	depends on MACH_SUN8I || COMPILE_TEST
+
+config SUN8I_V853_R_CCU
+	tristate "Support for the Allwinner V853/V851s/V851SE PRCM CCU"
+	default MACH_SUN8I
+	depends on MACH_SUN8I || COMPILE_TEST
+
 config SUN20I_D1_CCU
 	tristate "Support for the Allwinner D1/R528/T113 CCU"
 	default y
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 6b3ae2b620db..b87928462e15 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -25,6 +25,8 @@ sunxi-ccu-y			+= ccu_mp.o
 
 # SoC support
 obj-$(CONFIG_SUNIV_F1C100S_CCU)	+= suniv-f1c100s-ccu.o
+obj-$(CONFIG_SUN8I_V853_CCU)	+= sun8i-v853-ccu.o
+obj-$(CONFIG_SUN8I_V853_R_CCU)	+= sun8i-v853-r-ccu.o
 obj-$(CONFIG_SUN20I_D1_CCU)	+= sun20i-d1-ccu.o
 obj-$(CONFIG_SUN20I_D1_R_CCU)	+= sun20i-d1-r-ccu.o
 obj-$(CONFIG_SUN50I_A64_CCU)	+= sun50i-a64-ccu.o
@@ -50,6 +52,8 @@ obj-$(CONFIG_SUN9I_A80_CCU)	+= sun9i-a80-de-ccu.o
 obj-$(CONFIG_SUN9I_A80_CCU)	+= sun9i-a80-usb-ccu.o
 
 suniv-f1c100s-ccu-y		+= ccu-suniv-f1c100s.o
+sun8i-v853-ccu-y		+= ccu-sun8i-v853.o
+sun8i-v853-r-ccu-y		+= ccu-sun8i-v853-r.o
 sun20i-d1-ccu-y			+= ccu-sun20i-d1.o
 sun20i-d1-r-ccu-y		+= ccu-sun20i-d1-r.o
 sun50i-a64-ccu-y		+= ccu-sun50i-a64.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
new file mode 100644
index 000000000000..bd60e00cda7f
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
+ *
+ * Based on ccu-sun20i-d1-r.c by Samuel Holland.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+
+#include "ccu-sun8i-v853-r.h"
+
+static const struct clk_parent_data r_ahb_apb0_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .fw_name = "losc" },
+	{ .fw_name = "iosc" },
+	{ .fw_name = "pll-periph" },
+	{ .fw_name = "pll-audio" }
+};
+
+static SUNXI_CCU_MP_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
+				  r_ahb_apb0_parents, 0x000,
+				  0, 5,		/* M */
+				  8, 2,		/* P */
+				  24, 3,	/* mux */
+				  0);
+static const struct clk_hw *r_ahb_hw = &r_ahb_clk.common.hw;
+
+static SUNXI_CCU_MP_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
+				  r_ahb_apb0_parents, 0x00c,
+				  0, 5,		/* M */
+				  8, 2,		/* P */
+				  24, 3,	/* mux */
+				  0);
+static const struct clk_hw *r_apb0_hw = &r_apb0_clk.common.hw;
+
+static SUNXI_CCU_GATE_HWS(bus_r_twd_clk, "bus-r-twd", &r_apb0_hw, 
+			  0x12c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_hw,
+			  0x1ac, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_r_rtc_clk, "bus-r-rtc", &r_ahb_hw,
+			  0x20c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_r_cpucfg_clk, "bus-r-cpucfg", &r_apb0_hw,
+			  0x22c, BIT(0), 0);
+
+static struct ccu_common *sun8i_v853_r_ccu_clks[] = {
+	&r_ahb_clk.common,
+	&r_apb0_clk.common,
+	&bus_r_twd_clk.common,
+	&bus_r_ppu_clk.common,
+	&bus_r_rtc_clk.common,
+	&bus_r_cpucfg_clk.common,
+};
+
+static struct clk_hw_onecell_data sun8i_v853_r_hw_clks = {
+	.num	= CLK_NUMBER,
+	.hws	= {
+		[CLK_R_AHB]		= &r_ahb_clk.common.hw,
+		[CLK_R_APB0]		= &r_apb0_clk.common.hw,
+		[CLK_BUS_R_TWD]		= &bus_r_twd_clk.common.hw,
+		[CLK_BUS_R_PPU]		= &bus_r_ppu_clk.common.hw,
+		[CLK_BUS_R_RTC]		= &bus_r_rtc_clk.common.hw,
+		[CLK_BUS_R_CPUCFG]	= &bus_r_cpucfg_clk.common.hw,
+	},
+};
+
+static const struct ccu_reset_map sun8i_v853_r_ccu_resets[] = {
+	[RST_BUS_R_TWD]		= { 0x12c, BIT(16) },
+	[RST_BUS_R_PPU]		= { 0x1ac, BIT(16) },
+	[RST_BUS_R_RTC]		= { 0x20c, BIT(16) },
+	[RST_BUS_R_CPUCFG]	= { 0x22c, BIT(16) },
+};
+
+static const struct sunxi_ccu_desc sun8i_v853_r_ccu_desc = {
+	.ccu_clks	= sun8i_v853_r_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_v853_r_ccu_clks),
+
+	.hw_clks	= &sun8i_v853_r_hw_clks,
+
+	.resets		= sun8i_v853_r_ccu_resets,
+	.num_resets	= ARRAY_SIZE(sun8i_v853_r_ccu_resets),
+};
+
+static int sun8i_v853_r_ccu_probe(struct platform_device *pdev)
+{
+	void __iomem *reg;
+
+	reg = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(reg))
+		return PTR_ERR(reg);
+
+	return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_v853_r_ccu_desc);
+}
+
+static const struct of_device_id sun8i_v853_r_ccu_ids[] = {
+	{ .compatible = "allwinner,sun8i-v853-r-ccu" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, sun8i_v853_r_ccu_ids);
+
+static struct platform_driver sun8i_v853_r_ccu_driver = {
+	.probe	= sun8i_v853_r_ccu_probe,
+	.driver	= {
+		.name			= "sun8i-v853-r-ccu",
+		.suppress_bind_attrs	= true,
+		.of_match_table		= sun8i_v853_r_ccu_ids,
+	},
+};
+module_platform_driver(sun8i_v853_r_ccu_driver);
+
+MODULE_IMPORT_NS("SUNXI_CCU");
+MODULE_DESCRIPTION("Support for the Allwinner V853 PRCM CCU");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
new file mode 100644
index 000000000000..2c6cc7b6f251
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
+ */
+
+#ifndef _CCU_SUN8I_V853_R_H
+#define _CCU_SUN8I_V853_R_H
+
+#include <dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h>
+#include <dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h>
+
+#define CLK_NUMBER		(CLK_BUS_R_CPUCFG + 1)
+
+#endif
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853.c b/drivers/clk/sunxi-ng/ccu-sun8i-v853.c
new file mode 100644
index 000000000000..4b32f3a913cf
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853.c
@@ -0,0 +1,1145 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
+ *
+ * Based on ccu-sun20i-d1.c by Samuel Holland.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "../clk.h"
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun8i-v853.h"
+
+static const struct clk_parent_data osc24M[] = {
+	{ .fw_name = "hosc" }
+};
+
+/*
+ * For the CPU PLL, the output divider is described as "only for testing"
+ * in the user manual. So it's not modelled and forced to 0.
+ */
+#define SUN8I_V853_PLL_CPU_REG		0x000
+
+static struct ccu_mult pll_cpu_clk = {
+	.enable		= BIT(27),
+	.lock		= BIT(28),
+	.mult		= _SUNXI_CCU_MULT_MIN(8, 8, 11),
+	.common		= {
+		.reg		= 0x000,
+		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-cpu", osc24M,
+							   &ccu_mult_ops,
+							   CLK_SET_RATE_GATE),
+	},
+};
+
+/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
+#define SUN8I_V853_PLL_DDR_REG		0x010
+static struct ccu_nkmp pll_ddr_clk = {
+	.enable		= BIT(27),
+	.lock		= BIT(28),
+	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 11),
+	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
+	.p		= _SUNXI_CCU_DIV(0, 1), /* output divider */
+	.common		= {
+		.reg		= 0x010,
+		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-ddr", osc24M,
+							   &ccu_nkmp_ops,
+							   CLK_SET_RATE_GATE),
+	},
+};
+
+#define SUN8I_V853_PLL_PERIPH_REG	0x020
+static struct ccu_nm pll_periph_4x_clk = {
+	.enable		= BIT(27),
+	.lock		= BIT(28),
+	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 11),
+	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
+	.common		= {
+		.reg		= 0x020,
+		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-periph-4x", osc24M,
+							   &ccu_nm_ops,
+							   CLK_SET_RATE_GATE),
+	},
+};
+
+static const struct clk_hw *pll_periph_4x_hws[] = {
+	&pll_periph_4x_clk.common.hw
+};
+
+static SUNXI_CCU_M_HWS(pll_periph_2x_clk, "pll-periph-2x", pll_periph_4x_hws,
+		       0x020, 16, 3, 0);
+
+static SUNXI_CCU_M_HWS(pll_periph_800M_clk, "pll-periph-800M", pll_periph_4x_hws,
+		       0x020, 20, 3, 0);
+
+static SUNXI_CCU_M_HWS(pll_periph_480M_clk, "pll-periph-480M", pll_periph_4x_hws,
+		       0x020, 2, 3, 0);
+
+static CLK_FIXED_FACTOR_HW(pll_periph_600M_clk, "pll-periph-600M",
+			   &pll_periph_2x_clk.common.hw, 2, 1, 0);
+
+static CLK_FIXED_FACTOR_HW(pll_periph_400M_clk, "pll-periph-400M",
+			   &pll_periph_2x_clk.common.hw, 3, 1, 0);
+
+static CLK_FIXED_FACTOR_HW(pll_periph_300M_clk, "pll-periph-300M",
+			   &pll_periph_600M_clk.hw, 2, 1, 0);
+
+static CLK_FIXED_FACTOR_HW(pll_periph_200M_clk, "pll-periph-200M",
+			   &pll_periph_400M_clk.hw, 2, 1, 0);
+
+static CLK_FIXED_FACTOR_HW(pll_periph_160M_clk, "pll-periph-160M",
+			   &pll_periph_480M_clk.common.hw, 3, 1, 0);
+
+static CLK_FIXED_FACTOR_HW(pll_periph_150M_clk, "pll-periph-150M",
+			   &pll_periph_300M_clk.hw, 2, 1, 0);
+
+/*
+ * For Video PLLs, the output divider is described as "only for testing"
+ * in the user manual.
+ */
+#define SUN8I_V853_PLL_VIDEO_REG	0x040
+static struct ccu_nkmp pll_video_4x_clk = {
+	.enable		= BIT(27),
+	.lock		= BIT(28),
+	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 11),
+	.p		= _SUNXI_CCU_DIV(1, 1), /* input divider */
+	.common		= {
+		.reg		= 0x040,
+		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-video-4x", osc24M,
+							   &ccu_nkmp_ops,
+							   CLK_SET_RATE_GATE),
+	},
+};
+
+static const struct clk_hw *pll_video_4x_hws[] = {
+	&pll_video_4x_clk.common.hw
+};
+static CLK_FIXED_FACTOR_HWS(pll_video_2x_clk, "pll-video-2x",
+			    pll_video_4x_hws, 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_video_1x_clk, "pll-video-1x",
+			    pll_video_4x_hws, 4, 1, CLK_SET_RATE_PARENT);
+
+
+/*
+ * For CSI PLLs, the output divider is described as "only for testing"
+ * in the user manual.
+ */
+#define SUN8I_V853_PLL_CSI_REG		0x048
+static struct ccu_nkmp pll_csi_4x_clk = {
+	.enable		= BIT(27),
+	.lock		= BIT(28),
+	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 11),
+	.p		= _SUNXI_CCU_DIV(1, 1), /* input divider */
+	.common		= {
+		.reg		= 0x048,
+		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-csi-4x", osc24M,
+							   &ccu_nkmp_ops,
+							   CLK_SET_RATE_GATE),
+	},
+};
+
+static CLK_FIXED_FACTOR_HW(pll_csi_clk, "pll-csi",
+			   &pll_csi_4x_clk.common.hw, 4, 1, CLK_SET_RATE_PARENT);
+
+
+#define SUN8I_V853_PLL_AUDIO_REG	0x078
+static struct ccu_sdm_setting pll_audio_div5_sdm_table[] = {
+	{ .rate = 196608000, .pattern = 0xc001eb85, .m = 5, .n = 40 }, /* 24.576 */
+	{ .rate = 67737600, .pattern = 0xc001288d, .m = 8, .n = 22 }, /* 22.5792 */
+};
+
+static struct ccu_nm pll_audio_div5_clk = {
+	.enable		= BIT(27),
+	.lock           = BIT(28),
+	.n              = _SUNXI_CCU_MULT(8, 8),
+	.m              = _SUNXI_CCU_DIV(20, 3),
+	.sdm            = _SUNXI_CCU_SDM(pll_audio_div5_sdm_table,
+				    BIT(24), 0x0178, BIT(31)),
+	.common         = {
+		.reg            = 0x0078,
+		.features       = CCU_FEATURE_SIGMA_DELTA_MOD,
+		.hw.init        = CLK_HW_INIT_PARENTS_DATA("pll-audio-div5", osc24M,
+							   &ccu_nm_ops,
+							   CLK_SET_RATE_UNGATE),
+	},
+};
+
+static const struct clk_hw *pll_audio_div5_hws[] = {
+	&pll_audio_div5_clk.common.hw
+};
+
+static SUNXI_CCU_M_HWS(pll_audio_1x_clk, "pll-audio-1x", pll_audio_div5_hws,
+		       0xe00, 0, 5, CLK_SET_RATE_PARENT);
+
+/* pll-audio-div2 and pll-audio-4x not used, because pll-audio-1x can cover 
+ * 22.5792M and 24.576M 
+ */
+static SUNXI_CCU_M(pll_audio_div2_clk, "pll-audio-div2", "pll-audio",
+		   0x078, 16, 3, 0);
+static SUNXI_CCU_M(pll_audio_4x_clk, "pll-audio-4x", "pll-audio-div2",
+		   0xe00, 5, 5, 0);
+
+/*
+ * For the NPU PLL, the output divider is described as "only for testing"
+ * in the user manual.
+ */
+#define SUN8I_V853_PLL_NPU_REG		0x080
+static struct ccu_nkmp pll_npu_4x_clk = {
+	.enable		= BIT(27),
+	.lock		= BIT(28),
+	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 11),
+	.p		= _SUNXI_CCU_DIV(1, 1), /* input divider */
+	.common		= {
+		.reg		= 0x080,
+		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-npu-4x", osc24M,
+							   &ccu_nkmp_ops,
+							   CLK_SET_RATE_UNGATE),
+	},
+};
+
+/*
+ * The CPU gate is not modelled - it is in a separate register (0x504)
+ * and has a special key field. The clock must not be gated anyway by
+ * the kernel.
+ */
+static const struct clk_parent_data cpu_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .fw_name = "losc" },
+	{ .fw_name = "iosc" },
+	{ .hw = &pll_cpu_clk.common.hw },
+	{ .hw = &pll_periph_600M_clk.hw },
+	{ .hw = &pll_periph_800M_clk.common.hw },
+};
+
+/*
+ * There is a P factor (PLL_OUT_EXT_DIVP[17:16]) in this register, but it is not modeled.
+ * The manual states that it should be used only, when the output clock is less than 288 MHz.
+ */
+static SUNXI_CCU_MUX_DATA(cpu_clk, "cpu", cpu_parents,
+			  0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
+
+static const struct clk_hw *cpu_hws[] = { &cpu_clk.common.hw };
+
+static SUNXI_CCU_M_HWS(cpu_axi_clk, "cpu-axi", cpu_hws,
+		       0x500, 0, 2, 0);
+static SUNXI_CCU_M_HWS(cpu_apb_clk, "cpu-apb", cpu_hws,
+		       0x500, 8, 2, 0);
+
+static const struct clk_parent_data ahb_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .fw_name = "losc" },
+	{ .fw_name = "iosc" },
+	{ .hw = &pll_periph_600M_clk.hw },
+};
+static SUNXI_CCU_MP_DATA_WITH_MUX(ahb_clk, "ahb", ahb_parents, 0x510,
+				  0, 5,		/* M */
+				  8, 2,		/* P */
+				  24, 2,	/* mux */
+				  0);
+
+static SUNXI_CCU_MP_DATA_WITH_MUX(apb0_clk, "apb0", ahb_parents, 0x520,
+				  0, 5,		/* M */
+				  8, 2,		/* P */
+				  24, 2,	/* mux */
+				  0);
+
+static SUNXI_CCU_MP_DATA_WITH_MUX(apb1_clk, "apb1", ahb_parents, 0x524,
+				  0, 5,		/* M */
+				  8, 2,		/* P */
+				  24, 2,	/* mux */
+				  0);
+
+static const struct clk_hw *ahb_hws[] = { &ahb_clk.common.hw };
+static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw };
+static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw };
+
+
+static const struct clk_hw *de_g2d_parents[] = {
+	&pll_periph_300M_clk.hw,
+	&pll_video_1x_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_g2d_parents, 0x600,
+				    0, 5,	/* M */
+				    24, 1,	/* mux */
+				    BIT(31),	/* gate */
+				    CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", ahb_hws,
+			  0x60c, BIT(0), 0);
+
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", de_g2d_parents, 0x630,
+				    0, 5,	/* M */
+				    24, 1,	/* mux */
+				    BIT(31),	/* gate */
+				    CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb_hws,
+			  0x63c, BIT(0), 0);
+
+
+static const struct clk_parent_data ce_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .hw = &pll_periph_400M_clk.hw, },
+	{ .hw = &pll_periph_300M_clk.hw, }
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
+				      0, 4,	/* M */
+				      24, 3,	/* mux */
+				      BIT(31),	/* gate */
+				      CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", ahb_hws,
+			  0x68c, BIT(0) | BIT(1), 0);
+
+static const struct clk_hw *ve_parents[] = {
+	&pll_periph_300M_clk.hw,
+	&pll_periph_400M_clk.hw,
+	&pll_periph_480M_clk.common.hw,
+	&pll_npu_4x_clk.common.hw,
+	&pll_video_4x_clk.common.hw,
+	&pll_csi_4x_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
+				    0, 5,	/* M */
+				    24, 3,	/* mux */
+				    BIT(31),	/* gate */
+				    0);
+
+static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", ahb_hws,
+			  0x69c, BIT(0), 0);
+
+
+static const struct clk_hw *npu_parents[] = {
+	&pll_periph_480M_clk.common.hw,
+	&pll_periph_600M_clk.hw,
+	&pll_periph_800M_clk.common.hw,
+	&pll_npu_4x_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0x6e0,
+				    0, 5,	/* M */
+				    24, 3,	/* mux */
+				    BIT(31),	/* gate */
+				    0);
+
+static SUNXI_CCU_GATE_HWS(bus_npu_clk, "bus-npu", ahb_hws,
+			  0x6ec, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", ahb_hws,
+			  0x70c, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", ahb_hws,
+			  0x71c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_msgbox1_clk, "bus-msgbox1", ahb_hws,
+			  0x71c, BIT(1), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", ahb_hws,
+			  0x72c, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", ahb_hws,
+			  0x73c, BIT(0), 0);
+
+static SUNXI_CCU_GATE_DATA(avs_clk, "avs", osc24M,
+			   0x740, BIT(31), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", ahb_hws,
+			  0x78c, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_pwm_clk, "bus-pwm", apb0_hws,
+			  0x7ac, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", ahb_hws,
+			  0x7bc, BIT(0), 0);
+
+static const struct clk_hw *dram_parents[] = {
+	&pll_ddr_clk.common.hw,
+	&pll_periph_2x_clk.common.hw,
+	&pll_periph_800M_clk.common.hw,
+};
+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dram_clk, "dram", dram_parents, 0x800,
+				     0, 5,	/* M */
+				     8, 2,	/* P */
+				     24, 3,	/* mux */
+				     BIT(31), CLK_IS_CRITICAL);
+
+static CLK_FIXED_FACTOR_HW(mbus_clk, "mbus",
+			   &dram_clk.common.hw, 4, 1, 0);
+
+static const struct clk_hw *mbus_hws[] = { &mbus_clk.hw };
+
+static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
+			  0x804, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws,
+			  0x804, BIT(1), 0);
+static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws,
+			  0x804, BIT(2), 0);
+static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws,
+			  0x804, BIT(8), 0);
+static SUNXI_CCU_GATE_HWS(mbus_isp_clk, "mbus-isp", mbus_hws,
+			  0x804, BIT(9), 0);
+static SUNXI_CCU_GATE_HWS(mbus_g2d_clk, "mbus-g2d", mbus_hws,
+			  0x804, BIT(10), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", ahb_hws,
+			  0x80c, BIT(0), CLK_IS_CRITICAL);
+
+
+static const struct clk_parent_data mmc0_mmc1_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .hw = &pll_periph_400M_clk.hw, },
+	{ .hw = &pll_periph_300M_clk.hw, },
+};
+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830,
+				       0, 4,	/* M */
+				       8, 2,	/* P */
+				       24, 3,	/* mux */
+				       BIT(31),	/* gate */
+				       0);
+
+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834,
+				       0, 4,	/* M */
+				       8, 2,	/* P */
+				       24, 3,	/* mux */
+				       BIT(31),	/* gate */
+				       0);
+
+static const struct clk_parent_data mmc2_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .hw = &pll_periph_600M_clk.hw, },
+	{ .hw = &pll_periph_400M_clk.hw, },
+};
+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838,
+				       0, 4,	/* M */
+				       8, 2,	/* P */
+				       24, 3,	/* mux */
+				       BIT(31),	/* gate */
+				       0);
+
+static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", ahb_hws,
+			  0x84c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", ahb_hws,
+			  0x84c, BIT(1), 0);
+static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", ahb_hws,
+			  0x84c, BIT(2), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws,
+			  0x90c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws,
+			  0x90c, BIT(1), 0);
+static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws,
+			  0x90c, BIT(2), 0);
+static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws,
+			  0x90c, BIT(3), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws,
+			  0x91c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws,
+			  0x91c, BIT(1), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws,
+			  0x91c, BIT(2), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws,
+			  0x91c, BIT(3), 0);
+static SUNXI_CCU_GATE_HWS(bus_i2c4_clk, "bus-i2c4", apb1_hws,
+			  0x91c, BIT(4), 0);
+
+static const struct clk_parent_data spi_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .hw = &pll_periph_300M_clk.hw, },
+	{ .hw = &pll_periph_200M_clk.hw, },
+};
+
+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
+				       0, 4,	/* M */
+				       8, 2,	/* P */
+				       24, 3,	/* mux */
+				       BIT(31),	/* gate */
+				       0);
+
+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
+				       0, 4,	/* M */
+				       8, 2,	/* P */
+				       24, 3,	/* mux */
+				       BIT(31),	/* gate */
+				       0);
+
+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi2_clk, "spi2", spi_parents, 0x948,
+				       0, 4,	/* M */
+				       8, 2,	/* P */
+				       24, 3,	/* mux */
+				       BIT(31),	/* gate */
+				       0);
+
+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi3_clk, "spi3", spi_parents, 0x94c,
+				       0, 4,	/* M */
+				       8, 2,	/* P */
+				       24, 3,	/* mux */
+				       BIT(31),	/* gate */
+				       0);
+
+static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", ahb_hws,
+			  0x96c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", ahb_hws,
+			  0x96c, BIT(1), 0);
+static SUNXI_CCU_GATE_HWS(bus_spi2_clk, "bus-spi2", ahb_hws,
+			  0x96c, BIT(2), 0);
+static SUNXI_CCU_GATE_HWS(bus_spi3_clk, "bus-spi3", ahb_hws,
+			  0x96c, BIT(3), 0);
+
+
+static const struct clk_parent_data spif_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .hw = &pll_periph_400M_clk.hw, },
+	{ .hw = &pll_periph_300M_clk.hw, },
+};
+
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(spif_clk, "spif", spif_parents, 0x0950,
+				      0, 4,	/* M */
+				      24, 3,	/* mux */
+				      BIT(31),	/* gate */
+				      CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE_HWS(bus_spif_clk, "bus-spif", ahb_hws,
+			  0x096c, BIT(4), 0);
+
+
+static const struct clk_hw *pll_periph_150M_hws[] = { &pll_periph_150M_clk.hw };
+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25M_clk, "emac-25M", pll_periph_150M_hws,
+				      0x970, BIT(31) | BIT(30), 6, 0);
+
+static SUNXI_CCU_GATE_HWS(bus_emac_clk, "bus-emac", ahb_hws,
+			  0x97c, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_gpadc_clk, "bus-gpadc", apb0_hws,
+			  0x9ec, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", ahb_hws,
+			  0x9fc, BIT(0), 0);
+
+
+static const struct clk_hw *audio_parents[] = {
+	&pll_audio_1x_clk.common.hw,
+	&pll_audio_4x_clk.common.hw,
+};
+
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2s0_clk, "i2s0", audio_parents, 0xa10,
+				    0, 4,	/* M */
+				    24, 1,	/* mux */
+				    BIT(31),	/* gate */
+				    CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2s1_clk, "i2s1", audio_parents, 0xa14,
+				    0, 4,	/* M */
+				    24, 1,	/* mux */
+				    BIT(31),	/* gate */
+				    CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE_HWS(bus_i2s0_clk, "bus-i2s0", ahb_hws,
+			  0xa20, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_i2s1_clk, "bus-i2s1", ahb_hws,
+			  0xa20, BIT(1), 0);
+
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(dmic_clk, "dmic", audio_parents, 0xa40,
+				    0, 4,	/* M */
+				    24, 1,	/* mux */
+				    BIT(31),	/* gate */
+				    CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", ahb_hws,
+			  0xa4c, BIT(0), 0);
+
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(audio_codec_dac_clk, "audio-codec-dac", 
+				    audio_parents, 0xa50,
+				    0, 4,	/* M */
+				    24, 1,	/* mux */
+				    BIT(31),	/* gate */
+				    CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(audio_codec_adc_clk, "audio-codec-adc", 
+				    audio_parents, 0xa54,
+				    0, 4,	/* M */
+				    24, 1,	/* mux */
+				    BIT(31),	/* gate */
+				    CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE_HWS(bus_audio_codec_clk, "bus-audio-codec", apb0_hws,
+			  0xa5c, BIT(0), 0);
+
+/*
+ * There are OHCI 12M clock source selection bits for the USB 2.0 port.
+ * We will force them to 0 (12M divided from 48M).
+ */
+static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
+
+#define SUN8I_V853_USB_CLK_REG		0xa70
+
+static SUNXI_CCU_GATE(usb_ohci_clk, "usb", "osc12M", 0x0a70, BIT(31), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_ohci_clk, "bus-ohci", ahb_hws, 0xa8c, BIT(0), 0);
+static SUNXI_CCU_GATE_HWS(bus_ehci_clk, "bus-ehci", ahb_hws, 0xa8c, BIT(4), 0);
+static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", ahb_hws, 0xa8c, BIT(8), 0);
+
+static SUNXI_CCU_GATE_HWS(bus_dpss_top_clk, "bus-dpss-top", ahb_hws,
+			  0xabc, BIT(0), 0);
+
+
+static const struct clk_parent_data mipi_dsi_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .hw = &pll_periph_200M_clk.hw },
+	{ .hw = &pll_periph_150M_clk.hw },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", mipi_dsi_parents, 
+				      0xb24,
+				      0, 4,	/* M */
+				      24, 3,	/* mux */
+				      BIT(31),	/* gate */
+				      CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE_HWS(bus_mipi_dsi_clk, "bus-mipi-dsi", ahb_hws,
+			  0xb4c, BIT(0), 0);
+
+
+static const struct clk_hw *tcon_lcd_parents[] = {
+	&pll_video_4x_clk.common.hw,
+	&pll_periph_2x_clk.common.hw,
+	&pll_csi_4x_clk.common.hw,
+};
+static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_lcd_clk, "tcon-lcd", tcon_lcd_parents, 
+				     0xb60,
+				     0, 4,	/* M */
+				     8, 2,	/* P */
+				     24, 3,	/* mux */
+				     BIT(31),	/* gate */
+				     CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE_HWS(bus_tcon_lcd_clk, "bus-tcon-lcd", ahb_hws,
+			  0xb7c, BIT(0), 0);
+
+
+static const struct clk_hw *csi_top_parents[] = {
+	&pll_periph_300M_clk.hw,
+	&pll_periph_400M_clk.hw,
+	&pll_video_4x_clk.common.hw,
+	&pll_csi_4x_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents, 0xc04,
+				    0, 5,	/* M */
+				    24, 3,	/* mux */
+				    BIT(31),	/* gate */
+				    0);
+
+
+static const struct clk_parent_data csi_mclk_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .hw = &pll_csi_4x_clk.common.hw },
+	{ .hw = &pll_video_4x_clk.common.hw },
+	{ .hw = &pll_periph_2x_clk.common.hw },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk0_clk, "csi-mclk0", csi_mclk_parents, 
+				      0xc08,
+				      0, 5,	/* M */
+				      24, 3,	/* mux */
+				      BIT(31),	/* gate */
+				      0);
+
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk1_clk, "csi-mclk1", csi_mclk_parents, 
+				      0xc0c,
+				      0, 5,	/* M */
+				      24, 3,	/* mux */
+				      BIT(31),	/* gate */
+				      0);
+
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk2_clk, "csi-mclk2", csi_mclk_parents, 
+				      0xc10,
+				      0, 5,	/* M */
+				      24, 3,	/* mux */
+				      BIT(31),	/* gate */
+				      0);
+
+static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", ahb_hws,
+			  0xc2c, BIT(0), 0);
+
+
+static SUNXI_CCU_GATE_HWS(bus_wiegand_clk, "bus-wiegand", ahb_hws,
+			  0xc7c, BIT(0), 0);
+
+
+static const struct clk_parent_data riscv_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .fw_name = "losc" },
+	{ .fw_name = "iosc" },
+	{ .hw = &pll_periph_600M_clk.hw },
+	{ .hw = &pll_periph_480M_clk.common.hw },
+	{ .hw = &pll_cpu_clk.common.hw },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX(riscv_clk, "riscv-cpu", riscv_parents, 0xd00,
+				 0, 5,	/* M */
+				 24, 3,	/* mux */
+				 CLK_SET_RATE_PARENT);
+
+/* The riscv-axi clk must be divided by at least 2. */
+static struct clk_div_table riscv_axi_table[] = {
+	{ .val = 1, .div = 2 },
+	{ .val = 2, .div = 3 },
+	{ .val = 3, .div = 4 },
+	{ /* Sentinel */ }
+};
+static SUNXI_CCU_DIV_TABLE_HW(riscv_axi_clk, "riscv-axi", &riscv_clk.common.hw,
+			      0xd00, 8, 2, riscv_axi_table, 0);
+
+static SUNXI_CCU_GATE_HWS_WITH_KEY(riscv_core_gate, "riscv-core-gate", ahb_hws,
+				   0xd04, BIT(0), 0);
+
+static SUNXI_CCU_GATE_HWS(riscv_cfg_gate, "riscv-cfg-gate", ahb_hws,
+			  0xd0c, BIT(0), 0);
+
+
+static const struct clk_hw *pll_periph_160M_hws[] = {
+	&pll_periph_160M_clk.hw,
+};
+
+static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
+			   0xf30, BIT(0), 0);
+static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
+				       0xf30, BIT(1), 2, 0);
+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph_160M_hws,
+				      0xf30, BIT(2), 10, 0);
+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph_150M_hws,
+				      0xf30, BIT(3), 6, 0);
+
+
+/* This clock has a second divider that is not modelled and forced to 0. */
+#define SUN8I_V853_FANOUT_27M_REG	0xf34
+static const struct clk_hw *fanout_27M_parents[] = {
+	&pll_video_1x_clk.hw,
+	&pll_csi_clk.hw,
+	&pll_periph_300M_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(fanout_27M_clk, "fanout-27M", 
+				    fanout_27M_parents, 0xf34,
+				    0, 5,	/* M */
+				    24, 2,	/* mux */
+				    BIT(31),	/* gate */
+				    0);
+static SUNXI_CCU_M_HWS_WITH_GATE(fanout_pclk_clk, "fanout-pclk", apb0_hws, 0xf38,
+				 0, 5,		/* M */
+				 BIT(31),	/* gate */
+				 0);
+
+static const struct clk_parent_data fanout_parents[] = {
+	{ .fw_name = "losc" },
+	{ .hw = &fanout_12M_clk.common.hw },
+	{ .hw = &fanout_16M_clk.common.hw },
+	{ .hw = &fanout_24M_clk.common.hw },
+	{ .hw = &fanout_25M_clk.common.hw },
+	{ .hw = &fanout_27M_clk.common.hw },
+	{ .hw = &fanout_pclk_clk.common.hw },
+};
+
+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 0xf3c,
+				    0, 3,	/* mux */
+				    BIT(21),	/* gate */
+				    0);
+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 0xf3c,
+				    3, 3,	/* mux */
+				    BIT(22),	/* gate */
+				    0);
+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 0xf3c,
+				    6, 3,	/* mux */
+				    BIT(23),	/* gate */
+				    0);
+
+
+static struct ccu_common *sun8i_v853_ccu_clks[] = {
+	&pll_cpu_clk.common,
+	&pll_ddr_clk.common,
+	&pll_periph_4x_clk.common,
+	&pll_periph_2x_clk.common,
+	&pll_periph_800M_clk.common,
+	&pll_periph_480M_clk.common,
+	&pll_video_4x_clk.common,
+	&pll_csi_4x_clk.common,
+	&pll_audio_div2_clk.common,
+	&pll_audio_div5_clk.common,
+	&pll_audio_4x_clk.common,
+	&pll_audio_1x_clk.common,
+	&pll_npu_4x_clk.common,
+	&cpu_clk.common,
+	&cpu_axi_clk.common,
+	&cpu_apb_clk.common,
+	&ahb_clk.common,
+	&apb0_clk.common,
+	&apb1_clk.common,
+	&de_clk.common,
+	&bus_de_clk.common,
+	&g2d_clk.common,
+	&bus_g2d_clk.common,
+	&ce_clk.common,
+	&bus_ce_clk.common,
+	&ve_clk.common,
+	&bus_ve_clk.common,
+	&npu_clk.common,
+	&bus_npu_clk.common,
+	&bus_dma_clk.common,
+	&bus_msgbox0_clk.common,
+	&bus_msgbox1_clk.common,
+	&bus_spinlock_clk.common,
+	&bus_hstimer_clk.common,
+	&avs_clk.common,
+	&bus_dbg_clk.common,
+	&bus_pwm_clk.common,
+	&bus_iommu_clk.common,
+	&dram_clk.common,
+	&mbus_dma_clk.common,
+	&mbus_ve_clk.common,
+	&mbus_ce_clk.common,
+	&mbus_csi_clk.common,
+	&mbus_isp_clk.common,
+	&mbus_g2d_clk.common,
+	&bus_dram_clk.common,
+	&mmc0_clk.common,
+	&mmc1_clk.common,
+	&mmc2_clk.common,
+	&bus_mmc0_clk.common,
+	&bus_mmc1_clk.common,
+	&bus_mmc2_clk.common,
+	&bus_uart0_clk.common,
+	&bus_uart1_clk.common,
+	&bus_uart2_clk.common,
+	&bus_uart3_clk.common,
+	&bus_i2c0_clk.common,
+	&bus_i2c1_clk.common,
+	&bus_i2c2_clk.common,
+	&bus_i2c3_clk.common,
+	&bus_i2c4_clk.common,
+	&spi0_clk.common,
+	&spi1_clk.common,
+	&spi2_clk.common,
+	&spi3_clk.common,
+	&bus_spi0_clk.common,
+	&bus_spi1_clk.common,
+	&bus_spi2_clk.common,
+	&bus_spi3_clk.common,
+	&spif_clk.common,
+	&bus_spif_clk.common,
+	&emac_25M_clk.common,
+	&bus_emac_clk.common,
+	&bus_gpadc_clk.common,
+	&bus_ths_clk.common,
+	&usb_ohci_clk.common,
+	&bus_ohci_clk.common,
+	&bus_ehci_clk.common,
+	&bus_otg_clk.common,
+	&i2s0_clk.common,
+	&i2s1_clk.common,
+	&bus_i2s0_clk.common,
+	&bus_i2s1_clk.common,
+	&dmic_clk.common,
+	&bus_dmic_clk.common,
+	&audio_codec_dac_clk.common,
+	&audio_codec_adc_clk.common,
+	&bus_audio_codec_clk.common,
+	&bus_dpss_top_clk.common,
+	&mipi_dsi_clk.common,
+	&bus_mipi_dsi_clk.common,
+	&tcon_lcd_clk.common,
+	&bus_tcon_lcd_clk.common,
+	&csi_top_clk.common,
+	&csi_mclk0_clk.common,
+	&csi_mclk1_clk.common,
+	&csi_mclk2_clk.common,
+	&bus_csi_clk.common,
+	&bus_wiegand_clk.common,
+	&riscv_clk.common,
+	&riscv_axi_clk.common,
+	&riscv_core_gate.common,
+	&riscv_cfg_gate.common,
+	&fanout_24M_clk.common,
+	&fanout_12M_clk.common,
+	&fanout_16M_clk.common,
+	&fanout_25M_clk.common,
+	&fanout_27M_clk.common,
+	&fanout_pclk_clk.common,
+	&fanout0_clk.common,
+	&fanout1_clk.common,
+	&fanout2_clk.common,
+};
+
+static struct clk_hw_onecell_data sun8i_v853_hw_clks = {
+	.num	= CLK_NUMBER,
+	.hws	= {
+		[CLK_OSC12M]            = &osc12M_clk.hw,
+		[CLK_PLL_CPU]		= &pll_cpu_clk.common.hw,
+		[CLK_PLL_DDR]		= &pll_ddr_clk.common.hw,
+		[CLK_PLL_PERIPH_4X]	= &pll_periph_4x_clk.common.hw,
+		[CLK_PLL_PERIPH_2X]	= &pll_periph_2x_clk.common.hw,
+		[CLK_PLL_PERIPH_800M]	= &pll_periph_800M_clk.common.hw,
+		[CLK_PLL_PERIPH_480M]	= &pll_periph_480M_clk.common.hw,
+		[CLK_PLL_PERIPH_600M]	= &pll_periph_600M_clk.hw,
+		[CLK_PLL_PERIPH_400M]	= &pll_periph_400M_clk.hw,
+		[CLK_PLL_PERIPH_300M]	= &pll_periph_300M_clk.hw,
+		[CLK_PLL_PERIPH_200M]	= &pll_periph_200M_clk.hw,
+		[CLK_PLL_PERIPH_160M]	= &pll_periph_160M_clk.hw,
+		[CLK_PLL_PERIPH_150M]	= &pll_periph_150M_clk.hw,
+		[CLK_PLL_VIDEO_4X]	= &pll_video_4x_clk.common.hw,
+		[CLK_PLL_VIDEO_2X]	= &pll_video_2x_clk.hw,
+		[CLK_PLL_VIDEO_1X]	= &pll_video_1x_clk.hw,
+		[CLK_PLL_CSI_4X]	= &pll_csi_4x_clk.common.hw,
+		[CLK_PLL_AUDIO_DIV2]	= &pll_audio_div2_clk.common.hw,
+		[CLK_PLL_AUDIO_DIV5]	= &pll_audio_div5_clk.common.hw,
+		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.common.hw,
+		[CLK_PLL_AUDIO_1X]	= &pll_audio_1x_clk.common.hw,
+		[CLK_PLL_NPU_4X]	= &pll_npu_4x_clk.common.hw,
+		[CLK_CPU]		= &cpu_clk.common.hw,
+		[CLK_CPU_AXI]		= &cpu_axi_clk.common.hw,
+		[CLK_CPU_APB]		= &cpu_apb_clk.common.hw,
+		[CLK_AHB]		= &ahb_clk.common.hw,
+		[CLK_APB0]		= &apb0_clk.common.hw,
+		[CLK_APB1]		= &apb1_clk.common.hw,
+		[CLK_MBUS]		= &mbus_clk.hw,
+		[CLK_DE]		= &de_clk.common.hw,
+		[CLK_BUS_DE]		= &bus_de_clk.common.hw,
+		[CLK_G2D]		= &g2d_clk.common.hw,
+		[CLK_BUS_G2D]		= &bus_g2d_clk.common.hw,
+		[CLK_CE]		= &ce_clk.common.hw,
+		[CLK_BUS_CE]		= &bus_ce_clk.common.hw,
+		[CLK_VE]		= &ve_clk.common.hw,
+		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
+		[CLK_NPU]		= &npu_clk.common.hw,
+		[CLK_BUS_NPU]		= &bus_npu_clk.common.hw,
+		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
+		[CLK_BUS_MSGBOX0]	= &bus_msgbox0_clk.common.hw,
+		[CLK_BUS_MSGBOX1]	= &bus_msgbox1_clk.common.hw,
+		[CLK_BUS_SPINLOCK]	= &bus_spinlock_clk.common.hw,
+		[CLK_BUS_HSTIMER]	= &bus_hstimer_clk.common.hw,
+		[CLK_AVS]		= &avs_clk.common.hw,
+		[CLK_BUS_DBG]		= &bus_dbg_clk.common.hw,
+		[CLK_BUS_PWM]		= &bus_pwm_clk.common.hw,
+		[CLK_BUS_IOMMU]		= &bus_iommu_clk.common.hw,
+		[CLK_DRAM]		= &dram_clk.common.hw,
+		[CLK_MBUS_DMA]		= &mbus_dma_clk.common.hw,
+		[CLK_MBUS_VE]		= &mbus_ve_clk.common.hw,
+		[CLK_MBUS_CE]		= &mbus_ce_clk.common.hw,
+		[CLK_MBUS_CSI]		= &mbus_csi_clk.common.hw,
+		[CLK_MBUS_ISP]		= &mbus_isp_clk.common.hw,
+		[CLK_MBUS_G2D]		= &mbus_g2d_clk.common.hw,
+		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
+		[CLK_MMC0]		= &mmc0_clk.common.hw,
+		[CLK_MMC1]		= &mmc1_clk.common.hw,
+		[CLK_MMC2]		= &mmc2_clk.common.hw,
+		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
+		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
+		[CLK_BUS_MMC2]		= &bus_mmc2_clk.common.hw,
+		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
+		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
+		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
+		[CLK_BUS_UART3]		= &bus_uart3_clk.common.hw,
+		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
+		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
+		[CLK_BUS_I2C2]		= &bus_i2c2_clk.common.hw,
+		[CLK_BUS_I2C3]		= &bus_i2c3_clk.common.hw,
+		[CLK_BUS_I2C4]		= &bus_i2c4_clk.common.hw,
+		[CLK_SPI0]		= &spi0_clk.common.hw,
+		[CLK_SPI1]		= &spi1_clk.common.hw,
+		[CLK_SPI2]		= &spi2_clk.common.hw,
+		[CLK_SPI3]		= &spi3_clk.common.hw,
+		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
+		[CLK_BUS_SPI1]		= &bus_spi1_clk.common.hw,
+		[CLK_BUS_SPI2]		= &bus_spi2_clk.common.hw,
+		[CLK_BUS_SPI3]		= &bus_spi3_clk.common.hw,
+		[CLK_SPIF]		= &spif_clk.common.hw,
+		[CLK_BUS_SPIF]		= &bus_spif_clk.common.hw,
+		[CLK_EMAC_25M]		= &emac_25M_clk.common.hw,
+		[CLK_BUS_EMAC]		= &bus_emac_clk.common.hw,
+		[CLK_BUS_GPADC]		= &bus_gpadc_clk.common.hw,
+		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
+		[CLK_I2S0]		= &i2s0_clk.common.hw,
+		[CLK_I2S1]		= &i2s1_clk.common.hw,
+		[CLK_BUS_I2S0]		= &bus_i2s0_clk.common.hw,
+		[CLK_BUS_I2S1]		= &bus_i2s1_clk.common.hw,
+		[CLK_DMIC]		= &dmic_clk.common.hw,
+		[CLK_BUS_DMIC]		= &bus_dmic_clk.common.hw,
+		[CLK_AUDIO_CODEC_DAC]	= &audio_codec_dac_clk.common.hw,
+		[CLK_AUDIO_CODEC_ADC]	= &audio_codec_adc_clk.common.hw,
+		[CLK_BUS_AUDIO_CODEC]	= &bus_audio_codec_clk.common.hw,
+		[CLK_USB_OHCI]		= &usb_ohci_clk.common.hw,
+		[CLK_BUS_OHCI]		= &bus_ohci_clk.common.hw,
+		[CLK_BUS_EHCI]		= &bus_ehci_clk.common.hw,
+		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
+		[CLK_BUS_DPSS_TOP]	= &bus_dpss_top_clk.common.hw,
+		[CLK_MIPI_DSI]		= &mipi_dsi_clk.common.hw,
+		[CLK_BUS_MIPI_DSI]	= &bus_mipi_dsi_clk.common.hw,
+		[CLK_TCON_LCD]		= &tcon_lcd_clk.common.hw,
+		[CLK_BUS_TCON_LCD]	= &bus_tcon_lcd_clk.common.hw,
+		[CLK_CSI_TOP]		= &csi_top_clk.common.hw,
+		[CLK_CSI_MCLK0]		= &csi_mclk0_clk.common.hw,
+		[CLK_CSI_MCLK1]		= &csi_mclk1_clk.common.hw,
+		[CLK_CSI_MCLK2]		= &csi_mclk2_clk.common.hw,
+		[CLK_BUS_CSI]		= &bus_csi_clk.common.hw,
+		[CLK_BUS_WIEGAND]	= &bus_wiegand_clk.common.hw,
+		[CLK_RISCV]		= &riscv_clk.common.hw,
+		[CLK_RISCV_AXI]		= &riscv_axi_clk.common.hw,
+		[CLK_RISCV_CORE_GATE]   = &riscv_core_gate.common.hw,
+		[CLK_RISCV_CFG_GATE]    = &riscv_cfg_gate.common.hw,
+		[CLK_FANOUT_24M]	= &fanout_24M_clk.common.hw,
+		[CLK_FANOUT_16M]	= &fanout_16M_clk.common.hw,
+		[CLK_FANOUT_12M]	= &fanout_12M_clk.common.hw,
+		[CLK_FANOUT_25M]	= &fanout_25M_clk.common.hw,
+		[CLK_FANOUT_27M]	= &fanout_27M_clk.common.hw,
+		[CLK_FANOUT_PCLK]	= &fanout_pclk_clk.common.hw,
+		[CLK_FANOUT0]		= &fanout0_clk.common.hw,
+		[CLK_FANOUT1]		= &fanout1_clk.common.hw,
+		[CLK_FANOUT2]		= &fanout2_clk.common.hw,
+	},
+};
+
+static struct ccu_reset_map sun8i_v853_ccu_resets[] = {
+	[RST_MBUS]		= { 0x540, BIT(30) },
+	[RST_BUS_DE]		= { 0x60c, BIT(16) },
+	[RST_BUS_G2D]		= { 0x63c, BIT(16) },
+	[RST_BUS_CE]		= { 0x68c, BIT(16) | BIT(17)},
+	[RST_BUS_VE]		= { 0x69c, BIT(16) },
+	[RST_BUS_NPU]		= { 0x6ec, BIT(16) },
+	[RST_BUS_DMA]		= { 0x70c, BIT(16) },
+	[RST_BUS_MSGBOX0]	= { 0x71c, BIT(16) },
+	[RST_BUS_MSGBOX1]	= { 0x71c, BIT(17) },
+	[RST_BUS_SPINLOCK]	= { 0x72c, BIT(16) },
+	[RST_BUS_HSTIMER]	= { 0x73c, BIT(16) },
+	[RST_BUS_DBG]		= { 0x78c, BIT(16) },
+	[RST_BUS_PWM]		= { 0x7ac, BIT(16) },
+	[RST_BUS_DRAM]		= { 0x80c, BIT(16) },
+	[RST_BUS_MMC0]		= { 0x84c, BIT(16) },
+	[RST_BUS_MMC1]		= { 0x84c, BIT(17) },
+	[RST_BUS_MMC2]		= { 0x84c, BIT(18) },
+	[RST_BUS_UART0]		= { 0x90c, BIT(16) },
+	[RST_BUS_UART1]		= { 0x90c, BIT(17) },
+	[RST_BUS_UART2]		= { 0x90c, BIT(18) },
+	[RST_BUS_UART3]		= { 0x90c, BIT(19) },
+	[RST_BUS_I2C0]		= { 0x91c, BIT(16) },
+	[RST_BUS_I2C1]		= { 0x91c, BIT(17) },
+	[RST_BUS_I2C2]		= { 0x91c, BIT(18) },
+	[RST_BUS_I2C3]		= { 0x91c, BIT(19) },
+	[RST_BUS_I2C4]		= { 0x91c, BIT(20) },
+	[RST_BUS_SPI0]		= { 0x96c, BIT(16) },
+	[RST_BUS_SPI1]		= { 0x96c, BIT(17) },
+	[RST_BUS_SPI2]		= { 0x96c, BIT(18) },
+	[RST_BUS_SPI3]		= { 0x96c, BIT(19) },
+	[RST_BUS_SPIF]		= { 0x96c, BIT(20) },
+	[RST_BUS_EMAC]		= { 0x97c, BIT(16) },
+	[RST_BUS_GPADC]		= { 0x9ec, BIT(16) },
+	[RST_BUS_THS]		= { 0x9fc, BIT(16) },
+	[RST_BUS_I2S0]		= { 0xa20, BIT(16) },
+	[RST_BUS_I2S1]		= { 0xa20, BIT(17) },
+	[RST_BUS_DMIC]		= { 0xa4c, BIT(16) },
+	[RST_BUS_AUDIO_CODEC]	= { 0xa5c, BIT(16) },
+	[RST_USB_PHY]		= { 0xa70, BIT(30) },
+	[RST_BUS_OHCI]		= { 0xa8c, BIT(16) },
+	[RST_BUS_EHCI]		= { 0xa8c, BIT(20) },
+	[RST_BUS_OTG]		= { 0xa8c, BIT(24) },
+	[RST_BUS_DPSS_TOP]	= { 0xabc, BIT(16) },
+	[RST_BUS_MIPI_DSI]	= { 0xb4c, BIT(16) },
+	[RST_BUS_TCON_LCD]	= { 0xb7c, BIT(16) },
+	[RST_BUS_CSI]		= { 0xc2c, BIT(16) },
+	[RST_BUS_WIEGAND]	= { 0xc7c, BIT(16) },
+	[RST_RISCV_SYS_APB]	= { 0xd04, BIT(2), CCU_FEATURE_KEY_FIELD },
+	[RST_RISCV_SOFT]	= { 0xd04, BIT(1), CCU_FEATURE_KEY_FIELD },
+	[RST_RISCV_CFG]		= { 0xd0c, BIT(16) }
+};
+
+static const struct sunxi_ccu_desc sun8i_v853_ccu_desc = {
+	.ccu_clks	= sun8i_v853_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_v853_ccu_clks),
+
+	.hw_clks	= &sun8i_v853_hw_clks,
+
+	.resets		= sun8i_v853_ccu_resets,
+	.num_resets	= ARRAY_SIZE(sun8i_v853_ccu_resets),
+};
+
+static const u32 pll_regs[] = {
+	SUN8I_V853_PLL_CPU_REG,
+	SUN8I_V853_PLL_DDR_REG,
+	SUN8I_V853_PLL_PERIPH_REG,
+	SUN8I_V853_PLL_VIDEO_REG,
+	SUN8I_V853_PLL_CSI_REG,
+	SUN8I_V853_PLL_AUDIO_REG,
+	SUN8I_V853_PLL_NPU_REG,
+};
+
+static int sun8i_v853_ccu_probe(struct platform_device *pdev)
+{
+	void __iomem *reg;
+	u32 val;
+	int i, ret;
+
+	reg = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(reg))
+		return PTR_ERR(reg);
+
+	/* Enable the enable, LDO, and lock bits on all PLLs. */
+	for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
+		val = readl(reg + pll_regs[i]);
+		val |= BIT(31) | BIT(30) | BIT(29);
+		writel(val, reg + pll_regs[i]);
+	}
+
+	/* Force PLL_CPU factor M to 0. */
+	val = readl(reg + SUN8I_V853_PLL_CPU_REG);
+	val &= ~GENMASK(1, 0);
+	writel(val, reg + SUN8I_V853_PLL_CPU_REG);
+
+	/*
+	 * Force OHCI 12M clock source to 00 (12MHz divided from 48MHz)
+	 *
+	 * This clock mux is still mysterious, and the code just enforces
+	 * it to have a valid clock parent.
+	 */
+	val = readl(reg + SUN8I_V853_USB_CLK_REG);
+	val &= ~GENMASK(25, 24);
+	writel(val, reg + SUN8I_V853_USB_CLK_REG);
+
+	/* Force fanout-27M factor N to 0. */
+	val = readl(reg + SUN8I_V853_FANOUT_27M_REG);
+	val &= ~GENMASK(9, 8);
+	writel(val, reg + SUN8I_V853_FANOUT_27M_REG);
+
+	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_v853_ccu_desc);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct of_device_id sun8i_v853_ccu_ids[] = {
+	{ .compatible = "allwinner,sun8i-v853-ccu" },
+	{ }
+};
+
+static struct platform_driver sun8i_v853_ccu_driver = {
+	.probe	= sun8i_v853_ccu_probe,
+	.driver	= {
+		.name			= "sun8i-v853-ccu",
+		.suppress_bind_attrs	= true,
+		.of_match_table		= sun8i_v853_ccu_ids,
+	},
+};
+module_platform_driver(sun8i_v853_ccu_driver);
+
+MODULE_IMPORT_NS("SUNXI_CCU");
+MODULE_DESCRIPTION("Support for the Allwinner V853 CCU");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853.h b/drivers/clk/sunxi-ng/ccu-sun8i-v853.h
new file mode 100644
index 000000000000..f1b2a4d0bcd3
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com>
+ */
+
+#ifndef _CCU_SUN8I_V853_H_
+#define _CCU_SUN8I_V853_H_
+
+#include <dt-bindings/clock/allwinner,sun8i-v853-ccu.h>
+#include <dt-bindings/reset/allwinner,sun8i-v853-ccu.h>
+
+#define CLK_NUMBER		(CLK_FANOUT2 + 1)
+
+#endif
-- 
2.39.5

[PATCH v2 05/10] dt-bindings: power: add V853 ppu bindings

[Andras Szemzo]

Document V853 PPU compatible.

Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
---
 .../bindings/power/allwinner,sun20i-d1-ppu.yaml        |  1 +
 include/dt-bindings/power/allwinner,sun8i-v853-ppu.h   | 10 ++++++++++
 2 files changed, 11 insertions(+)
 create mode 100644 include/dt-bindings/power/allwinner,sun8i-v853-ppu.h

diff --git a/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml
index 46e2647a5d72..f578be6a3bc8 100644
--- a/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml
+++ b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml
@@ -17,6 +17,7 @@ properties:
   compatible:
     enum:
       - allwinner,sun20i-d1-ppu
+      - allwinner,sun8i-v853-ppu
 
   reg:
     maxItems: 1
diff --git a/include/dt-bindings/power/allwinner,sun8i-v853-ppu.h b/include/dt-bindings/power/allwinner,sun8i-v853-ppu.h
new file mode 100644
index 000000000000..b1c18a490613
--- /dev/null
+++ b/include/dt-bindings/power/allwinner,sun8i-v853-ppu.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_POWER_SUN8I_V853_PPU_H_
+#define _DT_BINDINGS_POWER_SUN8I_V853_PPU_H_
+
+#define PD_RISCV		0
+#define PD_NPU			1
+#define PD_VE			2
+
+#endif
-- 
2.39.5

[PATCH v2 06/10] pmdomain: sunxi: add V853 ppu support

[Andras Szemzo]

V853 has a similar ppu like Allwinner D1, add compatible and the available pd names.

Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
---
 drivers/pmdomain/sunxi/sun20i-ppu.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/pmdomain/sunxi/sun20i-ppu.c b/drivers/pmdomain/sunxi/sun20i-ppu.c
index 8700f9dd5f75..9f002748d224 100644
--- a/drivers/pmdomain/sunxi/sun20i-ppu.c
+++ b/drivers/pmdomain/sunxi/sun20i-ppu.c
@@ -182,11 +182,26 @@ static const struct sun20i_ppu_desc sun20i_d1_ppu_desc = {
 	.num_domains	= ARRAY_SIZE(sun20i_d1_ppu_pd_names),
 };
 
+static const char *const sun8i_v853_ppu_pd_names[] = {
+	"RISCV",
+	"NPU",
+	"VE",
+};
+
+static const struct sun20i_ppu_desc sun8i_v853_ppu_desc = {
+	.names		= sun8i_v853_ppu_pd_names,
+	.num_domains	= ARRAY_SIZE(sun8i_v853_ppu_pd_names),
+};
+
 static const struct of_device_id sun20i_ppu_of_match[] = {
 	{
 		.compatible	= "allwinner,sun20i-d1-ppu",
 		.data		= &sun20i_d1_ppu_desc,
 	},
+	{
+		.compatible	= "allwinner,sun8i-v853-ppu",
+		.data		= &sun8i_v853_ppu_desc,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, sun20i_ppu_of_match);
-- 
2.39.5

[PATCH v2 07/10] dt-bindings: phy: allwinner: add v853 usb phy

[Andras Szemzo]

Document Allwinner v853 USB phy.

Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
---
 .../devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml   | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
index 21209126ed00..815742c4f5fb 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
@@ -19,9 +19,11 @@ properties:
       - enum:
           - allwinner,sun20i-d1-usb-phy
           - allwinner,sun50i-a64-usb-phy
+          - allwinner,sun8i-v853-usb-phy
       - items:
           - const: allwinner,sun50i-a100-usb-phy
           - const: allwinner,sun20i-d1-usb-phy
+          - const: allwinner,sun8i-v853-usb-phy
 
   reg:
     items:
-- 
2.39.5

[PATCH v2 08/10] phy: allwinner: add v853 usb phy compatible

[Andras Szemzo]

V853 has a dual role USB phy, similar to other Allwinner devices, but with
only one phy. Add a compatible for it.

Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
---
 drivers/phy/allwinner/phy-sun4i-usb.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 29b8fd4b9351..1610501fb8bb 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -1005,6 +1005,15 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.phy0_dual_route = true,
 };
 
+static const struct sun4i_usb_phy_cfg sun8i_v853_cfg = {
+	.num_phys = 1,
+	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
+	.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
+	.phy0_dual_route = true,
+	.siddq_in_base = true,
+};
+
 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
 	.num_phys = 4,
 	.phyctl_offset = REG_PHYCTL_A33,
@@ -1041,6 +1050,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
 	  .data = &sun50i_a64_cfg},
 	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
 	{ .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
+	{ .compatible = "allwinner,sun8i-v853-usb-phy", .data = &sun8i_v853_cfg },
 	{ .compatible = "allwinner,suniv-f1c100s-usb-phy",
 	  .data = &suniv_f1c100s_cfg },
 	{ },
-- 
2.39.5

[PATCH v2 09/10] ARM: dts: sun8i: add DTSI file for V853

[Andras Szemzo]

V853/V851 is a new SoC by Allwinner. Add a basic dtsi file for it.

Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
---
 arch/arm/boot/dts/allwinner/sun8i-v853.dtsi | 656 ++++++++++++++++++++
 1 file changed, 656 insertions(+)
 create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v853.dtsi

diff --git a/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
new file mode 100644
index 000000000000..8b82b8783127
--- /dev/null
+++ b/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
@@ -0,0 +1,656 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+// Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com>
+
+#include <dt-bindings/clock/sun6i-rtc.h>
+#include <dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h>
+#include <dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h>
+#include <dt-bindings/clock/allwinner,sun8i-v853-ccu.h>
+#include <dt-bindings/reset/allwinner,sun8i-v853-ccu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/allwinner,sun8i-v853-ppu.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	dcxo: dcxo-clk {
+		compatible = "fixed-clock";
+		clock-output-names = "osc24M";
+		#clock-cells = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7","arm,armv7";
+			reg = <0>;
+			clocks = <&ccu CLK_CPU>;
+			clock-names = "cpu";
+			clock-frequency = <912000000>;
+			clock-latency = <200000>;
+			cooling-min-level = <5>;
+			cooling-max-level = <0>;
+			#cooling-cells = <2>; /* min followed by max */
+			dynamic-power-coefficient = <142>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <24000000>;
+		interrupt-parent = <&gic>;
+		arm,cpu-registers-not-fw-configured;
+		arm,no-tick-in-suspend;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&gic>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		dma-noncoherent;
+
+		pio: pinctrl@2000000 {
+			compatible = "allwinner,sun8i-v853-pinctrl";
+			reg = <0x2000000 0x800>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_APB0>, <&dcxo>, <&rtc CLK_OSC32K>;
+			clock-names = "apb", "hosc", "losc";
+			gpio-controller;
+			interrupt-controller;
+			#gpio-cells = <3>;
+			#interrupt-cells = <3>;
+
+			/omit-if-no-ref/
+			uart0_ph9_pins: uart0-ph9-pins {
+				pins = "PH9", "PH10";
+				function = "uart0";
+				allwinner,pinmux = <5>;
+			};
+
+			/omit-if-no-ref/
+			uart2_pe12_pins: uart2-pe12-pins {
+				pins = "PE12", "PE13";
+				function = "uart2";
+				allwinner,pinmux = <6>;
+			};
+
+			/omit-if-no-ref/
+			dsi_2lane_pins: dsi-2lane-pins {
+				pins = "PD1", "PD2", "PD3", "PD4", "PD5", "PD6";
+				function = "dsi";
+				allwinner,pinmux = <5>;
+			};
+
+			/omit-if-no-ref/
+			spi0_pins: spi0-pins {
+				pins = "PC0", "PC1", "PC2", "PC3", "PC4", "PC5";
+				function = "spi0";
+				allwinner,pinmux = <4>;
+			};
+
+			/omit-if-no-ref/
+			spi3_pins: spi3-pins {
+				pins = "PH11", "PH12", "PH13", "PH14";
+				function = "spi3";
+				allwinner,pinmux = <6>;
+			};
+
+			/omit-if-no-ref/
+			i2c2_ph11_pins: i2c2-ph11-pins {
+				pins = "PH11", "PH12";
+				function = "i2c2";
+				allwinner,pinmux = <5>;
+			};
+
+			/omit-if-no-ref/
+			i2c3_ph13_pins: i2c3-ph13-pins {
+				pins = "PH13", "PH14";
+				function = "i2c3";
+				allwinner,pinmux = <5>;
+			};
+
+			/omit-if-no-ref/
+			mmc0_pins: mmc0-pins {
+				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+				function = "sdc0";
+				allwinner,pinmux = <2>;
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/
+			mmc1_pins: mmc1-pins {
+				pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5";
+				function = "sdc1";
+				allwinner,pinmux = <6>;
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/
+			rmii_pe_pins: rmii-pe-pins {
+				pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+				       "PE5", "PE6", "PE7", "PE8", "PE9";
+				function = "emac";
+				allwinner,pinmux = <3>;
+			};
+		};
+
+		ccu: clock-controller@2001000 {
+			compatible = "allwinner,sun8i-v853-ccu";
+			reg = <0x2001000 0x1000>;
+			clocks = <&dcxo>,
+				 <&rtc CLK_IOSC>,
+				 <&rtc CLK_OSC32K>;
+			clock-names = "hosc", "iosc", "losc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		gpadc: adc@2009000 {
+			compatible = "allwinner,sun20i-d1-gpadc";
+			reg = <0x2009000 0x0400>;
+			clocks = <&ccu CLK_BUS_GPADC>;
+			resets = <&ccu RST_BUS_GPADC>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		i2s0: i2s@2032000 {
+			compatible = "allwinner,sun50i-r329-i2s";
+			reg = <0x2032000 0x1000>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2S0>,
+				 <&ccu CLK_I2S0>;
+			clock-names = "apb", "mod";
+			resets = <&ccu RST_BUS_I2S0>;
+			dmas = <&dma 3>, <&dma 3>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#sound-dai-cells = <0>;
+		};
+
+		i2s1: i2s@2033000 {
+			compatible = "allwinner,sun50i-r329-i2s";
+			reg = <0x2033000 0x1000>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2S1>,
+				 <&ccu CLK_I2S1>;
+			clock-names = "apb", "mod";
+			resets = <&ccu RST_BUS_I2S1>;
+			dmas = <&dma 4>, <&dma 4>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#sound-dai-cells = <0>;
+		};
+
+		timer: timer@2050000 {
+			compatible = "allwinner,sun20i-d1-timer",
+				     "allwinner,sun8i-a23-timer";
+			reg = <0x2050000 0xa0>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dcxo>;
+		};
+
+		wdt: watchdog@20500a0 {
+			compatible = "allwinner,sun20i-d1-wdt-reset",
+				     "allwinner,sun20i-d1-wdt";
+			reg = <0x20500a0 0x20>;
+			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dcxo>, <&rtc CLK_OSC32K>;
+			clock-names = "hosc", "losc";
+			status = "reserved";
+		};
+
+		uart0: serial@2500000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x2500000 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_UART0>;
+			resets = <&ccu RST_BUS_UART0>;
+			dmas = <&dma 14>, <&dma 14>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		uart1: serial@2500400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x2500400 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_UART1>;
+			resets = <&ccu RST_BUS_UART1>;
+			dmas = <&dma 15>, <&dma 15>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		uart2: serial@2500800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x2500800 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_UART2>;
+			resets = <&ccu RST_BUS_UART2>;
+			dmas = <&dma 16>, <&dma 16>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		uart3: serial@2500c00 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x2500c00 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_UART3>;
+			resets = <&ccu RST_BUS_UART3>;
+			dmas = <&dma 17>, <&dma 17>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		i2c0: i2c@2502000 {
+			compatible = "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x2502000 0x400>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C0>;
+			resets = <&ccu RST_BUS_I2C0>;
+			dmas = <&dma 43>, <&dma 43>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@2502400 {
+			compatible = "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x2502400 0x400>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C1>;
+			resets = <&ccu RST_BUS_I2C1>;
+			dmas = <&dma 44>, <&dma 44>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@2502800 {
+			compatible = "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x2502800 0x400>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C2>;
+			resets = <&ccu RST_BUS_I2C2>;
+			dmas = <&dma 45>, <&dma 45>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@2502c00 {
+			compatible = "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x2502c00 0x400>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C3>;
+			resets = <&ccu RST_BUS_I2C3>;
+			dmas = <&dma 46>, <&dma 46>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@2503000 {
+			compatible = "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x2503000 0x400>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C4>;
+			resets = <&ccu RST_BUS_I2C4>;
+			dmas = <&dma 47>, <&dma 47>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		syscon: syscon@3000000 {
+			compatible = "allwinner,sun8i-h3-system-control";
+			reg = <0x3000000 0x1000>;
+			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_c: sram@20000 {
+				compatible = "mmio-sram";
+				reg = <0x00020000 0x21000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00020000 0x21000>;
+
+				ve_sram: sram-section@0 {
+				    compatible = "allwinner,sun8i-v3s-sram-c", 
+						 "allwinner,sun4i-a10-sram-c1";
+				    reg = <0x000000 0x21000>;
+				};
+			};
+		};
+
+		dma: dma-controller@3002000 {
+			compatible = "allwinner,sun20i-d1-dma";
+			reg = <0x3002000 0x1000>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
+			clock-names = "bus", "mbus";
+			resets = <&ccu RST_BUS_DMA>;
+			dma-channels = <16>;
+			dma-requests = <48>;
+			#dma-cells = <1>;
+		};
+
+		hwspinlock: hwlock@3005000 {
+		    compatible = "allwinner,sun6i-a31-hwspinlock";
+			reg = <0x3005000 0x1000>;
+			clocks = <&ccu CLK_BUS_SPINLOCK>;
+			clock-names = "ahb";
+			resets = <&ccu RST_BUS_SPINLOCK>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		sid: efuse@3006000 {
+			compatible = "allwinner,sun20i-d1-sid";
+			reg = <0x3006000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ths_calib: ths-calib@14 {
+				reg = <0x14 0x8>;
+			};
+		};
+
+		hstimer@3008000 {
+			compatible = "allwinner,sun7i-a20-hstimer";
+			reg = <0x03008000 0x1000>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_HSTIMER>;
+		};
+
+		gic: interrupt-controller@3021000 {
+			compatible = "arm,gic-400";
+			reg = <0x03021000 0x1000>,	/* GIC Dist */
+			      <0x03022000 0x2000>,	/* GIC CPU */
+			      <0x03024000 0x2000>,	/* GIC VCPU Control */
+			      <0x03026000 0x2000>;	/* GIC VCPU */
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		mbus: dram-controller@3102000 {
+			compatible = "allwinner,sun20i-d1-mbus";
+			reg = <0x3102000 0x1000>,
+			      <0x3103000 0x1000>;
+			reg-names = "mbus", "dram";
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_MBUS>,
+				 <&ccu CLK_DRAM>,
+				 <&ccu CLK_BUS_DRAM>;
+			clock-names = "mbus", "dram", "bus";
+			dma-ranges = <0 0x40000000 0x80000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#interconnect-cells = <1>;
+		};
+
+		mmc0: mmc@4020000 {
+			compatible = "allwinner,sun20i-d1-mmc";
+			reg = <0x4020000 0x1000>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC0>;
+			reset-names = "ahb";
+			no-sdio;
+			no-mmc;
+			cap-sd-highspeed;
+			max-frequency = <150000000>;
+			mmc-ddr-1_8v;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc@4021000 {
+			compatible = "allwinner,sun20i-d1-mmc";
+			reg = <0x4021000 0x1000>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC1>;
+			reset-names = "ahb";
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			max-frequency = <150000000>;
+			mmc-ddr-1_8v;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc2: mmc@4022000 {
+			compatible = "allwinner,sun20i-d1-mmc";
+			reg = <0x4022000 0x1000>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC2>;
+			reset-names = "ahb";
+			no-sdio;
+			no-sd;
+			cap-mmc-highspeed;
+			max-frequency = <150000000>;
+			mmc-ddr-1_8v;
+			mmc-ddr-3_3v;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi0: spi@4025000 {
+			compatible = "allwinner,sun50i-r329-spi";
+			reg = <0x4025000 0x1000>;
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI0>;
+			dmas = <&dma 22>, <&dma 22>;
+			dma-names = "rx", "tx";
+			num-cs = <1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@4026000 {
+			compatible = "allwinner,sun50i-r329-spi-dbi",
+				     "allwinner,sun50i-r329-spi";
+			reg = <0x4026000 0x1000>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI1>;
+			dmas = <&dma 23>, <&dma 23>;
+			dma-names = "rx", "tx";
+			num-cs = <1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi2: spi@4027000 {
+			compatible = "allwinner,sun50i-r329-spi";
+			reg = <0x4027000 0x1000>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI2>;
+			dmas = <&dma 24>, <&dma 24>;
+			dma-names = "rx", "tx";
+			num-cs = <1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi3: spi@4028000 {
+			compatible = "allwinner,sun50i-r329-spi";
+			reg = <0x4028000 0x1000>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI3>;
+			dmas = <&dma 25>, <&dma 25>;
+			dma-names = "rx", "tx";
+			num-cs = <1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		usb_otg: usb@4100000 {
+			compatible = "allwinner,sun8i-a33-musb";
+			reg = <0x4100000 0x400>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			extcon = <&usbphy 0>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		usbphy: phy@4100400 {
+			compatible = "allwinner,sun8i-v853-usb-phy";
+			reg = <0x4100400 0x100>,
+			      <0x4101800 0x100>;
+			reg-names = "phy_ctrl",
+				    "pmu0";
+			clocks = <&ccu CLK_USB_OHCI>;
+			clock-names = "usb0_phy";
+			resets = <&ccu RST_USB_PHY>;
+			reset-names = "usb0_reset";
+			status = "disabled";
+			#phy-cells = <1>;
+		};
+
+		ehci0: usb@4101000 {
+			compatible = "generic-ehci";
+			reg = <0x4101000 0x100>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI>,
+				 <&ccu CLK_BUS_EHCI>,
+				 <&ccu CLK_USB_OHCI>;
+			resets = <&ccu RST_BUS_OHCI>,
+				 <&ccu RST_BUS_EHCI>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci0: usb@4101400 {
+			compatible = "generic-ohci";
+			reg = <0x4101400 0x100>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI>,
+				 <&ccu CLK_USB_OHCI>;
+			resets = <&ccu RST_BUS_OHCI>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ppu: power-controller@7001000 {
+			compatible = "allwinner,sun8i-v853-ppu";
+			reg = <0x7001000 0x400>;
+			clocks = <&r_ccu CLK_BUS_R_PPU>;
+			resets = <&r_ccu RST_BUS_R_PPU>;
+			#power-domain-cells = <1>;
+		};
+
+		r_ccu: clock-controller@7010000 {
+			compatible = "allwinner,sun8i-v853-r-ccu";
+			reg = <0x7010000 0x230>;
+			clocks = <&dcxo>,
+				 <&rtc CLK_IOSC>,
+				 <&rtc CLK_OSC32K>,
+				 <&ccu CLK_PLL_PERIPH_200M>,
+				 <&ccu CLK_PLL_AUDIO_4X>;
+			clock-names = "hosc",
+				      "iosc",
+				      "losc",
+				      "pll-periph",
+				      "pll-audio";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		nmi_intc: intc-nmi@7010320 {
+			compatible = "allwinner,sun9i-a80-nmi";
+			interrupt-parent = <&gic>;
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x07010320 0xc>;
+			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		rtc: rtc@7090000 {
+			compatible = "allwinner,sun50i-r329-rtc";
+			reg = <0x7090000 0x400>;
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_BUS_R_RTC>;
+			clock-names = "bus";
+			resets = <&r_ccu RST_BUS_R_RTC>;
+			wakeup-source;
+			#clock-cells = <1>;
+		};
+	};
+};
-- 
2.39.5

[PATCH v2 10/10] ARM: dts: sun8i: add DTS file for yuzuki-lizard V851s

[Andras Szemzo]

Yuzuki-lizard is an Open Hardware board based on Allwinner V851s SoC. Add a basic dts for it.

Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
---
 arch/arm/boot/dts/allwinner/Makefile          |   1 +
 .../boot/dts/allwinner/sun8i-v851s-lizard.dts | 196 ++++++++++++++++++
 2 files changed, 197 insertions(+)
 create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dts

diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
index 48666f73e638..af84073f6a51 100644
--- a/arch/arm/boot/dts/allwinner/Makefile
+++ b/arch/arm/boot/dts/allwinner/Makefile
@@ -260,6 +260,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 	sun8i-v3-sl631-imx179.dtb \
 	sun8i-v3s-anbernic-rg-nano.dtb \
 	sun8i-v3s-licheepi-zero.dtb \
+	sun8i-v851s-lizard.dtb \
 	sun8i-v3s-licheepi-zero-dock.dtb \
 	sun8i-v40-bananapi-m2-berry.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
diff --git a/arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dts b/arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dts
new file mode 100644
index 000000000000..180d10b1a06a
--- /dev/null
+++ b/arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dts
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+// Copyright (C) 2024 Andras Szemzo.andras@gmail.com>
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "sun8i-v853.dtsi"
+
+/ {
+	model = "Yuzuki-lizard";
+	compatible = "yuzukihd,lizard", "allwinner,sun8i-v853", "allwinner,sun8i";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+	    reg = <0x40000000 0x4000000>;
+	};
+
+	reg_vcc: vcc {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	reg_vcc_1v8: vcc-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc-1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	reg_usbvbus: usbvbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usbvbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&reg_vcc>;
+	};
+
+	reg_vcc_3v3: vcc-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&reg_vcc>;
+	};
+
+	reg_vdd_cpu: vdd-cpu {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-cpu";
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&reg_vcc>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		status_led {
+			linux,default-trigger = "heartbeat";
+			label = "led:red";
+			gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&pio 4 6 GPIO_ACTIVE_LOW>; /* PE6 */
+	};
+};
+
+&dcxo {
+	clock-frequency = <24000000>;
+};
+
+&cpu0 {
+	cpu-supply = <&reg_vdd_cpu>;
+};
+
+&pio {
+	vcc-pa-supply = <&reg_vcc_3v3>;
+	vcc-pc-supply = <&reg_vcc_3v3>;
+	vcc-pd-supply = <&reg_vcc_3v3>;
+	vcc-pe-supply = <&reg_vcc_3v3>;
+	vcc-pf-supply = <&reg_vcc_3v3>;
+	vcc-ph-supply = <&reg_vcc_3v3>;
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_ph9_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-0 = <&spi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "spi-nand";
+		spi-max-frequency = <75000000>;
+		reg = <0>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "awboot";
+				reg = <0x00000000 0x00020000>;	/* 128K */
+			};
+
+			partition@20000 {
+				label = "dtb";
+				reg = <0x00020000 0x00020000>;  /* 128k */
+			};
+
+			partition@40000 {
+				label = "kernel";
+				reg = <0x00040000 0x00800000>;  /* 8MB */
+			};
+
+			partition@840000 {
+				label = "rootfs";
+				reg = <0x00840000 0x077c0000>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_ph11_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&mmc0 {
+	bus-width = <4>;
+	broken-cd;
+	disable-wp;
+	vmmc-supply = <&reg_vcc_3v3>;
+	vqmmc-supply = <&reg_vcc_3v3>;
+	pinctrl-0 = <&mmc0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&mmc1 {
+	bus-width = <4>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	non-removable;
+	vmmc-supply = <&reg_vcc_3v3>;
+	vqmmc-supply = <&reg_vcc_3v3>;
+	pinctrl-0 = <&mmc1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	xr829: wifi@1 {
+		reg = <1>;
+		interrupt-parent = <&pio>;
+		interrupts = <4 7 IRQ_TYPE_LEVEL_HIGH>; /* PE7 */
+		interrupt-names = "host-wake";
+	};
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&usbphy {
+	usb0_vbus-supply = <&reg_usbvbus>;
+	usb0_id_det-gpio = <&pio 4 9 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
-- 
2.39.5

Re: [PATCH v2 00/10] Support for Allwinner V853 SoC

[Rob Herring (Arm)]

On Wed, 05 Feb 2025 13:52:15 +0100, Andras Szemzo wrote:
> V85x is a SoC from Allwinner with video encoding targeted for the field of
> IP Camera. It integrates the single CA7 core, and a T-Head E907 RISC-V mcu.
> The SoC has the usual Allwinner peripherals and a Vivante NPU.
> V853 is a BGA package without DRAM, V851s/V851s3 has the same die with
> co-packaged 64MB/128MB DRAM (in a QFN88 package).
> 
> This patchset tries to add basical support for the V853 device family.
> 
> Changelog - v2:
>  - rebased on 6.14-rc1
>  - add a needed gate with key support to sunxi clk
>  - rewrite the ccu-r driver
>  - fix license issues
>  - remove the pinctrl binding, as it has beed applied
>  - rework the pinctrl driver, use the new sunxi dt based mux support. This new pinctrl
>    driver depends on the new sunxi device-tree based mux support patch series [1].
>  - remove the new usb phy binding, as the v853's usb phy is very close to d1/a64
>  - add a board dts
>  - ccu: add module description
>  - ccu: fix PLL enable bits, and min multipliers
>  - ccu: change PLL flags to CLK_SET_RATE_GATE
>  - ccu: use SUNXI_CCU_M_HWS at peripheral PLLs
>  - ccu: convert the VIDEO and CSI PLLs from nm type to nkmp according to BSP
>  - ccu: cpu axi clk use pointer
>  - ccu: fix comments
>  - ccu: swap i2s1 and i2s0 bus clocks
>  - ccu: fix indentation
>  - ccu: fix RST_BUS_SPIF order
>  - ccu: convert RST_RISCV_CLK_GATING from reset to gate
> 
> [1]: https://lore.kernel.org/linux-sunxi/20241111005750.13071-1-andre.przywara@arm.com/T/
> 
> Andras Szemzo (10):
>   clk: sunxi-ng: allow key feature in ccu reset and gate
>   pinctrl: sunxi: add driver for Allwinner V853
>   dt-bindings: clock: sunxi-ng: add compatibles for V853
>   clk: sunxi-ng: add CCU drivers for V853
>   dt-bindings: power: add V853 ppu bindings
>   pmdomain: sunxi: add V853 ppu support
>   dt-bindings: phy: allwinner: add v853 usb phy
>   phy: allwinner: add v853 usb phy compatible
>   ARM: dts: sun8i: add DTSI file for V853
>   ARM: dts: sun8i: add DTS file for yuzuki-lizard V851s
> 
>  .../clock/allwinner,sun4i-a10-ccu.yaml        |    3 +
>  .../phy/allwinner,sun50i-a64-usb-phy.yaml     |    2 +
>  .../power/allwinner,sun20i-d1-ppu.yaml        |    1 +
>  arch/arm/boot/dts/allwinner/Makefile          |    1 +
>  .../boot/dts/allwinner/sun8i-v851s-lizard.dts |  196 +++
>  arch/arm/boot/dts/allwinner/sun8i-v853.dtsi   |  656 ++++++++++
>  drivers/clk/sunxi-ng/Kconfig                  |   10 +
>  drivers/clk/sunxi-ng/Makefile                 |    4 +
>  drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c       |  120 ++
>  drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h       |   14 +
>  drivers/clk/sunxi-ng/ccu-sun8i-v853.c         | 1145 +++++++++++++++++
>  drivers/clk/sunxi-ng/ccu-sun8i-v853.h         |   14 +
>  drivers/clk/sunxi-ng/ccu_common.h             |    2 +
>  drivers/clk/sunxi-ng/ccu_gate.c               |    6 +
>  drivers/clk/sunxi-ng/ccu_gate.h               |   14 +
>  drivers/clk/sunxi-ng/ccu_mux.c                |    4 +-
>  drivers/clk/sunxi-ng/ccu_reset.c              |    7 +
>  drivers/clk/sunxi-ng/ccu_reset.h              |    2 +-
>  drivers/phy/allwinner/phy-sun4i-usb.c         |   10 +
>  drivers/pinctrl/sunxi/Kconfig                 |    5 +
>  drivers/pinctrl/sunxi/Makefile                |    1 +
>  drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c    |   53 +
>  drivers/pmdomain/sunxi/sun20i-ppu.c           |   15 +
>  .../clock/allwinner,sun8i-v853-ccu.h          |  132 ++
>  .../clock/allwinner,sun8i-v853-r-ccu.h        |   16 +
>  .../power/allwinner,sun8i-v853-ppu.h          |   10 +
>  .../reset/allwinner,sun8i-v853-ccu.h          |   60 +
>  .../reset/allwinner,sun8i-v853-r-ccu.h        |   14 +
>  28 files changed, 2513 insertions(+), 4 deletions(-)
>  create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dts
>  create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.h
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c
>  create mode 100644 include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h
>  create mode 100644 include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h
>  create mode 100644 include/dt-bindings/power/allwinner,sun8i-v853-ppu.h
>  create mode 100644 include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h
>  create mode 100644 include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h
> 
> --
> 2.39.5
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/allwinner/' for 20250205125225.1152849-1-szemzo.andras@gmail.com:

arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: /: memory: False schema does not allow {'reg': [[1073741824, 67108864]]}
	from schema $id: http://devicetree.org/schemas/root-node.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: /: memory: 'device_type' is a required property
	from schema $id: http://devicetree.org/schemas/memory.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: /: failed to match any schema with compatible: ['yuzukihd,lizard', 'allwinner,sun8i-v853', 'allwinner,sun8i']
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: /: failed to match any schema with compatible: ['yuzukihd,lizard', 'allwinner,sun8i-v853', 'allwinner,sun8i']
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: /: failed to match any schema with compatible: ['yuzukihd,lizard', 'allwinner,sun8i-v853', 'allwinner,sun8i']
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: cpu@0: compatible: ['arm,cortex-a7', 'arm,armv7'] is too long
	from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: /cpus/cpu@0: failed to match any schema with compatible: ['arm,cortex-a7', 'arm,armv7']
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: pinctrl@2000000: uart0-ph9-pins: 'allwinner,pinmux' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: pinctrl@2000000: spi0-pins: 'allwinner,pinmux' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: pinctrl@2000000: i2c2-ph11-pins: 'allwinner,pinmux' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: pinctrl@2000000: mmc0-pins: 'allwinner,pinmux' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: pinctrl@2000000: mmc1-pins: 'allwinner,pinmux' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: clock-controller@2001000: clock-names:1: 'losc' was expected
	from schema $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: clock-controller@2001000: clock-names:2: 'iosc' was expected
	from schema $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: serial@2500000: dma-names:0: 'tx' was expected
	from schema $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: serial@2500000: dma-names:1: 'rx' was expected
	from schema $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: serial@2500000: Unevaluated properties are not allowed ('dma-names' was unexpected)
	from schema $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: serial@2500400: dma-names:0: 'tx' was expected
	from schema $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: serial@2500400: dma-names:1: 'rx' was expected
	from schema $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: serial@2500800: dma-names:0: 'tx' was expected
	from schema $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: serial@2500800: dma-names:1: 'rx' was expected
	from schema $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: serial@2500c00: dma-names:0: 'tx' was expected
	from schema $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: serial@2500c00: dma-names:1: 'rx' was expected
	from schema $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: syscon@3000000: sram@20000:sram-section@0:compatible: 'oneOf' conditional failed, one must be fixed:
	['allwinner,sun8i-v3s-sram-c', 'allwinner,sun4i-a10-sram-c1'] is too long
	'allwinner,sun4i-a10-sram-a3-a4' was expected
	'allwinner,sun4i-a10-sram-c1' was expected
	'allwinner,sun4i-a10-sram-d' was expected
	'allwinner,sun50i-a64-sram-c' was expected
	'allwinner,sun8i-v3s-sram-c' is not one of ['allwinner,sun5i-a13-sram-a3-a4', 'allwinner,sun7i-a20-sram-a3-a4']
	'allwinner,sun8i-v3s-sram-c' is not one of ['allwinner,sun5i-a13-sram-c1', 'allwinner,sun7i-a20-sram-c1', 'allwinner,sun8i-a23-sram-c1', 'allwinner,sun8i-h3-sram-c1', 'allwinner,sun8i-r40-sram-c1', 'allwinner,sun50i-a64-sram-c1', 'allwinner,sun50i-h5-sram-c1', 'allwinner,sun50i-h6-sram-c1']
	'allwinner,sun8i-v3s-sram-c' is not one of ['allwinner,suniv-f1c100s-sram-d', 'allwinner,sun5i-a13-sram-d', 'allwinner,sun7i-a20-sram-d']
	'allwinner,sun50i-h6-sram-c' was expected
	from schema $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: /soc/syscon@3000000/sram@20000/sram-section@0: failed to match any schema with compatible: ['allwinner,sun8i-v3s-sram-c', 'allwinner,sun4i-a10-sram-c1']
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: hwlock@3005000: '#hwlock-cells' is a required property
	from schema $id: http://devicetree.org/schemas/hwlock/allwinner,sun6i-a31-hwspinlock.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: hwlock@3005000: 'clock-names', 'interrupts', 'reset-names' do not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/hwlock/allwinner,sun6i-a31-hwspinlock.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: hstimer@3008000: interrupts: [[0, 55, 4], [0, 56, 4]] is too short
	from schema $id: http://devicetree.org/schemas/timer/allwinner,sun5i-a13-hstimer.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: phy@4100400: reg: [[68158464, 256], [68163584, 256]] is too short
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: phy@4100400: reg-names: ['phy_ctrl', 'pmu0'] is too short
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: phy@4100400: clocks: [[1, 94]] is too short
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: phy@4100400: clock-names: ['usb0_phy'] is too short
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: phy@4100400: resets: [[1, 38]] is too short
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: phy@4100400: reset-names: ['usb0_reset'] is too short
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: phy@4100400: 'usb0_id_det-gpio' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: clock-controller@7010000: clocks: [[4], [5, 2], [5, 0], [1, 10], [1, 19]] is too long
	from schema $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: clock-controller@7010000: clock-names:1: 'losc' was expected
	from schema $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: clock-controller@7010000: clock-names:2: 'iosc' was expected
	from schema $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: clock-controller@7010000: clock-names: ['hosc', 'iosc', 'losc', 'pll-periph', 'pll-audio'] is too long
	from schema $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: clock-controller@7010000: clocks: [[4], [5, 2], [5, 0], [1, 10], [1, 19]] is too long
	from schema $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: clock-controller@7010000: clock-names: ['hosc', 'iosc', 'losc', 'pll-periph', 'pll-audio'] is too long
	from schema $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: intc-nmi@7010320: $nodename:0: 'intc-nmi@7010320' does not match '^interrupt-controller(@[0-9a-f,]+)*$'
	from schema $id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: intc-nmi@7010320: Unevaluated properties are not allowed ('#address-cells' was unexpected)
	from schema $id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: rtc@7090000: clocks: [[17, 4]] is too short
	from schema $id: http://devicetree.org/schemas/rtc/allwinner,sun6i-a31-rtc.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: rtc@7090000: clock-names: ['bus'] is too short
	from schema $id: http://devicetree.org/schemas/rtc/allwinner,sun6i-a31-rtc.yaml#
arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dtb: rtc@7090000: 'resets', 'wakeup-source' do not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/rtc/allwinner,sun6i-a31-rtc.yaml#

Re: [PATCH v2 09/10] ARM: dts: sun8i: add DTSI file for V853

[Andre Przywara]

On Wed,  5 Feb 2025 13:52:24 +0100
Andras Szemzo <szemzo.andras@gmail.com> wrote:

Hi,

> V853/V851 is a new SoC by Allwinner. Add a basic dtsi file for it.
> 
> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
> ---
>  arch/arm/boot/dts/allwinner/sun8i-v853.dtsi | 656 ++++++++++++++++++++
>  1 file changed, 656 insertions(+)
>  create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
> 
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
> new file mode 100644
> index 000000000000..8b82b8783127
> --- /dev/null
> +++ b/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
> @@ -0,0 +1,656 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
> +// Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com>
> +
> +#include <dt-bindings/clock/sun6i-rtc.h>
> +#include <dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h>
> +#include <dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h>
> +#include <dt-bindings/clock/allwinner,sun8i-v853-ccu.h>
> +#include <dt-bindings/reset/allwinner,sun8i-v853-ccu.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/allwinner,sun8i-v853-ppu.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	dcxo: dcxo-clk {

What's people's opinion about the node name? Traditionally we call this
"osc24M", in all the other SoCs except D1 and A100. So is this the new
black?

> +		compatible = "fixed-clock";
> +		clock-output-names = "osc24M";
> +		#clock-cells = <0>;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a7","arm,armv7";
> +			reg = <0>;
> +			clocks = <&ccu CLK_CPU>;
> +			clock-names = "cpu";
> +			clock-frequency = <912000000>;
> +			clock-latency = <200000>;
> +			cooling-min-level = <5>;
> +			cooling-max-level = <0>;
> +			#cooling-cells = <2>; /* min followed by max */
> +			dynamic-power-coefficient = <142>;
> +		};
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a7-pmu";
> +		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-parent = <&gic>;

Please move interrupt-parent to the root node, as the first property. Then
you can lose it here, and in the timer and soc node.

> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> +		clock-frequency = <24000000>;

Please remove this, and let the firmware set CNTFRQ. U-Boot does this
automatically (in nonsec_virt.S), and it should be just a few lines to add
to awboot's arch/arm32/arch_timer.c.

Or, even better: provide proper U-Boot support ;-)

> +		interrupt-parent = <&gic>;
> +		arm,cpu-registers-not-fw-configured;

Same here, please fix your firmware to configure the non-secure world
correctly, and remove this property.
I am happy to help you with that.

> +		arm,no-tick-in-suspend;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		ranges;
> +		interrupt-parent = <&gic>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		dma-noncoherent;
> +
> +		pio: pinctrl@2000000 {
> +			compatible = "allwinner,sun8i-v853-pinctrl";
> +			reg = <0x2000000 0x800>;
> +			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_APB0>, <&dcxo>, <&rtc CLK_OSC32K>;
> +			clock-names = "apb", "hosc", "losc";
> +			gpio-controller;
> +			interrupt-controller;
> +			#gpio-cells = <3>;
> +			#interrupt-cells = <3>;
> +
> +			/omit-if-no-ref/

You don't need omit-if-no-ref for *all* nodes, just the more obscure ones,
which are only used by one or two boards.
Here I'd say, just have it for: uart2, dsi, spi3, i2c3, and remove that
tag for the others.

> +			uart0_ph9_pins: uart0-ph9-pins {
> +				pins = "PH9", "PH10";
> +				function = "uart0";
> +				allwinner,pinmux = <5>;
> +			};
> +
> +			/omit-if-no-ref/
> +			uart2_pe12_pins: uart2-pe12-pins {
> +				pins = "PE12", "PE13";
> +				function = "uart2";
> +				allwinner,pinmux = <6>;
> +			};
> +
> +			/omit-if-no-ref/
> +			dsi_2lane_pins: dsi-2lane-pins {
> +				pins = "PD1", "PD2", "PD3", "PD4", "PD5", "PD6";
> +				function = "dsi";
> +				allwinner,pinmux = <5>;
> +			};
> +
> +			/omit-if-no-ref/
> +			spi0_pins: spi0-pins {
> +				pins = "PC0", "PC1", "PC2", "PC3", "PC4", "PC5";
> +				function = "spi0";
> +				allwinner,pinmux = <4>;
> +			};
> +
> +			/omit-if-no-ref/
> +			spi3_pins: spi3-pins {
> +				pins = "PH11", "PH12", "PH13", "PH14";
> +				function = "spi3";
> +				allwinner,pinmux = <6>;
> +			};
> +
> +			/omit-if-no-ref/
> +			i2c2_ph11_pins: i2c2-ph11-pins {
> +				pins = "PH11", "PH12";
> +				function = "i2c2";
> +				allwinner,pinmux = <5>;
> +			};
> +
> +			/omit-if-no-ref/
> +			i2c3_ph13_pins: i2c3-ph13-pins {
> +				pins = "PH13", "PH14";
> +				function = "i2c3";
> +				allwinner,pinmux = <5>;
> +			};
> +
> +			/omit-if-no-ref/
> +			mmc0_pins: mmc0-pins {
> +				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
> +				function = "sdc0";
> +				allwinner,pinmux = <2>;
> +				drive-strength = <30>;
> +				bias-pull-up;
> +			};
> +
> +			/omit-if-no-ref/
> +			mmc1_pins: mmc1-pins {
> +				pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5";
> +				function = "sdc1";
> +				allwinner,pinmux = <6>;
> +				drive-strength = <30>;
> +				bias-pull-up;
> +			};
> +
> +			/omit-if-no-ref/
> +			rmii_pe_pins: rmii-pe-pins {
> +				pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> +				       "PE5", "PE6", "PE7", "PE8", "PE9";
> +				function = "emac";
> +				allwinner,pinmux = <3>;
> +			};
> +		};
> +
> +		ccu: clock-controller@2001000 {
> +			compatible = "allwinner,sun8i-v853-ccu";
> +			reg = <0x2001000 0x1000>;
> +			clocks = <&dcxo>,
> +				 <&rtc CLK_IOSC>,
> +				 <&rtc CLK_OSC32K>;
> +			clock-names = "hosc", "iosc", "losc";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		gpadc: adc@2009000 {
> +			compatible = "allwinner,sun20i-d1-gpadc";

Please use a fallback notation:
	compatible = "allwinner,sun8i-v853-gpadc",
		     "allwinner,sun20i-d1-gpadc";

This allows to later add quirks should we need some for this SoC. 
And this requires a binding patch.

> +			reg = <0x2009000 0x0400>;
> +			clocks = <&ccu CLK_BUS_GPADC>;
> +			resets = <&ccu RST_BUS_GPADC>;
> +			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +			#io-channel-cells = <1>;
> +		};
> +
> +		i2s0: i2s@2032000 {
> +			compatible = "allwinner,sun50i-r329-i2s";

Same here, fallback compatible.

> +			reg = <0x2032000 0x1000>;
> +			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2S0>,
> +				 <&ccu CLK_I2S0>;
> +			clock-names = "apb", "mod";
> +			resets = <&ccu RST_BUS_I2S0>;
> +			dmas = <&dma 3>, <&dma 3>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#sound-dai-cells = <0>;
> +		};
> +
> +		i2s1: i2s@2033000 {
> +			compatible = "allwinner,sun50i-r329-i2s";
> +			reg = <0x2033000 0x1000>;
> +			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2S1>,
> +				 <&ccu CLK_I2S1>;
> +			clock-names = "apb", "mod";
> +			resets = <&ccu RST_BUS_I2S1>;
> +			dmas = <&dma 4>, <&dma 4>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#sound-dai-cells = <0>;
> +		};
> +
> +		timer: timer@2050000 {
> +			compatible = "allwinner,sun20i-d1-timer",

This should be allwinner,sun8i-v853-timer.

> +				     "allwinner,sun8i-a23-timer";
> +			reg = <0x2050000 0xa0>;
> +			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&dcxo>;
> +		};
> +
> +		wdt: watchdog@20500a0 {
> +			compatible = "allwinner,sun20i-d1-wdt-reset",
> +				     "allwinner,sun20i-d1-wdt";

Same here, use a more specific compatible, then the sun20i as a fallback.

> +			reg = <0x20500a0 0x20>;
> +			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&dcxo>, <&rtc CLK_OSC32K>;
> +			clock-names = "hosc", "losc";
> +			status = "reserved";
> +		};
> +
> +		uart0: serial@2500000 {
> +			compatible = "snps,dw-apb-uart";

The UART is an exception, it's just the generic Synopsis name, so this is
fine.

> +			reg = <0x2500000 0x400>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_UART0>;
> +			resets = <&ccu RST_BUS_UART0>;
> +			dmas = <&dma 14>, <&dma 14>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@2500400 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x2500400 0x400>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_UART1>;
> +			resets = <&ccu RST_BUS_UART1>;
> +			dmas = <&dma 15>, <&dma 15>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@2500800 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x2500800 0x400>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_UART2>;
> +			resets = <&ccu RST_BUS_UART2>;
> +			dmas = <&dma 16>, <&dma 16>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@2500c00 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x2500c00 0x400>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_UART3>;
> +			resets = <&ccu RST_BUS_UART3>;
> +			dmas = <&dma 17>, <&dma 17>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +		};
> +
> +		i2c0: i2c@2502000 {
> +			compatible = "allwinner,sun8i-v536-i2c",
> +				     "allwinner,sun6i-a31-i2c";

This needs three compatible strings:
			compatible = "allwinner,sun8i-v853-i2c",
				     "allwinner,sun8i-v536-i2c",
				     "allwinner,sun6i-a31-i2c";

> +			reg = <0x2502000 0x400>;
> +			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C0>;
> +			resets = <&ccu RST_BUS_I2C0>;
> +			dmas = <&dma 43>, <&dma 43>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c1: i2c@2502400 {
> +			compatible = "allwinner,sun8i-v536-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x2502400 0x400>;
> +			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C1>;
> +			resets = <&ccu RST_BUS_I2C1>;
> +			dmas = <&dma 44>, <&dma 44>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c2: i2c@2502800 {
> +			compatible = "allwinner,sun8i-v536-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x2502800 0x400>;
> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C2>;
> +			resets = <&ccu RST_BUS_I2C2>;
> +			dmas = <&dma 45>, <&dma 45>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c3: i2c@2502c00 {
> +			compatible = "allwinner,sun8i-v536-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x2502c00 0x400>;
> +			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C3>;
> +			resets = <&ccu RST_BUS_I2C3>;
> +			dmas = <&dma 46>, <&dma 46>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c4: i2c@2503000 {
> +			compatible = "allwinner,sun8i-v536-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x2503000 0x400>;
> +			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C4>;
> +			resets = <&ccu RST_BUS_I2C4>;
> +			dmas = <&dma 47>, <&dma 47>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		syscon: syscon@3000000 {
> +			compatible = "allwinner,sun8i-h3-system-control";

I think you got the idea by now, fallbacks ... and for the others below as
well.

> +			reg = <0x3000000 0x1000>;
> +			ranges;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			sram_c: sram@20000 {
> +				compatible = "mmio-sram";
> +				reg = <0x00020000 0x21000>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0 0x00020000 0x21000>;
> +
> +				ve_sram: sram-section@0 {
> +				    compatible = "allwinner,sun8i-v3s-sram-c", 
> +						 "allwinner,sun4i-a10-sram-c1";
> +				    reg = <0x000000 0x21000>;
> +				};
> +			};
> +		};
> +
> +		dma: dma-controller@3002000 {
> +			compatible = "allwinner,sun20i-d1-dma";
> +			reg = <0x3002000 0x1000>;
> +			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
> +			clock-names = "bus", "mbus";
> +			resets = <&ccu RST_BUS_DMA>;
> +			dma-channels = <16>;
> +			dma-requests = <48>;
> +			#dma-cells = <1>;
> +		};
> +
> +		hwspinlock: hwlock@3005000 {
> +		    compatible = "allwinner,sun6i-a31-hwspinlock";
> +			reg = <0x3005000 0x1000>;
> +			clocks = <&ccu CLK_BUS_SPINLOCK>;
> +			clock-names = "ahb";
> +			resets = <&ccu RST_BUS_SPINLOCK>;
> +			reset-names = "ahb";
> +			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		sid: efuse@3006000 {
> +			compatible = "allwinner,sun20i-d1-sid";
> +			reg = <0x3006000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			ths_calib: ths-calib@14 {
> +				reg = <0x14 0x8>;
> +			};
> +		};
> +
> +		hstimer@3008000 {
> +			compatible = "allwinner,sun7i-a20-hstimer";
> +			reg = <0x03008000 0x1000>;
> +			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_HSTIMER>;
> +		};
> +
> +		gic: interrupt-controller@3021000 {
> +			compatible = "arm,gic-400";

(no fallbacks needed here, it's an actual GIC-400)

> +			reg = <0x03021000 0x1000>,	/* GIC Dist */
> +			      <0x03022000 0x2000>,	/* GIC CPU */
> +			      <0x03024000 0x2000>,	/* GIC VCPU Control */
> +			      <0x03026000 0x2000>;	/* GIC VCPU */
> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +		};
> +
> +		mbus: dram-controller@3102000 {
> +			compatible = "allwinner,sun20i-d1-mbus";
> +			reg = <0x3102000 0x1000>,
> +			      <0x3103000 0x1000>;
> +			reg-names = "mbus", "dram";
> +			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_MBUS>,
> +				 <&ccu CLK_DRAM>,
> +				 <&ccu CLK_BUS_DRAM>;
> +			clock-names = "mbus", "dram", "bus";
> +			dma-ranges = <0 0x40000000 0x80000000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			#interconnect-cells = <1>;
> +		};
> +
> +		mmc0: mmc@4020000 {
> +			compatible = "allwinner,sun20i-d1-mmc";
> +			reg = <0x4020000 0x1000>;
> +			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> +			clock-names = "ahb", "mmc";
> +			resets = <&ccu RST_BUS_MMC0>;
> +			reset-names = "ahb";
> +			no-sdio;
> +			no-mmc;

I don't think we use those two properties in mainline?

> +			cap-sd-highspeed;
> +			max-frequency = <150000000>;
> +			mmc-ddr-1_8v;

This looks wrong here, definitely you should not have voltage dependent
properties in the SoC .dtsi.

And you can add the pinctrl properties already here, since there is only
one set of pins for MMC0.

> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc1: mmc@4021000 {
> +			compatible = "allwinner,sun20i-d1-mmc";
> +			reg = <0x4021000 0x1000>;
> +			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> +			clock-names = "ahb", "mmc";
> +			resets = <&ccu RST_BUS_MMC1>;
> +			reset-names = "ahb";
> +			cap-sd-highspeed;
> +			cap-mmc-highspeed;
> +			max-frequency = <150000000>;
> +			mmc-ddr-1_8v;

same here, please remove.

> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc2: mmc@4022000 {
> +			compatible = "allwinner,sun20i-d1-mmc";
> +			reg = <0x4022000 0x1000>;
> +			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> +			clock-names = "ahb", "mmc";
> +			resets = <&ccu RST_BUS_MMC2>;
> +			reset-names = "ahb";
> +			no-sdio;
> +			no-sd;
> +			cap-mmc-highspeed;
> +			max-frequency = <150000000>;
> +			mmc-ddr-1_8v;
> +			mmc-ddr-3_3v;

Please leave that to the board DTs to set, they know which voltage PortC is
running on.

> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		spi0: spi@4025000 {
> +			compatible = "allwinner,sun50i-r329-spi";
> +			reg = <0x4025000 0x1000>;
> +			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> +			clock-names = "ahb", "mod";
> +			resets = <&ccu RST_BUS_SPI0>;
> +			dmas = <&dma 22>, <&dma 22>;
> +			dma-names = "rx", "tx";
> +			num-cs = <1>;

Is that so? I see SPI0_CS0, SPI0_CS1, SPI1_CS0, SPI1_CS1 pins.

> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		spi1: spi@4026000 {
> +			compatible = "allwinner,sun50i-r329-spi-dbi",
> +				     "allwinner,sun50i-r329-spi";
> +			reg = <0x4026000 0x1000>;
> +			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> +			clock-names = "ahb", "mod";
> +			resets = <&ccu RST_BUS_SPI1>;
> +			dmas = <&dma 23>, <&dma 23>;
> +			dma-names = "rx", "tx";
> +			num-cs = <1>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		spi2: spi@4027000 {
> +			compatible = "allwinner,sun50i-r329-spi";
> +			reg = <0x4027000 0x1000>;
> +			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
> +			clock-names = "ahb", "mod";
> +			resets = <&ccu RST_BUS_SPI2>;
> +			dmas = <&dma 24>, <&dma 24>;
> +			dma-names = "rx", "tx";
> +			num-cs = <1>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		spi3: spi@4028000 {
> +			compatible = "allwinner,sun50i-r329-spi";
> +			reg = <0x4028000 0x1000>;
> +			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
> +			clock-names = "ahb", "mod";
> +			resets = <&ccu RST_BUS_SPI3>;
> +			dmas = <&dma 25>, <&dma 25>;
> +			dma-names = "rx", "tx";
> +			num-cs = <1>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		usb_otg: usb@4100000 {
> +			compatible = "allwinner,sun8i-a33-musb";
> +			reg = <0x4100000 0x400>;
> +			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "mc";
> +			clocks = <&ccu CLK_BUS_OTG>;
> +			resets = <&ccu RST_BUS_OTG>;
> +			extcon = <&usbphy 0>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		usbphy: phy@4100400 {
> +			compatible = "allwinner,sun8i-v853-usb-phy";
> +			reg = <0x4100400 0x100>,
> +			      <0x4101800 0x100>;
> +			reg-names = "phy_ctrl",
> +				    "pmu0";
> +			clocks = <&ccu CLK_USB_OHCI>;
> +			clock-names = "usb0_phy";
> +			resets = <&ccu RST_USB_PHY>;
> +			reset-names = "usb0_reset";
> +			status = "disabled";
> +			#phy-cells = <1>;
> +		};
> +
> +		ehci0: usb@4101000 {
> +			compatible = "generic-ehci";
> +			reg = <0x4101000 0x100>;
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI>,
> +				 <&ccu CLK_BUS_EHCI>,
> +				 <&ccu CLK_USB_OHCI>;
> +			resets = <&ccu RST_BUS_OHCI>,
> +				 <&ccu RST_BUS_EHCI>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ohci0: usb@4101400 {
> +			compatible = "generic-ohci";
> +			reg = <0x4101400 0x100>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI>,
> +				 <&ccu CLK_USB_OHCI>;
> +			resets = <&ccu RST_BUS_OHCI>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ppu: power-controller@7001000 {
> +			compatible = "allwinner,sun8i-v853-ppu";
> +			reg = <0x7001000 0x400>;
> +			clocks = <&r_ccu CLK_BUS_R_PPU>;
> +			resets = <&r_ccu RST_BUS_R_PPU>;
> +			#power-domain-cells = <1>;
> +		};
> +
> +		r_ccu: clock-controller@7010000 {
> +			compatible = "allwinner,sun8i-v853-r-ccu";
> +			reg = <0x7010000 0x230>;
> +			clocks = <&dcxo>,
> +				 <&rtc CLK_IOSC>,
> +				 <&rtc CLK_OSC32K>,
> +				 <&ccu CLK_PLL_PERIPH_200M>,
> +				 <&ccu CLK_PLL_AUDIO_4X>;
> +			clock-names = "hosc",
> +				      "iosc",
> +				      "losc",
> +				      "pll-periph",
> +				      "pll-audio";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		nmi_intc: intc-nmi@7010320 {
> +			compatible = "allwinner,sun9i-a80-nmi";
> +			interrupt-parent = <&gic>;

not needed

> +			#interrupt-cells = <2>;
> +			#address-cells = <0>;
> +			interrupt-controller;
> +			reg = <0x07010320 0xc>;
> +			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;

reg and interrupts typically come right after compatible

That's it for now, I will check all the numbers against the manual later,
and verify the clock names and such.

Cheers,
Andre

> +		};
> +
> +		rtc: rtc@7090000 {
> +			compatible = "allwinner,sun50i-r329-rtc";
> +			reg = <0x7090000 0x400>;
> +			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&r_ccu CLK_BUS_R_RTC>;
> +			clock-names = "bus";
> +			resets = <&r_ccu RST_BUS_R_RTC>;
> +			wakeup-source;
> +			#clock-cells = <1>;
> +		};
> +	};
> +};

Re: [PATCH v2 09/10] ARM: dts: sun8i: add DTSI file for V853

[Andre Przywara]

On Wed,  5 Feb 2025 13:52:24 +0100
Andras Szemzo <szemzo.andras@gmail.com> wrote:

Hi,

those comments go on top of those in my previous reply:

> V853/V851 is a new SoC by Allwinner. Add a basic dtsi file for it.
> 
> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
> ---
>  arch/arm/boot/dts/allwinner/sun8i-v853.dtsi | 656 ++++++++++++++++++++
>  1 file changed, 656 insertions(+)
>  create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
> 
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
> new file mode 100644
> index 000000000000..8b82b8783127
> --- /dev/null
> +++ b/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
> @@ -0,0 +1,656 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
> +// Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com>
> +
> +#include <dt-bindings/clock/sun6i-rtc.h>
> +#include <dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h>
> +#include <dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h>
> +#include <dt-bindings/clock/allwinner,sun8i-v853-ccu.h>
> +#include <dt-bindings/reset/allwinner,sun8i-v853-ccu.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/allwinner,sun8i-v853-ppu.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	dcxo: dcxo-clk {
> +		compatible = "fixed-clock";
> +		clock-output-names = "osc24M";
> +		#clock-cells = <0>;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a7","arm,armv7";

The binding says to only give the CPU name, so just the first string,
no fallback.

> +			reg = <0>;
> +			clocks = <&ccu CLK_CPU>;
> +			clock-names = "cpu";
> +			clock-frequency = <912000000>;

Please remove this, it only makes sense for a constant frequency, which
is contradicted by the previous two properties.

> +			clock-latency = <200000>;
> +			cooling-min-level = <5>;
> +			cooling-max-level = <0>;
> +			#cooling-cells = <2>; /* min followed by max */
> +			dynamic-power-coefficient = <142>;
> +		};
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a7-pmu";
> +		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;

What's the second interrupt for? I'd assume that's for a second core?
Can you check that? Use "perf record" (perf stat does not trigger
interrupts), and then check the counter in /proc/interrupts.

> +		interrupt-parent = <&gic>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

This should be GIC_CPU_MASK_SIMPLE(1) for a single core CPU.

> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> +		clock-frequency = <24000000>;
> +		interrupt-parent = <&gic>;
> +		arm,cpu-registers-not-fw-configured;
> +		arm,no-tick-in-suspend;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		ranges;
> +		interrupt-parent = <&gic>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		dma-noncoherent;
> +
> +		pio: pinctrl@2000000 {
> +			compatible = "allwinner,sun8i-v853-pinctrl";
> +			reg = <0x2000000 0x800>;
> +			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_APB0>, <&dcxo>, <&rtc CLK_OSC32K>;
> +			clock-names = "apb", "hosc", "losc";
> +			gpio-controller;
> +			interrupt-controller;
> +			#gpio-cells = <3>;
> +			#interrupt-cells = <3>;
> +
> +			/omit-if-no-ref/
> +			uart0_ph9_pins: uart0-ph9-pins {
> +				pins = "PH9", "PH10";
> +				function = "uart0";
> +				allwinner,pinmux = <5>;
> +			};
> +
> +			/omit-if-no-ref/
> +			uart2_pe12_pins: uart2-pe12-pins {

There is only one set of UART2 pins in PortE, so drop the pin number:
	uart2_pe_pins: uart-pe-pins {

> +				pins = "PE12", "PE13";
> +				function = "uart2";
> +				allwinner,pinmux = <6>;
> +			};
> +
> +			/omit-if-no-ref/
> +			dsi_2lane_pins: dsi-2lane-pins {
> +				pins = "PD1", "PD2", "PD3", "PD4", "PD5", "PD6";
> +				function = "dsi";
> +				allwinner,pinmux = <5>;
> +			};
> +
> +			/omit-if-no-ref/
> +			spi0_pins: spi0-pins {

SPI0 can be muxed to PortF as well, so please use spi0_pc_pins.

> +				pins = "PC0", "PC1", "PC2", "PC3", "PC4", "PC5";

This includes the optional WP and HOLD pins, I think they should be
separate? So add a second node, with just PC4 and PC5, and then
reference both nodes in your SPI flash node, in the board .dts.
The base pins should be untagged, but the optional pins should carry
the omit-if-no-ref tag.

> +				function = "spi0";
> +				allwinner,pinmux = <4>;
> +			};
> +
> +			/omit-if-no-ref/
> +			spi3_pins: spi3-pins {
> +				pins = "PH11", "PH12", "PH13", "PH14";
> +				function = "spi3";
> +				allwinner,pinmux = <6>;
> +			};
> +
> +			/omit-if-no-ref/
> +			i2c2_ph11_pins: i2c2-ph11-pins {
> +				pins = "PH11", "PH12";
> +				function = "i2c2";
> +				allwinner,pinmux = <5>;
> +			};
> +
> +			/omit-if-no-ref/
> +			i2c3_ph13_pins: i2c3-ph13-pins {
> +				pins = "PH13", "PH14";
> +				function = "i2c3";
> +				allwinner,pinmux = <5>;
> +			};
> +
> +			/omit-if-no-ref/
> +			mmc0_pins: mmc0-pins {
> +				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
> +				function = "sdc0";
> +				allwinner,pinmux = <2>;
> +				drive-strength = <30>;
> +				bias-pull-up;
> +			};
> +
> +			/omit-if-no-ref/
> +			mmc1_pins: mmc1-pins {

mmc1_pe_pins

> +				pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5";
> +				function = "sdc1";
> +				allwinner,pinmux = <6>;
> +				drive-strength = <30>;
> +				bias-pull-up;
> +			};
> +
> +			/omit-if-no-ref/
> +			rmii_pe_pins: rmii-pe-pins {
> +				pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> +				       "PE5", "PE6", "PE7", "PE8", "PE9";
> +				function = "emac";
> +				allwinner,pinmux = <3>;
> +			};
> +		};

Verified that the pin numbers and the pinmux match the function in the
manual.

> +
> +		ccu: clock-controller@2001000 {
> +			compatible = "allwinner,sun8i-v853-ccu";
> +			reg = <0x2001000 0x1000>;
> +			clocks = <&dcxo>,
> +				 <&rtc CLK_IOSC>,
> +				 <&rtc CLK_OSC32K>;
> +			clock-names = "hosc", "iosc", "losc";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		gpadc: adc@2009000 {
> +			compatible = "allwinner,sun20i-d1-gpadc";
> +			reg = <0x2009000 0x0400>;
> +			clocks = <&ccu CLK_BUS_GPADC>;
> +			resets = <&ccu RST_BUS_GPADC>;
> +			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +			#io-channel-cells = <1>;
> +		};
> +
> +		i2s0: i2s@2032000 {
> +			compatible = "allwinner,sun50i-r329-i2s";
> +			reg = <0x2032000 0x1000>;
> +			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2S0>,
> +				 <&ccu CLK_I2S0>;
> +			clock-names = "apb", "mod";
> +			resets = <&ccu RST_BUS_I2S0>;
> +			dmas = <&dma 3>, <&dma 3>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#sound-dai-cells = <0>;
> +		};
> +
> +		i2s1: i2s@2033000 {
> +			compatible = "allwinner,sun50i-r329-i2s";
> +			reg = <0x2033000 0x1000>;
> +			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2S1>,
> +				 <&ccu CLK_I2S1>;
> +			clock-names = "apb", "mod";
> +			resets = <&ccu RST_BUS_I2S1>;
> +			dmas = <&dma 4>, <&dma 4>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#sound-dai-cells = <0>;
> +		};
> +
> +		timer: timer@2050000 {
> +			compatible = "allwinner,sun20i-d1-timer",
> +				     "allwinner,sun8i-a23-timer";
> +			reg = <0x2050000 0xa0>;
> +			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;

Shouldn't there be four interrupts, for the four timers?

> +			clocks = <&dcxo>;
> +		};
> +
> +		wdt: watchdog@20500a0 {
> +			compatible = "allwinner,sun20i-d1-wdt-reset",
> +				     "allwinner,sun20i-d1-wdt";
> +			reg = <0x20500a0 0x20>;
> +			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&dcxo>, <&rtc CLK_OSC32K>;
> +			clock-names = "hosc", "losc";
> +			status = "reserved";

Who is this reserved for? Should be "okay", no?

> +		};
> +
> +		uart0: serial@2500000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x2500000 0x400>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_UART0>;
> +			resets = <&ccu RST_BUS_UART0>;
> +			dmas = <&dma 14>, <&dma 14>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@2500400 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x2500400 0x400>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_UART1>;
> +			resets = <&ccu RST_BUS_UART1>;
> +			dmas = <&dma 15>, <&dma 15>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@2500800 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x2500800 0x400>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_UART2>;
> +			resets = <&ccu RST_BUS_UART2>;
> +			dmas = <&dma 16>, <&dma 16>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@2500c00 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x2500c00 0x400>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_UART3>;
> +			resets = <&ccu RST_BUS_UART3>;
> +			dmas = <&dma 17>, <&dma 17>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +		};
> +
> +		i2c0: i2c@2502000 {
> +			compatible = "allwinner,sun8i-v536-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x2502000 0x400>;
> +			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C0>;
> +			resets = <&ccu RST_BUS_I2C0>;
> +			dmas = <&dma 43>, <&dma 43>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c1: i2c@2502400 {
> +			compatible = "allwinner,sun8i-v536-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x2502400 0x400>;
> +			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C1>;
> +			resets = <&ccu RST_BUS_I2C1>;
> +			dmas = <&dma 44>, <&dma 44>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c2: i2c@2502800 {
> +			compatible = "allwinner,sun8i-v536-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x2502800 0x400>;
> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C2>;
> +			resets = <&ccu RST_BUS_I2C2>;
> +			dmas = <&dma 45>, <&dma 45>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c3: i2c@2502c00 {
> +			compatible = "allwinner,sun8i-v536-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x2502c00 0x400>;
> +			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C3>;
> +			resets = <&ccu RST_BUS_I2C3>;
> +			dmas = <&dma 46>, <&dma 46>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c4: i2c@2503000 {
> +			compatible = "allwinner,sun8i-v536-i2c",
> +				     "allwinner,sun6i-a31-i2c";
> +			reg = <0x2503000 0x400>;
> +			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_I2C4>;
> +			resets = <&ccu RST_BUS_I2C4>;
> +			dmas = <&dma 47>, <&dma 47>;
> +			dma-names = "rx", "tx";
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		syscon: syscon@3000000 {
> +			compatible = "allwinner,sun8i-h3-system-control";
> +			reg = <0x3000000 0x1000>;
> +			ranges;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			sram_c: sram@20000 {
> +				compatible = "mmio-sram";
> +				reg = <0x00020000 0x21000>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				ranges = <0 0x00020000 0x21000>;
> +
> +				ve_sram: sram-section@0 {

The manual says "Using ISP SRAM". Do you know what it really is?

> +				    compatible = "allwinner,sun8i-v3s-sram-c", 
> +						 "allwinner,sun4i-a10-sram-c1";
> +				    reg = <0x000000 0x21000>;
> +				};
> +			};
> +		};
> +
> +		dma: dma-controller@3002000 {
> +			compatible = "allwinner,sun20i-d1-dma";
> +			reg = <0x3002000 0x1000>;
> +			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
> +			clock-names = "bus", "mbus";
> +			resets = <&ccu RST_BUS_DMA>;
> +			dma-channels = <16>;
> +			dma-requests = <48>;
> +			#dma-cells = <1>;
> +		};
> +
> +		hwspinlock: hwlock@3005000 {
> +		    compatible = "allwinner,sun6i-a31-hwspinlock";
> +			reg = <0x3005000 0x1000>;
> +			clocks = <&ccu CLK_BUS_SPINLOCK>;
> +			clock-names = "ahb";
> +			resets = <&ccu RST_BUS_SPINLOCK>;
> +			reset-names = "ahb";
> +			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		sid: efuse@3006000 {
> +			compatible = "allwinner,sun20i-d1-sid";
> +			reg = <0x3006000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			ths_calib: ths-calib@14 {
> +				reg = <0x14 0x8>;
> +			};
> +		};
> +
> +		hstimer@3008000 {
> +			compatible = "allwinner,sun7i-a20-hstimer";
> +			reg = <0x03008000 0x1000>;
> +			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_HSTIMER>;
> +		};
> +
> +		gic: interrupt-controller@3021000 {
> +			compatible = "arm,gic-400";
> +			reg = <0x03021000 0x1000>,	/* GIC Dist */
> +			      <0x03022000 0x2000>,	/* GIC CPU */
> +			      <0x03024000 0x2000>,	/* GIC VCPU Control */
> +			      <0x03026000 0x2000>;	/* GIC VCPU */
> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;

GIC_CPU_MASK_SIMPLE(1)

> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +		};
> +
> +		mbus: dram-controller@3102000 {
> +			compatible = "allwinner,sun20i-d1-mbus";
> +			reg = <0x3102000 0x1000>,
> +			      <0x3103000 0x1000>;
> +			reg-names = "mbus", "dram";
> +			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_MBUS>,
> +				 <&ccu CLK_DRAM>,
> +				 <&ccu CLK_BUS_DRAM>;
> +			clock-names = "mbus", "dram", "bus";
> +			dma-ranges = <0 0x40000000 0x80000000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			#interconnect-cells = <1>;
> +		};
> +
> +		mmc0: mmc@4020000 {
> +			compatible = "allwinner,sun20i-d1-mmc";
> +			reg = <0x4020000 0x1000>;
> +			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> +			clock-names = "ahb", "mmc";
> +			resets = <&ccu RST_BUS_MMC0>;
> +			reset-names = "ahb";
> +			no-sdio;
> +			no-mmc;
> +			cap-sd-highspeed;
> +			max-frequency = <150000000>;
> +			mmc-ddr-1_8v;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc1: mmc@4021000 {
> +			compatible = "allwinner,sun20i-d1-mmc";
> +			reg = <0x4021000 0x1000>;
> +			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> +			clock-names = "ahb", "mmc";
> +			resets = <&ccu RST_BUS_MMC1>;
> +			reset-names = "ahb";
> +			cap-sd-highspeed;
> +			cap-mmc-highspeed;
> +			max-frequency = <150000000>;
> +			mmc-ddr-1_8v;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc2: mmc@4022000 {
> +			compatible = "allwinner,sun20i-d1-mmc";
> +			reg = <0x4022000 0x1000>;
> +			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> +			clock-names = "ahb", "mmc";
> +			resets = <&ccu RST_BUS_MMC2>;
> +			reset-names = "ahb";
> +			no-sdio;
> +			no-sd;
> +			cap-mmc-highspeed;
> +			max-frequency = <150000000>;
> +			mmc-ddr-1_8v;
> +			mmc-ddr-3_3v;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		spi0: spi@4025000 {
> +			compatible = "allwinner,sun50i-r329-spi";
> +			reg = <0x4025000 0x1000>;
> +			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> +			clock-names = "ahb", "mod";
> +			resets = <&ccu RST_BUS_SPI0>;
> +			dmas = <&dma 22>, <&dma 22>;
> +			dma-names = "rx", "tx";
> +			num-cs = <1>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		spi1: spi@4026000 {
> +			compatible = "allwinner,sun50i-r329-spi-dbi",
> +				     "allwinner,sun50i-r329-spi";
> +			reg = <0x4026000 0x1000>;
> +			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> +			clock-names = "ahb", "mod";
> +			resets = <&ccu RST_BUS_SPI1>;
> +			dmas = <&dma 23>, <&dma 23>;
> +			dma-names = "rx", "tx";
> +			num-cs = <1>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		spi2: spi@4027000 {
> +			compatible = "allwinner,sun50i-r329-spi";
> +			reg = <0x4027000 0x1000>;
> +			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
> +			clock-names = "ahb", "mod";
> +			resets = <&ccu RST_BUS_SPI2>;
> +			dmas = <&dma 24>, <&dma 24>;
> +			dma-names = "rx", "tx";
> +			num-cs = <1>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		spi3: spi@4028000 {
> +			compatible = "allwinner,sun50i-r329-spi";
> +			reg = <0x4028000 0x1000>;
> +			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
> +			clock-names = "ahb", "mod";
> +			resets = <&ccu RST_BUS_SPI3>;
> +			dmas = <&dma 25>, <&dma 25>;
> +			dma-names = "rx", "tx";
> +			num-cs = <1>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		usb_otg: usb@4100000 {
> +			compatible = "allwinner,sun8i-a33-musb";
> +			reg = <0x4100000 0x400>;
> +			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "mc";
> +			clocks = <&ccu CLK_BUS_OTG>;
> +			resets = <&ccu RST_BUS_OTG>;
> +			extcon = <&usbphy 0>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		usbphy: phy@4100400 {
> +			compatible = "allwinner,sun8i-v853-usb-phy";
> +			reg = <0x4100400 0x100>,
> +			      <0x4101800 0x100>;
> +			reg-names = "phy_ctrl",
> +				    "pmu0";
> +			clocks = <&ccu CLK_USB_OHCI>;
> +			clock-names = "usb0_phy";
> +			resets = <&ccu RST_USB_PHY>;
> +			reset-names = "usb0_reset";
> +			status = "disabled";
> +			#phy-cells = <1>;
> +		};
> +
> +		ehci0: usb@4101000 {
> +			compatible = "generic-ehci";
> +			reg = <0x4101000 0x100>;
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI>,
> +				 <&ccu CLK_BUS_EHCI>,
> +				 <&ccu CLK_USB_OHCI>;
> +			resets = <&ccu RST_BUS_OHCI>,
> +				 <&ccu RST_BUS_EHCI>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ohci0: usb@4101400 {
> +			compatible = "generic-ohci";
> +			reg = <0x4101400 0x100>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI>,
> +				 <&ccu CLK_USB_OHCI>;
> +			resets = <&ccu RST_BUS_OHCI>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ppu: power-controller@7001000 {
> +			compatible = "allwinner,sun8i-v853-ppu";
> +			reg = <0x7001000 0x400>;
> +			clocks = <&r_ccu CLK_BUS_R_PPU>;
> +			resets = <&r_ccu RST_BUS_R_PPU>;
> +			#power-domain-cells = <1>;
> +		};
> +
> +		r_ccu: clock-controller@7010000 {
> +			compatible = "allwinner,sun8i-v853-r-ccu";
> +			reg = <0x7010000 0x230>;
> +			clocks = <&dcxo>,
> +				 <&rtc CLK_IOSC>,
> +				 <&rtc CLK_OSC32K>,
> +				 <&ccu CLK_PLL_PERIPH_200M>,
> +				 <&ccu CLK_PLL_AUDIO_4X>;
> +			clock-names = "hosc",
> +				      "iosc",
> +				      "losc",
> +				      "pll-periph",
> +				      "pll-audio";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		nmi_intc: intc-nmi@7010320 {
> +			compatible = "allwinner,sun9i-a80-nmi";
> +			interrupt-parent = <&gic>;
> +			#interrupt-cells = <2>;
> +			#address-cells = <0>;
> +			interrupt-controller;
> +			reg = <0x07010320 0xc>;
> +			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		rtc: rtc@7090000 {
> +			compatible = "allwinner,sun50i-r329-rtc";
> +			reg = <0x7090000 0x400>;
> +			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&r_ccu CLK_BUS_R_RTC>;
> +			clock-names = "bus";
> +			resets = <&r_ccu RST_BUS_R_RTC>;
> +			wakeup-source;
> +			#clock-cells = <1>;
> +		};

Verified that all MMIO base addresses, DMA channels and interrupts are
matching the manual.

Cheers,
Andre

> +	};
> +};

Re: [PATCH v2 03/10] dt-bindings: clock: sunxi-ng: add compatibles for V853

[Rob Herring]

On Wed, Feb 05, 2025 at 01:52:18PM +0100, Andras Szemzo wrote:
> V853 has 2 CCUs, add compatible strings for it.
> 
> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
> ---
>  .../clock/allwinner,sun4i-a10-ccu.yaml        |   3 +
>  .../clock/allwinner,sun8i-v853-ccu.h          | 132 ++++++++++++++++++
>  .../clock/allwinner,sun8i-v853-r-ccu.h        |  16 +++
>  .../reset/allwinner,sun8i-v853-ccu.h          |  60 ++++++++
>  .../reset/allwinner,sun8i-v853-r-ccu.h        |  14 ++
>  5 files changed, 225 insertions(+)
>  create mode 100644 include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h
>  create mode 100644 include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h
>  create mode 100644 include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h
>  create mode 100644 include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
> index 1690b9d99c3d..9369d62284ed 100644
> --- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
> +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
> @@ -33,6 +33,8 @@ properties:
>        - allwinner,sun8i-r40-ccu
>        - allwinner,sun8i-v3-ccu
>        - allwinner,sun8i-v3s-ccu
> +      - allwinner,sun8i-v853-ccu
> +      - allwinner,sun8i-v853-r-ccu

Please explain the difference between these in the commit message.

>        - allwinner,sun9i-a80-ccu
>        - allwinner,sun20i-d1-ccu
>        - allwinner,sun20i-d1-r-ccu
> @@ -103,6 +105,7 @@ else:
>        compatible:
>          enum:
>            - allwinner,sun20i-d1-ccu
> +          - allwinner,sun8i-v853-ccu
>            - allwinner,sun50i-a100-ccu
>            - allwinner,sun50i-h6-ccu
>            - allwinner,sun50i-h616-ccu
> diff --git a/include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h b/include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h
> new file mode 100644
> index 000000000000..cf56c168e1cd
> --- /dev/null
> +++ b/include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h
> @@ -0,0 +1,132 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

Dual license.

> +/*
> + * Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_ALLWINNER_SUN8I_V85X_CCU_H_
> +#define _DT_BINDINGS_CLK_ALLWINNER_SUN8I_V85X_CCU_H_
> +
> +#define CLK_OSC12M		0
> +#define CLK_PLL_CPU		1
> +#define CLK_PLL_DDR		2
> +#define CLK_PLL_PERIPH_4X	3
> +#define CLK_PLL_PERIPH_2X	4
> +#define CLK_PLL_PERIPH_800M	5
> +#define CLK_PLL_PERIPH_480M	6
> +#define CLK_PLL_PERIPH_600M	7
> +#define CLK_PLL_PERIPH_400M	8
> +#define CLK_PLL_PERIPH_300M	9
> +#define CLK_PLL_PERIPH_200M	10
> +#define CLK_PLL_PERIPH_160M	11
> +#define CLK_PLL_PERIPH_150M	12
> +#define CLK_PLL_VIDEO_4X	13
> +#define CLK_PLL_VIDEO_2X	14
> +#define CLK_PLL_VIDEO_1X	15
> +#define CLK_PLL_CSI_4X		16
> +#define CLK_PLL_AUDIO_DIV2	17
> +#define CLK_PLL_AUDIO_DIV5	18
> +#define CLK_PLL_AUDIO_4X	19
> +#define CLK_PLL_AUDIO_1X	20
> +#define CLK_PLL_NPU_4X		21
> +#define CLK_CPU			22
> +#define CLK_CPU_AXI		23
> +#define CLK_CPU_APB		24
> +#define CLK_AHB			25
> +#define CLK_APB0		26
> +#define CLK_APB1		27
> +#define CLK_MBUS		28
> +#define CLK_DE			29
> +#define CLK_BUS_DE		30
> +#define CLK_G2D			31
> +#define CLK_BUS_G2D		32
> +#define CLK_CE			33
> +#define CLK_BUS_CE		34
> +#define CLK_VE			35
> +#define CLK_BUS_VE		36
> +#define CLK_NPU			37
> +#define CLK_BUS_NPU		38
> +#define CLK_BUS_DMA		39
> +#define CLK_BUS_MSGBOX0		40
> +#define CLK_BUS_MSGBOX1		41
> +#define CLK_BUS_SPINLOCK	42
> +#define CLK_BUS_HSTIMER		43
> +#define CLK_AVS			44
> +#define CLK_BUS_DBG		45
> +#define CLK_BUS_PWM		46
> +#define CLK_BUS_IOMMU		47
> +#define CLK_DRAM		48
> +#define CLK_MBUS_DMA		49
> +#define CLK_MBUS_VE		50
> +#define CLK_MBUS_CE		51
> +#define CLK_MBUS_CSI		52
> +#define CLK_MBUS_ISP		53
> +#define CLK_MBUS_G2D		54
> +#define CLK_BUS_DRAM		55
> +#define CLK_MMC0		56
> +#define CLK_MMC1		57
> +#define CLK_MMC2		58
> +#define CLK_BUS_MMC0		59
> +#define CLK_BUS_MMC1		60
> +#define CLK_BUS_MMC2		61
> +#define CLK_BUS_UART0		62
> +#define CLK_BUS_UART1		63
> +#define CLK_BUS_UART2		64
> +#define CLK_BUS_UART3		65
> +#define CLK_BUS_I2C0		66
> +#define CLK_BUS_I2C1		67
> +#define CLK_BUS_I2C2		68
> +#define CLK_BUS_I2C3		69
> +#define CLK_BUS_I2C4		70
> +#define CLK_SPI0		71
> +#define CLK_SPI1		72
> +#define CLK_SPI2		73
> +#define CLK_SPI3		74
> +#define CLK_BUS_SPI0		75
> +#define CLK_BUS_SPI1		76
> +#define CLK_BUS_SPI2		77
> +#define CLK_BUS_SPI3		78
> +#define CLK_SPIF		79
> +#define CLK_BUS_SPIF		80
> +#define CLK_EMAC_25M		81
> +#define CLK_BUS_EMAC		82
> +#define CLK_BUS_GPADC		83
> +#define CLK_BUS_THS		84
> +#define CLK_I2S0		85
> +#define CLK_I2S1		86
> +#define CLK_BUS_I2S0		87
> +#define CLK_BUS_I2S1		88
> +#define CLK_DMIC		89
> +#define CLK_BUS_DMIC		90
> +#define CLK_AUDIO_CODEC_DAC	91
> +#define CLK_AUDIO_CODEC_ADC	92
> +#define CLK_BUS_AUDIO_CODEC	93
> +#define CLK_USB_OHCI		94
> +#define CLK_BUS_OHCI		95
> +#define CLK_BUS_EHCI		96
> +#define CLK_BUS_OTG		97
> +#define CLK_BUS_DPSS_TOP	98
> +#define CLK_MIPI_DSI		99
> +#define CLK_BUS_MIPI_DSI	100
> +#define CLK_TCON_LCD		101
> +#define CLK_BUS_TCON_LCD	102
> +#define CLK_CSI_TOP		103
> +#define CLK_CSI_MCLK0		104
> +#define CLK_CSI_MCLK1		105
> +#define CLK_CSI_MCLK2		106
> +#define CLK_BUS_CSI		107
> +#define CLK_BUS_WIEGAND		108
> +#define CLK_RISCV		109
> +#define CLK_RISCV_AXI		110
> +#define CLK_RISCV_CORE_GATE	111
> +#define CLK_RISCV_CFG_GATE	112
> +#define CLK_FANOUT_24M		113
> +#define CLK_FANOUT_12M		114
> +#define CLK_FANOUT_16M		115
> +#define CLK_FANOUT_25M		116
> +#define CLK_FANOUT_27M		117
> +#define CLK_FANOUT_PCLK		118
> +#define CLK_FANOUT0		119
> +#define CLK_FANOUT1		120
> +#define CLK_FANOUT2		121
> +
> +#endif
> diff --git a/include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h b/include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h
> new file mode 100644
> index 000000000000..48fe598b7bd8
> --- /dev/null
> +++ b/include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_ALLWINNER_SUN8I_V853_R_CCU_H_
> +#define _DT_BINDINGS_CLK_ALLWINNER_SUN8I_V853_R_CCU_H_
> +
> +#define CLK_R_AHB		0
> +#define CLK_R_APB0		1
> +#define CLK_BUS_R_TWD		2
> +#define CLK_BUS_R_PPU		3
> +#define CLK_BUS_R_RTC		4
> +#define CLK_BUS_R_CPUCFG	5
> +
> +#endif
> diff --git a/include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h b/include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h
> new file mode 100644
> index 000000000000..e258117518aa
> --- /dev/null
> +++ b/include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h
> @@ -0,0 +1,60 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com>
> + */
> +
> +#ifndef _DT_BINDINGS_RST_ALLWINNER_SUN8I_V85X_CCU_H_
> +#define _DT_BINDINGS_RST_ALLWINNER_SUN8I_V85X_CCU_H_
> +
> +#define RST_MBUS		0
> +#define RST_BUS_DE		1
> +#define RST_BUS_G2D		2
> +#define RST_BUS_CE		3
> +#define RST_BUS_VE		4
> +#define RST_BUS_NPU		5
> +#define RST_BUS_DMA		6
> +#define RST_BUS_MSGBOX0		7
> +#define RST_BUS_MSGBOX1		8
> +#define RST_BUS_SPINLOCK	9
> +#define RST_BUS_HSTIMER		10
> +#define RST_BUS_DBG		11
> +#define RST_BUS_PWM		12
> +#define RST_BUS_DRAM		13
> +#define RST_BUS_MMC0		14
> +#define RST_BUS_MMC1		15
> +#define RST_BUS_MMC2		16
> +#define RST_BUS_UART0		17
> +#define RST_BUS_UART1		18
> +#define RST_BUS_UART2		19
> +#define RST_BUS_UART3		20
> +#define RST_BUS_I2C0		21
> +#define RST_BUS_I2C1		22
> +#define RST_BUS_I2C2		23
> +#define RST_BUS_I2C3		24
> +#define RST_BUS_I2C4		25
> +#define RST_BUS_SPI0		26
> +#define RST_BUS_SPI1		27
> +#define RST_BUS_SPI2		28
> +#define RST_BUS_SPI3		29
> +#define RST_BUS_SPIF		30
> +#define RST_BUS_EMAC		31
> +#define RST_BUS_GPADC		32
> +#define RST_BUS_THS		33
> +#define RST_BUS_I2S0		34
> +#define RST_BUS_I2S1		35
> +#define RST_BUS_DMIC		36
> +#define RST_BUS_AUDIO_CODEC	37
> +#define RST_USB_PHY		38
> +#define RST_BUS_OHCI		39
> +#define RST_BUS_EHCI		40
> +#define RST_BUS_OTG		41
> +#define RST_BUS_DPSS_TOP	42
> +#define RST_BUS_MIPI_DSI	43
> +#define RST_BUS_TCON_LCD	44
> +#define RST_BUS_CSI		45
> +#define RST_BUS_WIEGAND		46
> +#define RST_RISCV_SYS_APB	47
> +#define RST_RISCV_SOFT		48
> +#define RST_RISCV_CFG		49
> +
> +#endif
> diff --git a/include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h b/include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h
> new file mode 100644
> index 000000000000..57629d635115
> --- /dev/null
> +++ b/include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
> + */
> +
> +#ifndef _DT_BINDINGS_RST_ALLWINNER_SUN8I_V853_R_CCU_H_
> +#define _DT_BINDINGS_RST_ALLWINNER_SUN8I_V853_R_CCU_H_
> +
> +#define RST_BUS_R_TWD		0
> +#define RST_BUS_R_PPU		1
> +#define RST_BUS_R_RTC		2
> +#define RST_BUS_R_CPUCFG	3
> +
> +#endif
> -- 
> 2.39.5
> 

Re: [PATCH v2 05/10] dt-bindings: power: add V853 ppu bindings

[Rob Herring (Arm)]

On Wed, 05 Feb 2025 13:52:20 +0100, Andras Szemzo wrote:
> Document V853 PPU compatible.
> 
> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
> ---
>  .../bindings/power/allwinner,sun20i-d1-ppu.yaml        |  1 +
>  include/dt-bindings/power/allwinner,sun8i-v853-ppu.h   | 10 ++++++++++
>  2 files changed, 11 insertions(+)
>  create mode 100644 include/dt-bindings/power/allwinner,sun8i-v853-ppu.h
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v2 07/10] dt-bindings: phy: allwinner: add v853 usb phy

[Rob Herring]

On Wed, Feb 05, 2025 at 01:52:22PM +0100, Andras Szemzo wrote:
> Document Allwinner v853 USB phy.
> 
> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
> ---
>  .../devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml   | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
> index 21209126ed00..815742c4f5fb 100644
> --- a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
> @@ -19,9 +19,11 @@ properties:
>        - enum:
>            - allwinner,sun20i-d1-usb-phy
>            - allwinner,sun50i-a64-usb-phy
> +          - allwinner,sun8i-v853-usb-phy
>        - items:
>            - const: allwinner,sun50i-a100-usb-phy
>            - const: allwinner,sun20i-d1-usb-phy
> +          - const: allwinner,sun8i-v853-usb-phy

You just changed existing users. 

>  
>    reg:
>      items:
> -- 
> 2.39.5
> 

Re: [PATCH v2 09/10] ARM: dts: sun8i: add DTSI file for V853

[Rob Herring]

On Thu, Feb 06, 2025 at 04:19:58PM +0000, Andre Przywara wrote:
> On Wed,  5 Feb 2025 13:52:24 +0100
> Andras Szemzo <szemzo.andras@gmail.com> wrote:
> 
> Hi,
> 
> > V853/V851 is a new SoC by Allwinner. Add a basic dtsi file for it.
> > 
> > Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
> > ---
> >  arch/arm/boot/dts/allwinner/sun8i-v853.dtsi | 656 ++++++++++++++++++++
> >  1 file changed, 656 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
> > 
> > diff --git a/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
> > new file mode 100644
> > index 000000000000..8b82b8783127
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
> > @@ -0,0 +1,656 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
> > +// Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com>
> > +
> > +#include <dt-bindings/clock/sun6i-rtc.h>
> > +#include <dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h>
> > +#include <dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h>
> > +#include <dt-bindings/clock/allwinner,sun8i-v853-ccu.h>
> > +#include <dt-bindings/reset/allwinner,sun8i-v853-ccu.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/power/allwinner,sun8i-v853-ppu.h>
> > +
> > +/ {
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +
> > +	dcxo: dcxo-clk {
> 
> What's people's opinion about the node name? Traditionally we call this
> "osc24M", in all the other SoCs except D1 and A100. So is this the new
> black?

That's documented (but not enforced) in fixed-clock.yaml now. It's 
"clock-<freq-in-hz>".

Rob

Re: [PATCH v2 09/10] ARM: dts: sun8i: add DTSI file for V853

[András Szemző]

Hi,

Thanks for your review!

> On 6 Feb 2025, at 17:19, Andre Przywara <andre.przywara@arm.com> wrote:
> 
> On Wed,  5 Feb 2025 13:52:24 +0100
> Andras Szemzo <szemzo.andras@gmail.com> wrote:
> 
> Hi,
> 
>> V853/V851 is a new SoC by Allwinner. Add a basic dtsi file for it.
>> 
>> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
>> ---
>> arch/arm/boot/dts/allwinner/sun8i-v853.dtsi | 656 ++++++++++++++++++++
>> 1 file changed, 656 insertions(+)
>> create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
>> 
>> diff --git a/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
>> new file mode 100644
>> index 000000000000..8b82b8783127
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
>> @@ -0,0 +1,656 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
>> +// Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com>
>> +
>> +#include <dt-bindings/clock/sun6i-rtc.h>
>> +#include <dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h>
>> +#include <dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h>
>> +#include <dt-bindings/clock/allwinner,sun8i-v853-ccu.h>
>> +#include <dt-bindings/reset/allwinner,sun8i-v853-ccu.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/power/allwinner,sun8i-v853-ppu.h>
>> +
>> +/ {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + dcxo: dcxo-clk {
> 
> What's people's opinion about the node name? Traditionally we call this
> "osc24M", in all the other SoCs except D1 and A100. So is this the new
> black?
> 

I renamed it because node names can’t contain capital letters, and D1/A100 already use
dcxo.

>> + compatible = "fixed-clock";
>> + clock-output-names = "osc24M";
>> + #clock-cells = <0>;
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7","arm,armv7";
>> + reg = <0>;
>> + clocks = <&ccu CLK_CPU>;
>> + clock-names = "cpu";
>> + clock-frequency = <912000000>;
>> + clock-latency = <200000>;
>> + cooling-min-level = <5>;
>> + cooling-max-level = <0>;
>> + #cooling-cells = <2>; /* min followed by max */
>> + dynamic-power-coefficient = <142>;
>> + };
>> + };
>> +
>> + pmu {
>> + compatible = "arm,cortex-a7-pmu";
>> + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-parent = <&gic>;
> 
> Please move interrupt-parent to the root node, as the first property. Then
> you can lose it here, and in the timer and soc node.
> 

ok.

>> + };
>> +
>> + timer {
>> + compatible = "arm,armv7-timer";
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
>> +     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
>> +     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
>> +     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
>> + clock-frequency = <24000000>;
> 
> Please remove this, and let the firmware set CNTFRQ. U-Boot does this
> automatically (in nonsec_virt.S), and it should be just a few lines to add
> to awboot's arch/arm32/arch_timer.c.
> 

I actually already did that.

> Or, even better: provide proper U-Boot support ;-)
> 
>> + interrupt-parent = <&gic>;
>> + arm,cpu-registers-not-fw-configured;
> 
> Same here, please fix your firmware to configure the non-secure world
> correctly, and remove this property.
> I am happy to help you with that.
> 

ok and thanks.

>> + arm,no-tick-in-suspend;
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + ranges;
>> + interrupt-parent = <&gic>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + dma-noncoherent;
>> +
>> + pio: pinctrl@2000000 {
>> + compatible = "allwinner,sun8i-v853-pinctrl";
>> + reg = <0x2000000 0x800>;
>> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_APB0>, <&dcxo>, <&rtc CLK_OSC32K>;
>> + clock-names = "apb", "hosc", "losc";
>> + gpio-controller;
>> + interrupt-controller;
>> + #gpio-cells = <3>;
>> + #interrupt-cells = <3>;
>> +
>> + /omit-if-no-ref/
> 
> You don't need omit-if-no-ref for *all* nodes, just the more obscure ones,
> which are only used by one or two boards.
> Here I'd say, just have it for: uart2, dsi, spi3, i2c3, and remove that
> tag for the others.
> 

ok

>> + uart0_ph9_pins: uart0-ph9-pins {
>> + pins = "PH9", "PH10";
>> + function = "uart0";
>> + allwinner,pinmux = <5>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + uart2_pe12_pins: uart2-pe12-pins {
>> + pins = "PE12", "PE13";
>> + function = "uart2";
>> + allwinner,pinmux = <6>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + dsi_2lane_pins: dsi-2lane-pins {
>> + pins = "PD1", "PD2", "PD3", "PD4", "PD5", "PD6";
>> + function = "dsi";
>> + allwinner,pinmux = <5>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + spi0_pins: spi0-pins {
>> + pins = "PC0", "PC1", "PC2", "PC3", "PC4", "PC5";
>> + function = "spi0";
>> + allwinner,pinmux = <4>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + spi3_pins: spi3-pins {
>> + pins = "PH11", "PH12", "PH13", "PH14";
>> + function = "spi3";
>> + allwinner,pinmux = <6>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + i2c2_ph11_pins: i2c2-ph11-pins {
>> + pins = "PH11", "PH12";
>> + function = "i2c2";
>> + allwinner,pinmux = <5>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + i2c3_ph13_pins: i2c3-ph13-pins {
>> + pins = "PH13", "PH14";
>> + function = "i2c3";
>> + allwinner,pinmux = <5>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + mmc0_pins: mmc0-pins {
>> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
>> + function = "sdc0";
>> + allwinner,pinmux = <2>;
>> + drive-strength = <30>;
>> + bias-pull-up;
>> + };
>> +
>> + /omit-if-no-ref/
>> + mmc1_pins: mmc1-pins {
>> + pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5";
>> + function = "sdc1";
>> + allwinner,pinmux = <6>;
>> + drive-strength = <30>;
>> + bias-pull-up;
>> + };
>> +
>> + /omit-if-no-ref/
>> + rmii_pe_pins: rmii-pe-pins {
>> + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
>> +       "PE5", "PE6", "PE7", "PE8", "PE9";
>> + function = "emac";
>> + allwinner,pinmux = <3>;
>> + };
>> + };
>> +
>> + ccu: clock-controller@2001000 {
>> + compatible = "allwinner,sun8i-v853-ccu";
>> + reg = <0x2001000 0x1000>;
>> + clocks = <&dcxo>,
>> + <&rtc CLK_IOSC>,
>> + <&rtc CLK_OSC32K>;
>> + clock-names = "hosc", "iosc", "losc";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + gpadc: adc@2009000 {
>> + compatible = "allwinner,sun20i-d1-gpadc";
> 
> Please use a fallback notation:
> compatible = "allwinner,sun8i-v853-gpadc",
>     "allwinner,sun20i-d1-gpadc";
> 
> This allows to later add quirks should we need some for this SoC. 
> And this requires a binding patch.
> 

ok for all the compatibles below.

>> + reg = <0x2009000 0x0400>;
>> + clocks = <&ccu CLK_BUS_GPADC>;
>> + resets = <&ccu RST_BUS_GPADC>;
>> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #io-channel-cells = <1>;
>> + };
>> +
>> + i2s0: i2s@2032000 {
>> + compatible = "allwinner,sun50i-r329-i2s";
> 
> Same here, fallback compatible.
> 
>> + reg = <0x2032000 0x1000>;
>> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2S0>,
>> + <&ccu CLK_I2S0>;
>> + clock-names = "apb", "mod";
>> + resets = <&ccu RST_BUS_I2S0>;
>> + dmas = <&dma 3>, <&dma 3>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #sound-dai-cells = <0>;
>> + };
>> +
>> + i2s1: i2s@2033000 {
>> + compatible = "allwinner,sun50i-r329-i2s";
>> + reg = <0x2033000 0x1000>;
>> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2S1>,
>> + <&ccu CLK_I2S1>;
>> + clock-names = "apb", "mod";
>> + resets = <&ccu RST_BUS_I2S1>;
>> + dmas = <&dma 4>, <&dma 4>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #sound-dai-cells = <0>;
>> + };
>> +
>> + timer: timer@2050000 {
>> + compatible = "allwinner,sun20i-d1-timer",
> 
> This should be allwinner,sun8i-v853-timer.
> 
>> +     "allwinner,sun8i-a23-timer";
>> + reg = <0x2050000 0xa0>;
>> + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&dcxo>;
>> + };
>> +
>> + wdt: watchdog@20500a0 {
>> + compatible = "allwinner,sun20i-d1-wdt-reset",
>> +     "allwinner,sun20i-d1-wdt";
> 
> Same here, use a more specific compatible, then the sun20i as a fallback.
> 
>> + reg = <0x20500a0 0x20>;
>> + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&dcxo>, <&rtc CLK_OSC32K>;
>> + clock-names = "hosc", "losc";
>> + status = "reserved";
>> + };
>> +
>> + uart0: serial@2500000 {
>> + compatible = "snps,dw-apb-uart";
> 
> The UART is an exception, it's just the generic Synopsis name, so this is
> fine.
> 
>> + reg = <0x2500000 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART0>;
>> + resets = <&ccu RST_BUS_UART0>;
>> + dmas = <&dma 14>, <&dma 14>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@2500400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x2500400 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART1>;
>> + resets = <&ccu RST_BUS_UART1>;
>> + dmas = <&dma 15>, <&dma 15>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@2500800 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x2500800 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART2>;
>> + resets = <&ccu RST_BUS_UART2>;
>> + dmas = <&dma 16>, <&dma 16>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial@2500c00 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x2500c00 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART3>;
>> + resets = <&ccu RST_BUS_UART3>;
>> + dmas = <&dma 17>, <&dma 17>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + i2c0: i2c@2502000 {
>> + compatible = "allwinner,sun8i-v536-i2c",
>> +     "allwinner,sun6i-a31-i2c";
> 
> This needs three compatible strings:
> compatible = "allwinner,sun8i-v853-i2c",
>     "allwinner,sun8i-v536-i2c",
>     "allwinner,sun6i-a31-i2c";
> 
>> + reg = <0x2502000 0x400>;
>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C0>;
>> + resets = <&ccu RST_BUS_I2C0>;
>> + dmas = <&dma 43>, <&dma 43>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c1: i2c@2502400 {
>> + compatible = "allwinner,sun8i-v536-i2c",
>> +     "allwinner,sun6i-a31-i2c";
>> + reg = <0x2502400 0x400>;
>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C1>;
>> + resets = <&ccu RST_BUS_I2C1>;
>> + dmas = <&dma 44>, <&dma 44>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c2: i2c@2502800 {
>> + compatible = "allwinner,sun8i-v536-i2c",
>> +     "allwinner,sun6i-a31-i2c";
>> + reg = <0x2502800 0x400>;
>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C2>;
>> + resets = <&ccu RST_BUS_I2C2>;
>> + dmas = <&dma 45>, <&dma 45>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c3: i2c@2502c00 {
>> + compatible = "allwinner,sun8i-v536-i2c",
>> +     "allwinner,sun6i-a31-i2c";
>> + reg = <0x2502c00 0x400>;
>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C3>;
>> + resets = <&ccu RST_BUS_I2C3>;
>> + dmas = <&dma 46>, <&dma 46>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c4: i2c@2503000 {
>> + compatible = "allwinner,sun8i-v536-i2c",
>> +     "allwinner,sun6i-a31-i2c";
>> + reg = <0x2503000 0x400>;
>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C4>;
>> + resets = <&ccu RST_BUS_I2C4>;
>> + dmas = <&dma 47>, <&dma 47>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + syscon: syscon@3000000 {
>> + compatible = "allwinner,sun8i-h3-system-control";
> 
> I think you got the idea by now, fallbacks ... and for the others below as
> well.
> 
>> + reg = <0x3000000 0x1000>;
>> + ranges;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + sram_c: sram@20000 {
>> + compatible = "mmio-sram";
>> + reg = <0x00020000 0x21000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x00020000 0x21000>;
>> +
>> + ve_sram: sram-section@0 {
>> +    compatible = "allwinner,sun8i-v3s-sram-c", 
>> + "allwinner,sun4i-a10-sram-c1";
>> +    reg = <0x000000 0x21000>;
>> + };
>> + };
>> + };
>> +
>> + dma: dma-controller@3002000 {
>> + compatible = "allwinner,sun20i-d1-dma";
>> + reg = <0x3002000 0x1000>;
>> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
>> + clock-names = "bus", "mbus";
>> + resets = <&ccu RST_BUS_DMA>;
>> + dma-channels = <16>;
>> + dma-requests = <48>;
>> + #dma-cells = <1>;
>> + };
>> +
>> + hwspinlock: hwlock@3005000 {
>> +    compatible = "allwinner,sun6i-a31-hwspinlock";
>> + reg = <0x3005000 0x1000>;
>> + clocks = <&ccu CLK_BUS_SPINLOCK>;
>> + clock-names = "ahb";
>> + resets = <&ccu RST_BUS_SPINLOCK>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + sid: efuse@3006000 {
>> + compatible = "allwinner,sun20i-d1-sid";
>> + reg = <0x3006000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + ths_calib: ths-calib@14 {
>> + reg = <0x14 0x8>;
>> + };
>> + };
>> +
>> + hstimer@3008000 {
>> + compatible = "allwinner,sun7i-a20-hstimer";
>> + reg = <0x03008000 0x1000>;
>> + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_HSTIMER>;
>> + };
>> +
>> + gic: interrupt-controller@3021000 {
>> + compatible = "arm,gic-400";
> 
> (no fallbacks needed here, it's an actual GIC-400)
> 
>> + reg = <0x03021000 0x1000>, /* GIC Dist */
>> +      <0x03022000 0x2000>, /* GIC CPU */
>> +      <0x03024000 0x2000>, /* GIC VCPU Control */
>> +      <0x03026000 0x2000>; /* GIC VCPU */
>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + };
>> +
>> + mbus: dram-controller@3102000 {
>> + compatible = "allwinner,sun20i-d1-mbus";
>> + reg = <0x3102000 0x1000>,
>> +      <0x3103000 0x1000>;
>> + reg-names = "mbus", "dram";
>> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_MBUS>,
>> + <&ccu CLK_DRAM>,
>> + <&ccu CLK_BUS_DRAM>;
>> + clock-names = "mbus", "dram", "bus";
>> + dma-ranges = <0 0x40000000 0x80000000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interconnect-cells = <1>;
>> + };
>> +
>> + mmc0: mmc@4020000 {
>> + compatible = "allwinner,sun20i-d1-mmc";
>> + reg = <0x4020000 0x1000>;
>> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ccu RST_BUS_MMC0>;
>> + reset-names = "ahb";
>> + no-sdio;
>> + no-mmc;
> 
> I don't think we use those two properties in mainline?
> 

yes, it’s remained from the BSP, I’ll remove.

>> + cap-sd-highspeed;
>> + max-frequency = <150000000>;
>> + mmc-ddr-1_8v;
> 
> This looks wrong here, definitely you should not have voltage dependent
> properties in the SoC .dtsi.
> 
> And you can add the pinctrl properties already here, since there is only
> one set of pins for MMC0.
> 

ok

>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc1: mmc@4021000 {
>> + compatible = "allwinner,sun20i-d1-mmc";
>> + reg = <0x4021000 0x1000>;
>> + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ccu RST_BUS_MMC1>;
>> + reset-names = "ahb";
>> + cap-sd-highspeed;
>> + cap-mmc-highspeed;
>> + max-frequency = <150000000>;
>> + mmc-ddr-1_8v;
> 
> same here, please remove.
> 
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc2: mmc@4022000 {
>> + compatible = "allwinner,sun20i-d1-mmc";
>> + reg = <0x4022000 0x1000>;
>> + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ccu RST_BUS_MMC2>;
>> + reset-names = "ahb";
>> + no-sdio;
>> + no-sd;
>> + cap-mmc-highspeed;
>> + max-frequency = <150000000>;
>> + mmc-ddr-1_8v;
>> + mmc-ddr-3_3v;
> 
> Please leave that to the board DTs to set, they know which voltage PortC is
> running on.
> 
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + spi0: spi@4025000 {
>> + compatible = "allwinner,sun50i-r329-spi";
>> + reg = <0x4025000 0x1000>;
>> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
>> + clock-names = "ahb", "mod";
>> + resets = <&ccu RST_BUS_SPI0>;
>> + dmas = <&dma 22>, <&dma 22>;
>> + dma-names = "rx", "tx";
>> + num-cs = <1>;
> 
> Is that so? I see SPI0_CS0, SPI0_CS1, SPI1_CS0, SPI1_CS1 pins.
> 

Sure, I implemented it from v851s datasheet, where there is no xCS1.

>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + spi1: spi@4026000 {
>> + compatible = "allwinner,sun50i-r329-spi-dbi",
>> +     "allwinner,sun50i-r329-spi";
>> + reg = <0x4026000 0x1000>;
>> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
>> + clock-names = "ahb", "mod";
>> + resets = <&ccu RST_BUS_SPI1>;
>> + dmas = <&dma 23>, <&dma 23>;
>> + dma-names = "rx", "tx";
>> + num-cs = <1>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + spi2: spi@4027000 {
>> + compatible = "allwinner,sun50i-r329-spi";
>> + reg = <0x4027000 0x1000>;
>> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
>> + clock-names = "ahb", "mod";
>> + resets = <&ccu RST_BUS_SPI2>;
>> + dmas = <&dma 24>, <&dma 24>;
>> + dma-names = "rx", "tx";
>> + num-cs = <1>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + spi3: spi@4028000 {
>> + compatible = "allwinner,sun50i-r329-spi";
>> + reg = <0x4028000 0x1000>;
>> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
>> + clock-names = "ahb", "mod";
>> + resets = <&ccu RST_BUS_SPI3>;
>> + dmas = <&dma 25>, <&dma 25>;
>> + dma-names = "rx", "tx";
>> + num-cs = <1>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + usb_otg: usb@4100000 {
>> + compatible = "allwinner,sun8i-a33-musb";
>> + reg = <0x4100000 0x400>;
>> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "mc";
>> + clocks = <&ccu CLK_BUS_OTG>;
>> + resets = <&ccu RST_BUS_OTG>;
>> + extcon = <&usbphy 0>;
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + usbphy: phy@4100400 {
>> + compatible = "allwinner,sun8i-v853-usb-phy";
>> + reg = <0x4100400 0x100>,
>> +      <0x4101800 0x100>;
>> + reg-names = "phy_ctrl",
>> +    "pmu0";
>> + clocks = <&ccu CLK_USB_OHCI>;
>> + clock-names = "usb0_phy";
>> + resets = <&ccu RST_USB_PHY>;
>> + reset-names = "usb0_reset";
>> + status = "disabled";
>> + #phy-cells = <1>;
>> + };
>> +
>> + ehci0: usb@4101000 {
>> + compatible = "generic-ehci";
>> + reg = <0x4101000 0x100>;
>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_OHCI>,
>> + <&ccu CLK_BUS_EHCI>,
>> + <&ccu CLK_USB_OHCI>;
>> + resets = <&ccu RST_BUS_OHCI>,
>> + <&ccu RST_BUS_EHCI>;
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ohci0: usb@4101400 {
>> + compatible = "generic-ohci";
>> + reg = <0x4101400 0x100>;
>> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_OHCI>,
>> + <&ccu CLK_USB_OHCI>;
>> + resets = <&ccu RST_BUS_OHCI>;
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ppu: power-controller@7001000 {
>> + compatible = "allwinner,sun8i-v853-ppu";
>> + reg = <0x7001000 0x400>;
>> + clocks = <&r_ccu CLK_BUS_R_PPU>;
>> + resets = <&r_ccu RST_BUS_R_PPU>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> + r_ccu: clock-controller@7010000 {
>> + compatible = "allwinner,sun8i-v853-r-ccu";
>> + reg = <0x7010000 0x230>;
>> + clocks = <&dcxo>,
>> + <&rtc CLK_IOSC>,
>> + <&rtc CLK_OSC32K>,
>> + <&ccu CLK_PLL_PERIPH_200M>,
>> + <&ccu CLK_PLL_AUDIO_4X>;
>> + clock-names = "hosc",
>> +      "iosc",
>> +      "losc",
>> +      "pll-periph",
>> +      "pll-audio";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + nmi_intc: intc-nmi@7010320 {
>> + compatible = "allwinner,sun9i-a80-nmi";
>> + interrupt-parent = <&gic>;
> 
> not needed
> 

ok

>> + #interrupt-cells = <2>;
>> + #address-cells = <0>;
>> + interrupt-controller;
>> + reg = <0x07010320 0xc>;
>> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
> 
> reg and interrupts typically come right after compatible
> 

ok

> That's it for now, I will check all the numbers against the manual later,
> and verify the clock names and such.
> 
> Cheers,
> Andre
> 
>> + };
>> +
>> + rtc: rtc@7090000 {
>> + compatible = "allwinner,sun50i-r329-rtc";
>> + reg = <0x7090000 0x400>;
>> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&r_ccu CLK_BUS_R_RTC>;
>> + clock-names = "bus";
>> + resets = <&r_ccu RST_BUS_R_RTC>;
>> + wakeup-source;
>> + #clock-cells = <1>;
>> + };
>> + };
>> +};
> 

Re: [PATCH v2 09/10] ARM: dts: sun8i: add DTSI file for V853

[András Szemző]

> On 7 Feb 2025, at 02:02, Andre Przywara <andre.przywara@arm.com> wrote:
> 
> On Wed,  5 Feb 2025 13:52:24 +0100
> Andras Szemzo <szemzo.andras@gmail.com> wrote:
> 
> Hi,
> 
> those comments go on top of those in my previous reply:
> 
>> V853/V851 is a new SoC by Allwinner. Add a basic dtsi file for it.
>> 
>> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
>> ---
>> arch/arm/boot/dts/allwinner/sun8i-v853.dtsi | 656 ++++++++++++++++++++
>> 1 file changed, 656 insertions(+)
>> create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
>> 
>> diff --git a/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
>> new file mode 100644
>> index 000000000000..8b82b8783127
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
>> @@ -0,0 +1,656 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
>> +// Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com>
>> +
>> +#include <dt-bindings/clock/sun6i-rtc.h>
>> +#include <dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h>
>> +#include <dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h>
>> +#include <dt-bindings/clock/allwinner,sun8i-v853-ccu.h>
>> +#include <dt-bindings/reset/allwinner,sun8i-v853-ccu.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/power/allwinner,sun8i-v853-ppu.h>
>> +
>> +/ {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + dcxo: dcxo-clk {
>> + compatible = "fixed-clock";
>> + clock-output-names = "osc24M";
>> + #clock-cells = <0>;
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7","arm,armv7";
> 
> The binding says to only give the CPU name, so just the first string,
> no fallback.
> 

ok

>> + reg = <0>;
>> + clocks = <&ccu CLK_CPU>;
>> + clock-names = "cpu";
>> + clock-frequency = <912000000>;
> 
> Please remove this, it only makes sense for a constant frequency, which
> is contradicted by the previous two properties.
> 

ok

>> + clock-latency = <200000>;
>> + cooling-min-level = <5>;
>> + cooling-max-level = <0>;
>> + #cooling-cells = <2>; /* min followed by max */
>> + dynamic-power-coefficient = <142>;
>> + };
>> + };
>> +
>> + pmu {
>> + compatible = "arm,cortex-a7-pmu";
>> + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> 
> What's the second interrupt for? I'd assume that's for a second core?
> Can you check that? Use "perf record" (perf stat does not trigger
> interrupts), and then check the counter in /proc/interrupts.
> 

I don't know what is the second IRQ, but the datasheet says C0_PMU0 and CO_PMU1 on the GIC section.
With perf record the IRQ#204 is triggering. Maybe this is a copy/paste error in the datasheet?

>> + interrupt-parent = <&gic>;
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv7-timer";
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> 
> This should be GIC_CPU_MASK_SIMPLE(1) for a single core CPU.
> 

Sure

>> +     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
>> +     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
>> +     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
>> + clock-frequency = <24000000>;
>> + interrupt-parent = <&gic>;
>> + arm,cpu-registers-not-fw-configured;
>> + arm,no-tick-in-suspend;
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + ranges;
>> + interrupt-parent = <&gic>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + dma-noncoherent;
>> +
>> + pio: pinctrl@2000000 {
>> + compatible = "allwinner,sun8i-v853-pinctrl";
>> + reg = <0x2000000 0x800>;
>> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_APB0>, <&dcxo>, <&rtc CLK_OSC32K>;
>> + clock-names = "apb", "hosc", "losc";
>> + gpio-controller;
>> + interrupt-controller;
>> + #gpio-cells = <3>;
>> + #interrupt-cells = <3>;
>> +
>> + /omit-if-no-ref/
>> + uart0_ph9_pins: uart0-ph9-pins {
>> + pins = "PH9", "PH10";
>> + function = "uart0";
>> + allwinner,pinmux = <5>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + uart2_pe12_pins: uart2-pe12-pins {
> 
> There is only one set of UART2 pins in PortE, so drop the pin number:
> uart2_pe_pins: uart-pe-pins {
> 

ok

>> + pins = "PE12", "PE13";
>> + function = "uart2";
>> + allwinner,pinmux = <6>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + dsi_2lane_pins: dsi-2lane-pins {
>> + pins = "PD1", "PD2", "PD3", "PD4", "PD5", "PD6";
>> + function = "dsi";
>> + allwinner,pinmux = <5>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + spi0_pins: spi0-pins {
> 
> SPI0 can be muxed to PortF as well, so please use spi0_pc_pins.
> 
>> + pins = "PC0", "PC1", "PC2", "PC3", "PC4", "PC5";
> 
> This includes the optional WP and HOLD pins, I think they should be
> separate? So add a second node, with just PC4 and PC5, and then
> reference both nodes in your SPI flash node, in the board .dts.
> The base pins should be untagged, but the optional pins should carry
> the omit-if-no-ref tag.
> 

What is your opinion about something like this?

                        spi0_pc_pins: spi0-pc-pins {
                                pins = "PC0", "PC2", "PC3";
                                function = "spi0";
                                allwinner,pinmux = <4>;
                        };

                        spi0_pc_cs0_pin: spi0-pc-cs0-pin {
                                pins = "PC1";
                                function = "spi0";
                                allwinner,pinmux = <4>;
                        };

                        /omit-if-no-ref/
                        spi0_pc_cs1_pin: spi0-pc-cs1-pin {
                                pins = "PC6";
                                function = "spi0";
                                allwinner,pinmux = <4>;
                        };

>> + function = "spi0";
>> + allwinner,pinmux = <4>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + spi3_pins: spi3-pins {
>> + pins = "PH11", "PH12", "PH13", "PH14";
>> + function = "spi3";
>> + allwinner,pinmux = <6>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + i2c2_ph11_pins: i2c2-ph11-pins {
>> + pins = "PH11", "PH12";
>> + function = "i2c2";
>> + allwinner,pinmux = <5>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + i2c3_ph13_pins: i2c3-ph13-pins {
>> + pins = "PH13", "PH14";
>> + function = "i2c3";
>> + allwinner,pinmux = <5>;
>> + };
>> +
>> + /omit-if-no-ref/
>> + mmc0_pins: mmc0-pins {
>> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
>> + function = "sdc0";
>> + allwinner,pinmux = <2>;
>> + drive-strength = <30>;
>> + bias-pull-up;
>> + };
>> +
>> + /omit-if-no-ref/
>> + mmc1_pins: mmc1-pins {
> 
> mmc1_pe_pins
> 

ok

>> + pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5";
>> + function = "sdc1";
>> + allwinner,pinmux = <6>;
>> + drive-strength = <30>;
>> + bias-pull-up;
>> + };
>> +
>> + /omit-if-no-ref/
>> + rmii_pe_pins: rmii-pe-pins {
>> + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
>> +       "PE5", "PE6", "PE7", "PE8", "PE9";
>> + function = "emac";
>> + allwinner,pinmux = <3>;
>> + };
>> + };
> 
> Verified that the pin numbers and the pinmux match the function in the
> manual.
> 
>> +
>> + ccu: clock-controller@2001000 {
>> + compatible = "allwinner,sun8i-v853-ccu";
>> + reg = <0x2001000 0x1000>;
>> + clocks = <&dcxo>,
>> + <&rtc CLK_IOSC>,
>> + <&rtc CLK_OSC32K>;
>> + clock-names = "hosc", "iosc", "losc";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + gpadc: adc@2009000 {
>> + compatible = "allwinner,sun20i-d1-gpadc";
>> + reg = <0x2009000 0x0400>;
>> + clocks = <&ccu CLK_BUS_GPADC>;
>> + resets = <&ccu RST_BUS_GPADC>;
>> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #io-channel-cells = <1>;
>> + };
>> +
>> + i2s0: i2s@2032000 {
>> + compatible = "allwinner,sun50i-r329-i2s";
>> + reg = <0x2032000 0x1000>;
>> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2S0>,
>> + <&ccu CLK_I2S0>;
>> + clock-names = "apb", "mod";
>> + resets = <&ccu RST_BUS_I2S0>;
>> + dmas = <&dma 3>, <&dma 3>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #sound-dai-cells = <0>;
>> + };
>> +
>> + i2s1: i2s@2033000 {
>> + compatible = "allwinner,sun50i-r329-i2s";
>> + reg = <0x2033000 0x1000>;
>> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2S1>,
>> + <&ccu CLK_I2S1>;
>> + clock-names = "apb", "mod";
>> + resets = <&ccu RST_BUS_I2S1>;
>> + dmas = <&dma 4>, <&dma 4>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #sound-dai-cells = <0>;
>> + };
>> +
>> + timer: timer@2050000 {
>> + compatible = "allwinner,sun20i-d1-timer",
>> +     "allwinner,sun8i-a23-timer";
>> + reg = <0x2050000 0xa0>;
>> + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> 
> Shouldn't there be four interrupts, for the four timers?
> 

Sure

>> + clocks = <&dcxo>;
>> + };
>> +
>> + wdt: watchdog@20500a0 {
>> + compatible = "allwinner,sun20i-d1-wdt-reset",
>> +     "allwinner,sun20i-d1-wdt";
>> + reg = <0x20500a0 0x20>;
>> + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&dcxo>, <&rtc CLK_OSC32K>;
>> + clock-names = "hosc", "losc";
>> + status = "reserved";
> 
> Who is this reserved for? Should be "okay", no?
> 

yes

>> + };
>> +
>> + uart0: serial@2500000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x2500000 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART0>;
>> + resets = <&ccu RST_BUS_UART0>;
>> + dmas = <&dma 14>, <&dma 14>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@2500400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x2500400 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART1>;
>> + resets = <&ccu RST_BUS_UART1>;
>> + dmas = <&dma 15>, <&dma 15>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@2500800 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x2500800 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART2>;
>> + resets = <&ccu RST_BUS_UART2>;
>> + dmas = <&dma 16>, <&dma 16>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial@2500c00 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x2500c00 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART3>;
>> + resets = <&ccu RST_BUS_UART3>;
>> + dmas = <&dma 17>, <&dma 17>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + i2c0: i2c@2502000 {
>> + compatible = "allwinner,sun8i-v536-i2c",
>> +     "allwinner,sun6i-a31-i2c";
>> + reg = <0x2502000 0x400>;
>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C0>;
>> + resets = <&ccu RST_BUS_I2C0>;
>> + dmas = <&dma 43>, <&dma 43>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c1: i2c@2502400 {
>> + compatible = "allwinner,sun8i-v536-i2c",
>> +     "allwinner,sun6i-a31-i2c";
>> + reg = <0x2502400 0x400>;
>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C1>;
>> + resets = <&ccu RST_BUS_I2C1>;
>> + dmas = <&dma 44>, <&dma 44>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c2: i2c@2502800 {
>> + compatible = "allwinner,sun8i-v536-i2c",
>> +     "allwinner,sun6i-a31-i2c";
>> + reg = <0x2502800 0x400>;
>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C2>;
>> + resets = <&ccu RST_BUS_I2C2>;
>> + dmas = <&dma 45>, <&dma 45>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c3: i2c@2502c00 {
>> + compatible = "allwinner,sun8i-v536-i2c",
>> +     "allwinner,sun6i-a31-i2c";
>> + reg = <0x2502c00 0x400>;
>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C3>;
>> + resets = <&ccu RST_BUS_I2C3>;
>> + dmas = <&dma 46>, <&dma 46>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c4: i2c@2503000 {
>> + compatible = "allwinner,sun8i-v536-i2c",
>> +     "allwinner,sun6i-a31-i2c";
>> + reg = <0x2503000 0x400>;
>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C4>;
>> + resets = <&ccu RST_BUS_I2C4>;
>> + dmas = <&dma 47>, <&dma 47>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + syscon: syscon@3000000 {
>> + compatible = "allwinner,sun8i-h3-system-control";
>> + reg = <0x3000000 0x1000>;
>> + ranges;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + sram_c: sram@20000 {
>> + compatible = "mmio-sram";
>> + reg = <0x00020000 0x21000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x00020000 0x21000>;
>> +
>> + ve_sram: sram-section@0 {
> 
> The manual says "Using ISP SRAM". Do you know what it really is?
> 

I didn’t had a chance to try this, but it can maybe be used by the ISP or VE?
I can rename it.

>> +    compatible = "allwinner,sun8i-v3s-sram-c", 
>> + "allwinner,sun4i-a10-sram-c1";
>> +    reg = <0x000000 0x21000>;
>> + };
>> + };
>> + };
>> +
>> + dma: dma-controller@3002000 {
>> + compatible = "allwinner,sun20i-d1-dma";
>> + reg = <0x3002000 0x1000>;
>> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
>> + clock-names = "bus", "mbus";
>> + resets = <&ccu RST_BUS_DMA>;
>> + dma-channels = <16>;
>> + dma-requests = <48>;
>> + #dma-cells = <1>;
>> + };
>> +
>> + hwspinlock: hwlock@3005000 {
>> +    compatible = "allwinner,sun6i-a31-hwspinlock";
>> + reg = <0x3005000 0x1000>;
>> + clocks = <&ccu CLK_BUS_SPINLOCK>;
>> + clock-names = "ahb";
>> + resets = <&ccu RST_BUS_SPINLOCK>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + sid: efuse@3006000 {
>> + compatible = "allwinner,sun20i-d1-sid";
>> + reg = <0x3006000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + ths_calib: ths-calib@14 {
>> + reg = <0x14 0x8>;
>> + };
>> + };
>> +
>> + hstimer@3008000 {
>> + compatible = "allwinner,sun7i-a20-hstimer";
>> + reg = <0x03008000 0x1000>;
>> + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
>> +     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_HSTIMER>;
>> + };
>> +
>> + gic: interrupt-controller@3021000 {
>> + compatible = "arm,gic-400";
>> + reg = <0x03021000 0x1000>, /* GIC Dist */
>> +      <0x03022000 0x2000>, /* GIC CPU */
>> +      <0x03024000 0x2000>, /* GIC VCPU Control */
>> +      <0x03026000 0x2000>; /* GIC VCPU */
>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> 
> GIC_CPU_MASK_SIMPLE(1)
> 

yes

>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + };
>> +
>> + mbus: dram-controller@3102000 {
>> + compatible = "allwinner,sun20i-d1-mbus";
>> + reg = <0x3102000 0x1000>,
>> +      <0x3103000 0x1000>;
>> + reg-names = "mbus", "dram";
>> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_MBUS>,
>> + <&ccu CLK_DRAM>,
>> + <&ccu CLK_BUS_DRAM>;
>> + clock-names = "mbus", "dram", "bus";
>> + dma-ranges = <0 0x40000000 0x80000000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interconnect-cells = <1>;
>> + };
>> +
>> + mmc0: mmc@4020000 {
>> + compatible = "allwinner,sun20i-d1-mmc";
>> + reg = <0x4020000 0x1000>;
>> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ccu RST_BUS_MMC0>;
>> + reset-names = "ahb";
>> + no-sdio;
>> + no-mmc;
>> + cap-sd-highspeed;
>> + max-frequency = <150000000>;
>> + mmc-ddr-1_8v;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc1: mmc@4021000 {
>> + compatible = "allwinner,sun20i-d1-mmc";
>> + reg = <0x4021000 0x1000>;
>> + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ccu RST_BUS_MMC1>;
>> + reset-names = "ahb";
>> + cap-sd-highspeed;
>> + cap-mmc-highspeed;
>> + max-frequency = <150000000>;
>> + mmc-ddr-1_8v;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc2: mmc@4022000 {
>> + compatible = "allwinner,sun20i-d1-mmc";
>> + reg = <0x4022000 0x1000>;
>> + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ccu RST_BUS_MMC2>;
>> + reset-names = "ahb";
>> + no-sdio;
>> + no-sd;
>> + cap-mmc-highspeed;
>> + max-frequency = <150000000>;
>> + mmc-ddr-1_8v;
>> + mmc-ddr-3_3v;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + spi0: spi@4025000 {
>> + compatible = "allwinner,sun50i-r329-spi";
>> + reg = <0x4025000 0x1000>;
>> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
>> + clock-names = "ahb", "mod";
>> + resets = <&ccu RST_BUS_SPI0>;
>> + dmas = <&dma 22>, <&dma 22>;
>> + dma-names = "rx", "tx";
>> + num-cs = <1>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + spi1: spi@4026000 {
>> + compatible = "allwinner,sun50i-r329-spi-dbi",
>> +     "allwinner,sun50i-r329-spi";
>> + reg = <0x4026000 0x1000>;
>> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
>> + clock-names = "ahb", "mod";
>> + resets = <&ccu RST_BUS_SPI1>;
>> + dmas = <&dma 23>, <&dma 23>;
>> + dma-names = "rx", "tx";
>> + num-cs = <1>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + spi2: spi@4027000 {
>> + compatible = "allwinner,sun50i-r329-spi";
>> + reg = <0x4027000 0x1000>;
>> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
>> + clock-names = "ahb", "mod";
>> + resets = <&ccu RST_BUS_SPI2>;
>> + dmas = <&dma 24>, <&dma 24>;
>> + dma-names = "rx", "tx";
>> + num-cs = <1>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + spi3: spi@4028000 {
>> + compatible = "allwinner,sun50i-r329-spi";
>> + reg = <0x4028000 0x1000>;
>> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
>> + clock-names = "ahb", "mod";
>> + resets = <&ccu RST_BUS_SPI3>;
>> + dmas = <&dma 25>, <&dma 25>;
>> + dma-names = "rx", "tx";
>> + num-cs = <1>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + usb_otg: usb@4100000 {
>> + compatible = "allwinner,sun8i-a33-musb";
>> + reg = <0x4100000 0x400>;
>> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "mc";
>> + clocks = <&ccu CLK_BUS_OTG>;
>> + resets = <&ccu RST_BUS_OTG>;
>> + extcon = <&usbphy 0>;
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + usbphy: phy@4100400 {
>> + compatible = "allwinner,sun8i-v853-usb-phy";
>> + reg = <0x4100400 0x100>,
>> +      <0x4101800 0x100>;
>> + reg-names = "phy_ctrl",
>> +    "pmu0";
>> + clocks = <&ccu CLK_USB_OHCI>;
>> + clock-names = "usb0_phy";
>> + resets = <&ccu RST_USB_PHY>;
>> + reset-names = "usb0_reset";
>> + status = "disabled";
>> + #phy-cells = <1>;
>> + };
>> +
>> + ehci0: usb@4101000 {
>> + compatible = "generic-ehci";
>> + reg = <0x4101000 0x100>;
>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_OHCI>,
>> + <&ccu CLK_BUS_EHCI>,
>> + <&ccu CLK_USB_OHCI>;
>> + resets = <&ccu RST_BUS_OHCI>,
>> + <&ccu RST_BUS_EHCI>;
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ohci0: usb@4101400 {
>> + compatible = "generic-ohci";
>> + reg = <0x4101400 0x100>;
>> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_OHCI>,
>> + <&ccu CLK_USB_OHCI>;
>> + resets = <&ccu RST_BUS_OHCI>;
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ppu: power-controller@7001000 {
>> + compatible = "allwinner,sun8i-v853-ppu";
>> + reg = <0x7001000 0x400>;
>> + clocks = <&r_ccu CLK_BUS_R_PPU>;
>> + resets = <&r_ccu RST_BUS_R_PPU>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> + r_ccu: clock-controller@7010000 {
>> + compatible = "allwinner,sun8i-v853-r-ccu";
>> + reg = <0x7010000 0x230>;
>> + clocks = <&dcxo>,
>> + <&rtc CLK_IOSC>,
>> + <&rtc CLK_OSC32K>,
>> + <&ccu CLK_PLL_PERIPH_200M>,
>> + <&ccu CLK_PLL_AUDIO_4X>;
>> + clock-names = "hosc",
>> +      "iosc",
>> +      "losc",
>> +      "pll-periph",
>> +      "pll-audio";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + nmi_intc: intc-nmi@7010320 {
>> + compatible = "allwinner,sun9i-a80-nmi";
>> + interrupt-parent = <&gic>;
>> + #interrupt-cells = <2>;
>> + #address-cells = <0>;
>> + interrupt-controller;
>> + reg = <0x07010320 0xc>;
>> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + rtc: rtc@7090000 {
>> + compatible = "allwinner,sun50i-r329-rtc";
>> + reg = <0x7090000 0x400>;
>> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&r_ccu CLK_BUS_R_RTC>;
>> + clock-names = "bus";
>> + resets = <&r_ccu RST_BUS_R_RTC>;
>> + wakeup-source;
>> + #clock-cells = <1>;
>> + };
> 
> Verified that all MMIO base addresses, DMA channels and interrupts are
> matching the manual.
> 
> Cheers,
> Andre
> 
>> + };
>> +};
> 

Re: [PATCH v2 03/10] dt-bindings: clock: sunxi-ng: add compatibles for V853

[András Szemző]

Thanks for your review, I’ll change and explain it better.

> On 11 Feb 2025, at 22:02, Rob Herring <robh@kernel.org> wrote:
> 
> On Wed, Feb 05, 2025 at 01:52:18PM +0100, Andras Szemzo wrote:
>> V853 has 2 CCUs, add compatible strings for it.
>> 
>> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
>> ---
>> .../clock/allwinner,sun4i-a10-ccu.yaml        |   3 +
>> .../clock/allwinner,sun8i-v853-ccu.h          | 132 ++++++++++++++++++
>> .../clock/allwinner,sun8i-v853-r-ccu.h        |  16 +++
>> .../reset/allwinner,sun8i-v853-ccu.h          |  60 ++++++++
>> .../reset/allwinner,sun8i-v853-r-ccu.h        |  14 ++
>> 5 files changed, 225 insertions(+)
>> create mode 100644 include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h
>> create mode 100644 include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h
>> create mode 100644 include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h
>> create mode 100644 include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h
>> 
>> diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
>> index 1690b9d99c3d..9369d62284ed 100644
>> --- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
>> +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
>> @@ -33,6 +33,8 @@ properties:
>>       - allwinner,sun8i-r40-ccu
>>       - allwinner,sun8i-v3-ccu
>>       - allwinner,sun8i-v3s-ccu
>> +      - allwinner,sun8i-v853-ccu
>> +      - allwinner,sun8i-v853-r-ccu
> 
> Please explain the difference between these in the commit message.
> 
>>       - allwinner,sun9i-a80-ccu
>>       - allwinner,sun20i-d1-ccu
>>       - allwinner,sun20i-d1-r-ccu
>> @@ -103,6 +105,7 @@ else:
>>       compatible:
>>         enum:
>>           - allwinner,sun20i-d1-ccu
>> +          - allwinner,sun8i-v853-ccu
>>           - allwinner,sun50i-a100-ccu
>>           - allwinner,sun50i-h6-ccu
>>           - allwinner,sun50i-h616-ccu
>> diff --git a/include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h b/include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h
>> new file mode 100644
>> index 000000000000..cf56c168e1cd
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h
>> @@ -0,0 +1,132 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
> 
> Dual license.
> 
>> +/*
>> + * Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_ALLWINNER_SUN8I_V85X_CCU_H_
>> +#define _DT_BINDINGS_CLK_ALLWINNER_SUN8I_V85X_CCU_H_
>> +
>> +#define CLK_OSC12M		0
>> +#define CLK_PLL_CPU		1
>> +#define CLK_PLL_DDR		2
>> +#define CLK_PLL_PERIPH_4X	3
>> +#define CLK_PLL_PERIPH_2X	4
>> +#define CLK_PLL_PERIPH_800M	5
>> +#define CLK_PLL_PERIPH_480M	6
>> +#define CLK_PLL_PERIPH_600M	7
>> +#define CLK_PLL_PERIPH_400M	8
>> +#define CLK_PLL_PERIPH_300M	9
>> +#define CLK_PLL_PERIPH_200M	10
>> +#define CLK_PLL_PERIPH_160M	11
>> +#define CLK_PLL_PERIPH_150M	12
>> +#define CLK_PLL_VIDEO_4X	13
>> +#define CLK_PLL_VIDEO_2X	14
>> +#define CLK_PLL_VIDEO_1X	15
>> +#define CLK_PLL_CSI_4X		16
>> +#define CLK_PLL_AUDIO_DIV2	17
>> +#define CLK_PLL_AUDIO_DIV5	18
>> +#define CLK_PLL_AUDIO_4X	19
>> +#define CLK_PLL_AUDIO_1X	20
>> +#define CLK_PLL_NPU_4X		21
>> +#define CLK_CPU			22
>> +#define CLK_CPU_AXI		23
>> +#define CLK_CPU_APB		24
>> +#define CLK_AHB			25
>> +#define CLK_APB0		26
>> +#define CLK_APB1		27
>> +#define CLK_MBUS		28
>> +#define CLK_DE			29
>> +#define CLK_BUS_DE		30
>> +#define CLK_G2D			31
>> +#define CLK_BUS_G2D		32
>> +#define CLK_CE			33
>> +#define CLK_BUS_CE		34
>> +#define CLK_VE			35
>> +#define CLK_BUS_VE		36
>> +#define CLK_NPU			37
>> +#define CLK_BUS_NPU		38
>> +#define CLK_BUS_DMA		39
>> +#define CLK_BUS_MSGBOX0		40
>> +#define CLK_BUS_MSGBOX1		41
>> +#define CLK_BUS_SPINLOCK	42
>> +#define CLK_BUS_HSTIMER		43
>> +#define CLK_AVS			44
>> +#define CLK_BUS_DBG		45
>> +#define CLK_BUS_PWM		46
>> +#define CLK_BUS_IOMMU		47
>> +#define CLK_DRAM		48
>> +#define CLK_MBUS_DMA		49
>> +#define CLK_MBUS_VE		50
>> +#define CLK_MBUS_CE		51
>> +#define CLK_MBUS_CSI		52
>> +#define CLK_MBUS_ISP		53
>> +#define CLK_MBUS_G2D		54
>> +#define CLK_BUS_DRAM		55
>> +#define CLK_MMC0		56
>> +#define CLK_MMC1		57
>> +#define CLK_MMC2		58
>> +#define CLK_BUS_MMC0		59
>> +#define CLK_BUS_MMC1		60
>> +#define CLK_BUS_MMC2		61
>> +#define CLK_BUS_UART0		62
>> +#define CLK_BUS_UART1		63
>> +#define CLK_BUS_UART2		64
>> +#define CLK_BUS_UART3		65
>> +#define CLK_BUS_I2C0		66
>> +#define CLK_BUS_I2C1		67
>> +#define CLK_BUS_I2C2		68
>> +#define CLK_BUS_I2C3		69
>> +#define CLK_BUS_I2C4		70
>> +#define CLK_SPI0		71
>> +#define CLK_SPI1		72
>> +#define CLK_SPI2		73
>> +#define CLK_SPI3		74
>> +#define CLK_BUS_SPI0		75
>> +#define CLK_BUS_SPI1		76
>> +#define CLK_BUS_SPI2		77
>> +#define CLK_BUS_SPI3		78
>> +#define CLK_SPIF		79
>> +#define CLK_BUS_SPIF		80
>> +#define CLK_EMAC_25M		81
>> +#define CLK_BUS_EMAC		82
>> +#define CLK_BUS_GPADC		83
>> +#define CLK_BUS_THS		84
>> +#define CLK_I2S0		85
>> +#define CLK_I2S1		86
>> +#define CLK_BUS_I2S0		87
>> +#define CLK_BUS_I2S1		88
>> +#define CLK_DMIC		89
>> +#define CLK_BUS_DMIC		90
>> +#define CLK_AUDIO_CODEC_DAC	91
>> +#define CLK_AUDIO_CODEC_ADC	92
>> +#define CLK_BUS_AUDIO_CODEC	93
>> +#define CLK_USB_OHCI		94
>> +#define CLK_BUS_OHCI		95
>> +#define CLK_BUS_EHCI		96
>> +#define CLK_BUS_OTG		97
>> +#define CLK_BUS_DPSS_TOP	98
>> +#define CLK_MIPI_DSI		99
>> +#define CLK_BUS_MIPI_DSI	100
>> +#define CLK_TCON_LCD		101
>> +#define CLK_BUS_TCON_LCD	102
>> +#define CLK_CSI_TOP		103
>> +#define CLK_CSI_MCLK0		104
>> +#define CLK_CSI_MCLK1		105
>> +#define CLK_CSI_MCLK2		106
>> +#define CLK_BUS_CSI		107
>> +#define CLK_BUS_WIEGAND		108
>> +#define CLK_RISCV		109
>> +#define CLK_RISCV_AXI		110
>> +#define CLK_RISCV_CORE_GATE	111
>> +#define CLK_RISCV_CFG_GATE	112
>> +#define CLK_FANOUT_24M		113
>> +#define CLK_FANOUT_12M		114
>> +#define CLK_FANOUT_16M		115
>> +#define CLK_FANOUT_25M		116
>> +#define CLK_FANOUT_27M		117
>> +#define CLK_FANOUT_PCLK		118
>> +#define CLK_FANOUT0		119
>> +#define CLK_FANOUT1		120
>> +#define CLK_FANOUT2		121
>> +
>> +#endif
>> diff --git a/include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h b/include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h
>> new file mode 100644
>> index 000000000000..48fe598b7bd8
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h
>> @@ -0,0 +1,16 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_ALLWINNER_SUN8I_V853_R_CCU_H_
>> +#define _DT_BINDINGS_CLK_ALLWINNER_SUN8I_V853_R_CCU_H_
>> +
>> +#define CLK_R_AHB		0
>> +#define CLK_R_APB0		1
>> +#define CLK_BUS_R_TWD		2
>> +#define CLK_BUS_R_PPU		3
>> +#define CLK_BUS_R_RTC		4
>> +#define CLK_BUS_R_CPUCFG	5
>> +
>> +#endif
>> diff --git a/include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h b/include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h
>> new file mode 100644
>> index 000000000000..e258117518aa
>> --- /dev/null
>> +++ b/include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h
>> @@ -0,0 +1,60 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_RST_ALLWINNER_SUN8I_V85X_CCU_H_
>> +#define _DT_BINDINGS_RST_ALLWINNER_SUN8I_V85X_CCU_H_
>> +
>> +#define RST_MBUS		0
>> +#define RST_BUS_DE		1
>> +#define RST_BUS_G2D		2
>> +#define RST_BUS_CE		3
>> +#define RST_BUS_VE		4
>> +#define RST_BUS_NPU		5
>> +#define RST_BUS_DMA		6
>> +#define RST_BUS_MSGBOX0		7
>> +#define RST_BUS_MSGBOX1		8
>> +#define RST_BUS_SPINLOCK	9
>> +#define RST_BUS_HSTIMER		10
>> +#define RST_BUS_DBG		11
>> +#define RST_BUS_PWM		12
>> +#define RST_BUS_DRAM		13
>> +#define RST_BUS_MMC0		14
>> +#define RST_BUS_MMC1		15
>> +#define RST_BUS_MMC2		16
>> +#define RST_BUS_UART0		17
>> +#define RST_BUS_UART1		18
>> +#define RST_BUS_UART2		19
>> +#define RST_BUS_UART3		20
>> +#define RST_BUS_I2C0		21
>> +#define RST_BUS_I2C1		22
>> +#define RST_BUS_I2C2		23
>> +#define RST_BUS_I2C3		24
>> +#define RST_BUS_I2C4		25
>> +#define RST_BUS_SPI0		26
>> +#define RST_BUS_SPI1		27
>> +#define RST_BUS_SPI2		28
>> +#define RST_BUS_SPI3		29
>> +#define RST_BUS_SPIF		30
>> +#define RST_BUS_EMAC		31
>> +#define RST_BUS_GPADC		32
>> +#define RST_BUS_THS		33
>> +#define RST_BUS_I2S0		34
>> +#define RST_BUS_I2S1		35
>> +#define RST_BUS_DMIC		36
>> +#define RST_BUS_AUDIO_CODEC	37
>> +#define RST_USB_PHY		38
>> +#define RST_BUS_OHCI		39
>> +#define RST_BUS_EHCI		40
>> +#define RST_BUS_OTG		41
>> +#define RST_BUS_DPSS_TOP	42
>> +#define RST_BUS_MIPI_DSI	43
>> +#define RST_BUS_TCON_LCD	44
>> +#define RST_BUS_CSI		45
>> +#define RST_BUS_WIEGAND		46
>> +#define RST_RISCV_SYS_APB	47
>> +#define RST_RISCV_SOFT		48
>> +#define RST_RISCV_CFG		49
>> +
>> +#endif
>> diff --git a/include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h b/include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h
>> new file mode 100644
>> index 000000000000..57629d635115
>> --- /dev/null
>> +++ b/include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h
>> @@ -0,0 +1,14 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_RST_ALLWINNER_SUN8I_V853_R_CCU_H_
>> +#define _DT_BINDINGS_RST_ALLWINNER_SUN8I_V853_R_CCU_H_
>> +
>> +#define RST_BUS_R_TWD		0
>> +#define RST_BUS_R_PPU		1
>> +#define RST_BUS_R_RTC		2
>> +#define RST_BUS_R_CPUCFG	3
>> +
>> +#endif
>> -- 
>> 2.39.5
>> 

Re: [PATCH v2 00/10] Support for Allwinner V853 SoC

[Ulf Hansson]

On Wed, 5 Feb 2025 at 13:52, Andras Szemzo <szemzo.andras@gmail.com> wrote:
>
> V85x is a SoC from Allwinner with video encoding targeted for the field of
> IP Camera. It integrates the single CA7 core, and a T-Head E907 RISC-V mcu.
> The SoC has the usual Allwinner peripherals and a Vivante NPU.
> V853 is a BGA package without DRAM, V851s/V851s3 has the same die with
> co-packaged 64MB/128MB DRAM (in a QFN88 package).
>
> This patchset tries to add basical support for the V853 device family.

Patch5 and patch6 applied for next via my pmdomain tree, thanks!

Note, patch5 (the DT patch) is also available on the immutable dt
branch, if soc maintainers need to pull it.

Kind regards
Uffe



>
> Changelog - v2:
>  - rebased on 6.14-rc1
>  - add a needed gate with key support to sunxi clk
>  - rewrite the ccu-r driver
>  - fix license issues
>  - remove the pinctrl binding, as it has beed applied
>  - rework the pinctrl driver, use the new sunxi dt based mux support. This new pinctrl
>    driver depends on the new sunxi device-tree based mux support patch series [1].
>  - remove the new usb phy binding, as the v853's usb phy is very close to d1/a64
>  - add a board dts
>  - ccu: add module description
>  - ccu: fix PLL enable bits, and min multipliers
>  - ccu: change PLL flags to CLK_SET_RATE_GATE
>  - ccu: use SUNXI_CCU_M_HWS at peripheral PLLs
>  - ccu: convert the VIDEO and CSI PLLs from nm type to nkmp according to BSP
>  - ccu: cpu axi clk use pointer
>  - ccu: fix comments
>  - ccu: swap i2s1 and i2s0 bus clocks
>  - ccu: fix indentation
>  - ccu: fix RST_BUS_SPIF order
>  - ccu: convert RST_RISCV_CLK_GATING from reset to gate
>
> [1]: https://lore.kernel.org/linux-sunxi/20241111005750.13071-1-andre.przywara@arm.com/T/
>
> Andras Szemzo (10):
>   clk: sunxi-ng: allow key feature in ccu reset and gate
>   pinctrl: sunxi: add driver for Allwinner V853
>   dt-bindings: clock: sunxi-ng: add compatibles for V853
>   clk: sunxi-ng: add CCU drivers for V853
>   dt-bindings: power: add V853 ppu bindings
>   pmdomain: sunxi: add V853 ppu support
>   dt-bindings: phy: allwinner: add v853 usb phy
>   phy: allwinner: add v853 usb phy compatible
>   ARM: dts: sun8i: add DTSI file for V853
>   ARM: dts: sun8i: add DTS file for yuzuki-lizard V851s
>
>  .../clock/allwinner,sun4i-a10-ccu.yaml        |    3 +
>  .../phy/allwinner,sun50i-a64-usb-phy.yaml     |    2 +
>  .../power/allwinner,sun20i-d1-ppu.yaml        |    1 +
>  arch/arm/boot/dts/allwinner/Makefile          |    1 +
>  .../boot/dts/allwinner/sun8i-v851s-lizard.dts |  196 +++
>  arch/arm/boot/dts/allwinner/sun8i-v853.dtsi   |  656 ++++++++++
>  drivers/clk/sunxi-ng/Kconfig                  |   10 +
>  drivers/clk/sunxi-ng/Makefile                 |    4 +
>  drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c       |  120 ++
>  drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h       |   14 +
>  drivers/clk/sunxi-ng/ccu-sun8i-v853.c         | 1145 +++++++++++++++++
>  drivers/clk/sunxi-ng/ccu-sun8i-v853.h         |   14 +
>  drivers/clk/sunxi-ng/ccu_common.h             |    2 +
>  drivers/clk/sunxi-ng/ccu_gate.c               |    6 +
>  drivers/clk/sunxi-ng/ccu_gate.h               |   14 +
>  drivers/clk/sunxi-ng/ccu_mux.c                |    4 +-
>  drivers/clk/sunxi-ng/ccu_reset.c              |    7 +
>  drivers/clk/sunxi-ng/ccu_reset.h              |    2 +-
>  drivers/phy/allwinner/phy-sun4i-usb.c         |   10 +
>  drivers/pinctrl/sunxi/Kconfig                 |    5 +
>  drivers/pinctrl/sunxi/Makefile                |    1 +
>  drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c    |   53 +
>  drivers/pmdomain/sunxi/sun20i-ppu.c           |   15 +
>  .../clock/allwinner,sun8i-v853-ccu.h          |  132 ++
>  .../clock/allwinner,sun8i-v853-r-ccu.h        |   16 +
>  .../power/allwinner,sun8i-v853-ppu.h          |   10 +
>  .../reset/allwinner,sun8i-v853-ccu.h          |   60 +
>  .../reset/allwinner,sun8i-v853-r-ccu.h        |   14 +
>  28 files changed, 2513 insertions(+), 4 deletions(-)
>  create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v851s-lizard.dts
>  create mode 100644 arch/arm/boot/dts/allwinner/sun8i-v853.dtsi
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.h
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c
>  create mode 100644 include/dt-bindings/clock/allwinner,sun8i-v853-ccu.h
>  create mode 100644 include/dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h
>  create mode 100644 include/dt-bindings/power/allwinner,sun8i-v853-ppu.h
>  create mode 100644 include/dt-bindings/reset/allwinner,sun8i-v853-ccu.h
>  create mode 100644 include/dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h
>
> --
> 2.39.5
>

Re: [PATCH v2 04/10] clk: sunxi-ng: add CCU drivers for V853

[Jernej Škrabec]

Dne sreda, 5. februar 2025 ob 13:52:19 Srednjeevropski standardni čas je Andras Szemzo napisal(a):
> V853 has similar gates/resets like existing Allwinner SOCs. Add support for it's CCU and PRCM CCU.
> 
> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
> ---
>  drivers/clk/sunxi-ng/Kconfig            |   10 +
>  drivers/clk/sunxi-ng/Makefile           |    4 +
>  drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c |  120 +++
>  drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h |   14 +
>  drivers/clk/sunxi-ng/ccu-sun8i-v853.c   | 1145 +++++++++++++++++++++++
>  drivers/clk/sunxi-ng/ccu-sun8i-v853.h   |   14 +
>  6 files changed, 1307 insertions(+)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.h
> 
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index b547198a2c65..e257373177e0 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -12,6 +12,16 @@ config SUNIV_F1C100S_CCU
>  	default y
>  	depends on MACH_SUNIV || COMPILE_TEST
>  
> +config SUN8I_V853_CCU
> +	tristate "Support for the Allwinner V853/V851s/V851SE CCU"
> +	default MACH_SUN8I
> +	depends on MACH_SUN8I || COMPILE_TEST
> +
> +config SUN8I_V853_R_CCU
> +	tristate "Support for the Allwinner V853/V851s/V851SE PRCM CCU"
> +	default MACH_SUN8I
> +	depends on MACH_SUN8I || COMPILE_TEST

Generally, this are two patches, one for each driver.

> +
>  config SUN20I_D1_CCU
>  	tristate "Support for the Allwinner D1/R528/T113 CCU"
>  	default y
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 6b3ae2b620db..b87928462e15 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -25,6 +25,8 @@ sunxi-ccu-y			+= ccu_mp.o
>  
>  # SoC support
>  obj-$(CONFIG_SUNIV_F1C100S_CCU)	+= suniv-f1c100s-ccu.o
> +obj-$(CONFIG_SUN8I_V853_CCU)	+= sun8i-v853-ccu.o
> +obj-$(CONFIG_SUN8I_V853_R_CCU)	+= sun8i-v853-r-ccu.o

Put it to other sun8i drivers.

>  obj-$(CONFIG_SUN20I_D1_CCU)	+= sun20i-d1-ccu.o
>  obj-$(CONFIG_SUN20I_D1_R_CCU)	+= sun20i-d1-r-ccu.o
>  obj-$(CONFIG_SUN50I_A64_CCU)	+= sun50i-a64-ccu.o
> @@ -50,6 +52,8 @@ obj-$(CONFIG_SUN9I_A80_CCU)	+= sun9i-a80-de-ccu.o
>  obj-$(CONFIG_SUN9I_A80_CCU)	+= sun9i-a80-usb-ccu.o
>  
>  suniv-f1c100s-ccu-y		+= ccu-suniv-f1c100s.o
> +sun8i-v853-ccu-y		+= ccu-sun8i-v853.o
> +sun8i-v853-r-ccu-y		+= ccu-sun8i-v853-r.o

Ditto.

>  sun20i-d1-ccu-y			+= ccu-sun20i-d1.o
>  sun20i-d1-r-ccu-y		+= ccu-sun20i-d1-r.o
>  sun50i-a64-ccu-y		+= ccu-sun50i-a64.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
> new file mode 100644
> index 000000000000..bd60e00cda7f
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
> @@ -0,0 +1,120 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
> + *
> + * Based on ccu-sun20i-d1-r.c by Samuel Holland.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +
> +#include "ccu-sun8i-v853-r.h"
> +
> +static const struct clk_parent_data r_ahb_apb0_parents[] = {
> +	{ .fw_name = "hosc" },
> +	{ .fw_name = "losc" },
> +	{ .fw_name = "iosc" },
> +	{ .fw_name = "pll-periph" },
> +	{ .fw_name = "pll-audio" }
> +};
> +
> +static SUNXI_CCU_MP_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
> +				  r_ahb_apb0_parents, 0x000,
> +				  0, 5,		/* M */
> +				  8, 2,		/* P */
> +				  24, 3,	/* mux */
> +				  0);
> +static const struct clk_hw *r_ahb_hw = &r_ahb_clk.common.hw;
> +
> +static SUNXI_CCU_MP_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
> +				  r_ahb_apb0_parents, 0x00c,
> +				  0, 5,		/* M */
> +				  8, 2,		/* P */
> +				  24, 3,	/* mux */
> +				  0);
> +static const struct clk_hw *r_apb0_hw = &r_apb0_clk.common.hw;

Where can I look for above clocks? There are not described in BSP driver.

> +
> +static SUNXI_CCU_GATE_HWS(bus_r_twd_clk, "bus-r-twd", &r_apb0_hw, 
> +			  0x12c, BIT(0), 0);
> +static SUNXI_CCU_GATE_HWS(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_hw,
> +			  0x1ac, BIT(0), 0);
> +static SUNXI_CCU_GATE_HWS(bus_r_rtc_clk, "bus-r-rtc", &r_ahb_hw,
> +			  0x20c, BIT(0), 0);
> +static SUNXI_CCU_GATE_HWS(bus_r_cpucfg_clk, "bus-r-cpucfg", &r_apb0_hw,
> +			  0x22c, BIT(0), 0);
> +
> +static struct ccu_common *sun8i_v853_r_ccu_clks[] = {
> +	&r_ahb_clk.common,
> +	&r_apb0_clk.common,
> +	&bus_r_twd_clk.common,
> +	&bus_r_ppu_clk.common,
> +	&bus_r_rtc_clk.common,
> +	&bus_r_cpucfg_clk.common,
> +};
> +
> +static struct clk_hw_onecell_data sun8i_v853_r_hw_clks = {
> +	.num	= CLK_NUMBER,
> +	.hws	= {
> +		[CLK_R_AHB]		= &r_ahb_clk.common.hw,
> +		[CLK_R_APB0]		= &r_apb0_clk.common.hw,
> +		[CLK_BUS_R_TWD]		= &bus_r_twd_clk.common.hw,
> +		[CLK_BUS_R_PPU]		= &bus_r_ppu_clk.common.hw,
> +		[CLK_BUS_R_RTC]		= &bus_r_rtc_clk.common.hw,
> +		[CLK_BUS_R_CPUCFG]	= &bus_r_cpucfg_clk.common.hw,
> +	},
> +};
> +
> +static const struct ccu_reset_map sun8i_v853_r_ccu_resets[] = {
> +	[RST_BUS_R_TWD]		= { 0x12c, BIT(16) },

Where did you get that? BSP driver that I checked doesn't mentions it.

> +	[RST_BUS_R_PPU]		= { 0x1ac, BIT(16) },
> +	[RST_BUS_R_RTC]		= { 0x20c, BIT(16) },
> +	[RST_BUS_R_CPUCFG]	= { 0x22c, BIT(16) },
> +};
> +
> +static const struct sunxi_ccu_desc sun8i_v853_r_ccu_desc = {
> +	.ccu_clks	= sun8i_v853_r_ccu_clks,
> +	.num_ccu_clks	= ARRAY_SIZE(sun8i_v853_r_ccu_clks),
> +
> +	.hw_clks	= &sun8i_v853_r_hw_clks,
> +
> +	.resets		= sun8i_v853_r_ccu_resets,
> +	.num_resets	= ARRAY_SIZE(sun8i_v853_r_ccu_resets),
> +};
> +
> +static int sun8i_v853_r_ccu_probe(struct platform_device *pdev)
> +{
> +	void __iomem *reg;
> +
> +	reg = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(reg))
> +		return PTR_ERR(reg);
> +
> +	return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_v853_r_ccu_desc);
> +}
> +
> +static const struct of_device_id sun8i_v853_r_ccu_ids[] = {
> +	{ .compatible = "allwinner,sun8i-v853-r-ccu" },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, sun8i_v853_r_ccu_ids);
> +
> +static struct platform_driver sun8i_v853_r_ccu_driver = {
> +	.probe	= sun8i_v853_r_ccu_probe,
> +	.driver	= {
> +		.name			= "sun8i-v853-r-ccu",
> +		.suppress_bind_attrs	= true,
> +		.of_match_table		= sun8i_v853_r_ccu_ids,
> +	},
> +};
> +module_platform_driver(sun8i_v853_r_ccu_driver);
> +
> +MODULE_IMPORT_NS("SUNXI_CCU");
> +MODULE_DESCRIPTION("Support for the Allwinner V853 PRCM CCU");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
> new file mode 100644
> index 000000000000..2c6cc7b6f251
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
> + */
> +
> +#ifndef _CCU_SUN8I_V853_R_H
> +#define _CCU_SUN8I_V853_R_H
> +
> +#include <dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h>
> +#include <dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h>
> +
> +#define CLK_NUMBER		(CLK_BUS_R_CPUCFG + 1)
> +
> +#endif
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853.c b/drivers/clk/sunxi-ng/ccu-sun8i-v853.c
> new file mode 100644
> index 000000000000..4b32f3a913cf
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853.c
> @@ -0,0 +1,1145 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
> + *
> + * Based on ccu-sun20i-d1.c by Samuel Holland.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#include "../clk.h"
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +#include "ccu_mult.h"
> +#include "ccu_nk.h"
> +#include "ccu_nkm.h"
> +#include "ccu_nkmp.h"
> +#include "ccu_nm.h"
> +
> +#include "ccu-sun8i-v853.h"
> +
> +static const struct clk_parent_data osc24M[] = {
> +	{ .fw_name = "hosc" }
> +};
> +
> +/*
> + * For the CPU PLL, the output divider is described as "only for testing"
> + * in the user manual. So it's not modelled and forced to 0.
> + */
> +#define SUN8I_V853_PLL_CPU_REG		0x000
> +
> +static struct ccu_mult pll_cpu_clk = {
> +	.enable		= BIT(27),
> +	.lock		= BIT(28),
> +	.mult		= _SUNXI_CCU_MULT_MIN(8, 8, 11),
> +	.common		= {
> +		.reg		= 0x000,
> +		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-cpu", osc24M,
> +							   &ccu_mult_ops,
> +							   CLK_SET_RATE_GATE),
> +	},
> +};
> +
> +/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
> +#define SUN8I_V853_PLL_DDR_REG		0x010
> +static struct ccu_nkmp pll_ddr_clk = {
> +	.enable		= BIT(27),
> +	.lock		= BIT(28),
> +	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 11),
> +	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
> +	.p		= _SUNXI_CCU_DIV(0, 1), /* output divider */
> +	.common		= {
> +		.reg		= 0x010,
> +		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-ddr", osc24M,
> +							   &ccu_nkmp_ops,
> +							   CLK_SET_RATE_GATE),
> +	},
> +};
> +
> +#define SUN8I_V853_PLL_PERIPH_REG	0x020
> +static struct ccu_nm pll_periph_4x_clk = {
> +	.enable		= BIT(27),
> +	.lock		= BIT(28),
> +	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 11),
> +	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
> +	.common		= {
> +		.reg		= 0x020,
> +		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-periph-4x", osc24M,
> +							   &ccu_nm_ops,
> +							   CLK_SET_RATE_GATE),
> +	},
> +};
> +
> +static const struct clk_hw *pll_periph_4x_hws[] = {
> +	&pll_periph_4x_clk.common.hw
> +};
> +
> +static SUNXI_CCU_M_HWS(pll_periph_2x_clk, "pll-periph-2x", pll_periph_4x_hws,
> +		       0x020, 16, 3, 0);
> +
> +static SUNXI_CCU_M_HWS(pll_periph_800M_clk, "pll-periph-800M", pll_periph_4x_hws,
> +		       0x020, 20, 3, 0);
> +
> +static SUNXI_CCU_M_HWS(pll_periph_480M_clk, "pll-periph-480M", pll_periph_4x_hws,
> +		       0x020, 2, 3, 0);
> +
> +static CLK_FIXED_FACTOR_HW(pll_periph_600M_clk, "pll-periph-600M",
> +			   &pll_periph_2x_clk.common.hw, 2, 1, 0);
> +
> +static CLK_FIXED_FACTOR_HW(pll_periph_400M_clk, "pll-periph-400M",
> +			   &pll_periph_2x_clk.common.hw, 3, 1, 0);
> +
> +static CLK_FIXED_FACTOR_HW(pll_periph_300M_clk, "pll-periph-300M",
> +			   &pll_periph_600M_clk.hw, 2, 1, 0);
> +
> +static CLK_FIXED_FACTOR_HW(pll_periph_200M_clk, "pll-periph-200M",
> +			   &pll_periph_400M_clk.hw, 2, 1, 0);
> +
> +static CLK_FIXED_FACTOR_HW(pll_periph_160M_clk, "pll-periph-160M",
> +			   &pll_periph_480M_clk.common.hw, 3, 1, 0);
> +
> +static CLK_FIXED_FACTOR_HW(pll_periph_150M_clk, "pll-periph-150M",
> +			   &pll_periph_300M_clk.hw, 2, 1, 0);
> +
> +/*
> + * For Video PLLs, the output divider is described as "only for testing"
> + * in the user manual.
> + */
> +#define SUN8I_V853_PLL_VIDEO_REG	0x040
> +static struct ccu_nkmp pll_video_4x_clk = {
> +	.enable		= BIT(27),
> +	.lock		= BIT(28),
> +	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 11),
> +	.p		= _SUNXI_CCU_DIV(1, 1), /* input divider */
> +	.common		= {
> +		.reg		= 0x040,
> +		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-video-4x", osc24M,
> +							   &ccu_nkmp_ops,
> +							   CLK_SET_RATE_GATE),
> +	},
> +};
> +
> +static const struct clk_hw *pll_video_4x_hws[] = {
> +	&pll_video_4x_clk.common.hw
> +};
> +static CLK_FIXED_FACTOR_HWS(pll_video_2x_clk, "pll-video-2x",
> +			    pll_video_4x_hws, 2, 1, CLK_SET_RATE_PARENT);
> +static CLK_FIXED_FACTOR_HWS(pll_video_1x_clk, "pll-video-1x",
> +			    pll_video_4x_hws, 4, 1, CLK_SET_RATE_PARENT);
> +
> +
> +/*
> + * For CSI PLLs, the output divider is described as "only for testing"
> + * in the user manual.
> + */
> +#define SUN8I_V853_PLL_CSI_REG		0x048
> +static struct ccu_nkmp pll_csi_4x_clk = {
> +	.enable		= BIT(27),
> +	.lock		= BIT(28),
> +	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 11),
> +	.p		= _SUNXI_CCU_DIV(1, 1), /* input divider */
> +	.common		= {
> +		.reg		= 0x048,
> +		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-csi-4x", osc24M,
> +							   &ccu_nkmp_ops,
> +							   CLK_SET_RATE_GATE),
> +	},
> +};
> +
> +static CLK_FIXED_FACTOR_HW(pll_csi_clk, "pll-csi",
> +			   &pll_csi_4x_clk.common.hw, 4, 1, CLK_SET_RATE_PARENT);
> +
> +
> +#define SUN8I_V853_PLL_AUDIO_REG	0x078
> +static struct ccu_sdm_setting pll_audio_div5_sdm_table[] = {
> +	{ .rate = 196608000, .pattern = 0xc001eb85, .m = 5, .n = 40 }, /* 24.576 */
> +	{ .rate = 67737600, .pattern = 0xc001288d, .m = 8, .n = 22 }, /* 22.5792 */
> +};
> +
> +static struct ccu_nm pll_audio_div5_clk = {
> +	.enable		= BIT(27),
> +	.lock           = BIT(28),
> +	.n              = _SUNXI_CCU_MULT(8, 8),
> +	.m              = _SUNXI_CCU_DIV(20, 3),
> +	.sdm            = _SUNXI_CCU_SDM(pll_audio_div5_sdm_table,
> +				    BIT(24), 0x0178, BIT(31)),
> +	.common         = {
> +		.reg            = 0x0078,
> +		.features       = CCU_FEATURE_SIGMA_DELTA_MOD,
> +		.hw.init        = CLK_HW_INIT_PARENTS_DATA("pll-audio-div5", osc24M,
> +							   &ccu_nm_ops,
> +							   CLK_SET_RATE_UNGATE),
> +	},
> +};
> +
> +static const struct clk_hw *pll_audio_div5_hws[] = {
> +	&pll_audio_div5_clk.common.hw
> +};
> +
> +static SUNXI_CCU_M_HWS(pll_audio_1x_clk, "pll-audio-1x", pll_audio_div5_hws,
> +		       0xe00, 0, 5, CLK_SET_RATE_PARENT);
> +
> +/* pll-audio-div2 and pll-audio-4x not used, because pll-audio-1x can cover 
> + * 22.5792M and 24.576M 
> + */
> +static SUNXI_CCU_M(pll_audio_div2_clk, "pll-audio-div2", "pll-audio",
> +		   0x078, 16, 3, 0);
> +static SUNXI_CCU_M(pll_audio_4x_clk, "pll-audio-4x", "pll-audio-div2",
> +		   0xe00, 5, 5, 0);
> +
> +/*
> + * For the NPU PLL, the output divider is described as "only for testing"
> + * in the user manual.
> + */
> +#define SUN8I_V853_PLL_NPU_REG		0x080
> +static struct ccu_nkmp pll_npu_4x_clk = {
> +	.enable		= BIT(27),
> +	.lock		= BIT(28),
> +	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 11),
> +	.p		= _SUNXI_CCU_DIV(1, 1), /* input divider */
> +	.common		= {
> +		.reg		= 0x080,
> +		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-npu-4x", osc24M,
> +							   &ccu_nkmp_ops,
> +							   CLK_SET_RATE_UNGATE),
> +	},
> +};
> +
> +/*
> + * The CPU gate is not modelled - it is in a separate register (0x504)
> + * and has a special key field. The clock must not be gated anyway by
> + * the kernel.
> + */
> +static const struct clk_parent_data cpu_parents[] = {
> +	{ .fw_name = "hosc" },
> +	{ .fw_name = "losc" },
> +	{ .fw_name = "iosc" },
> +	{ .hw = &pll_cpu_clk.common.hw },
> +	{ .hw = &pll_periph_600M_clk.hw },
> +	{ .hw = &pll_periph_800M_clk.common.hw },
> +};
> +
> +/*
> + * There is a P factor (PLL_OUT_EXT_DIVP[17:16]) in this register, but it is not modeled.
> + * The manual states that it should be used only, when the output clock is less than 288 MHz.
> + */
> +static SUNXI_CCU_MUX_DATA(cpu_clk, "cpu", cpu_parents,
> +			  0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
> +
> +static const struct clk_hw *cpu_hws[] = { &cpu_clk.common.hw };
> +
> +static SUNXI_CCU_M_HWS(cpu_axi_clk, "cpu-axi", cpu_hws,
> +		       0x500, 0, 2, 0);
> +static SUNXI_CCU_M_HWS(cpu_apb_clk, "cpu-apb", cpu_hws,
> +		       0x500, 8, 2, 0);
> +
> +static const struct clk_parent_data ahb_parents[] = {
> +	{ .fw_name = "hosc" },
> +	{ .fw_name = "losc" },
> +	{ .fw_name = "iosc" },
> +	{ .hw = &pll_periph_600M_clk.hw },
> +};
> +static SUNXI_CCU_MP_DATA_WITH_MUX(ahb_clk, "ahb", ahb_parents, 0x510,
> +				  0, 5,		/* M */
> +				  8, 2,		/* P */
> +				  24, 2,	/* mux */
> +				  0);
> +
> +static SUNXI_CCU_MP_DATA_WITH_MUX(apb0_clk, "apb0", ahb_parents, 0x520,
> +				  0, 5,		/* M */
> +				  8, 2,		/* P */
> +				  24, 2,	/* mux */
> +				  0);
> +
> +static SUNXI_CCU_MP_DATA_WITH_MUX(apb1_clk, "apb1", ahb_parents, 0x524,
> +				  0, 5,		/* M */
> +				  8, 2,		/* P */
> +				  24, 2,	/* mux */
> +				  0);
> +
> +static const struct clk_hw *ahb_hws[] = { &ahb_clk.common.hw };
> +static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw };
> +static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw };
> +
> +
> +static const struct clk_hw *de_g2d_parents[] = {
> +	&pll_periph_300M_clk.hw,
> +	&pll_video_1x_clk.hw,
> +};
> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_g2d_parents, 0x600,
> +				    0, 5,	/* M */
> +				    24, 1,	/* mux */
> +				    BIT(31),	/* gate */
> +				    CLK_SET_RATE_PARENT);
> +
> +static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", ahb_hws,
> +			  0x60c, BIT(0), 0);
> +
> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", de_g2d_parents, 0x630,
> +				    0, 5,	/* M */
> +				    24, 1,	/* mux */
> +				    BIT(31),	/* gate */
> +				    CLK_SET_RATE_PARENT);
> +
> +static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb_hws,
> +			  0x63c, BIT(0), 0);
> +
> +
> +static const struct clk_parent_data ce_parents[] = {
> +	{ .fw_name = "hosc" },

Where this come from? V853 manual v1.1 doesn't have it.

> +	{ .hw = &pll_periph_400M_clk.hw, },
> +	{ .hw = &pll_periph_300M_clk.hw, }
> +};
> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
> +				      0, 4,	/* M */
> +				      24, 3,	/* mux */
> +				      BIT(31),	/* gate */
> +				      CLK_SET_RATE_PARENT);

Set rate parent flag doesn't make sense on constant parents.

> +
> +static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", ahb_hws,
> +			  0x68c, BIT(0) | BIT(1), 0);
> +
> +static const struct clk_hw *ve_parents[] = {
> +	&pll_periph_300M_clk.hw,
> +	&pll_periph_400M_clk.hw,
> +	&pll_periph_480M_clk.common.hw,
> +	&pll_npu_4x_clk.common.hw,
> +	&pll_video_4x_clk.common.hw,
> +	&pll_csi_4x_clk.common.hw,
> +};
> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
> +				    0, 5,	/* M */
> +				    24, 3,	/* mux */
> +				    BIT(31),	/* gate */
> +				    0);

CLK_SET_RATE_PARENT flag? Cedrus driver set working clock at the beginning.

> +
> +static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", ahb_hws,
> +			  0x69c, BIT(0), 0);
> +
> +
> +static const struct clk_hw *npu_parents[] = {
> +	&pll_periph_480M_clk.common.hw,
> +	&pll_periph_600M_clk.hw,
> +	&pll_periph_800M_clk.common.hw,
> +	&pll_npu_4x_clk.common.hw,
> +};
> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0x6e0,
> +				    0, 5,	/* M */
> +				    24, 3,	/* mux */
> +				    BIT(31),	/* gate */
> +				    0);

I think CLK_SET_RATE_PARENT would also be beneficial here.

> +
> +static SUNXI_CCU_GATE_HWS(bus_npu_clk, "bus-npu", ahb_hws,
> +			  0x6ec, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", ahb_hws,
> +			  0x70c, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", ahb_hws,
> +			  0x71c, BIT(0), 0);
> +static SUNXI_CCU_GATE_HWS(bus_msgbox1_clk, "bus-msgbox1", ahb_hws,
> +			  0x71c, BIT(1), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", ahb_hws,
> +			  0x72c, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", ahb_hws,
> +			  0x73c, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_DATA(avs_clk, "avs", osc24M,
> +			   0x740, BIT(31), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", ahb_hws,
> +			  0x78c, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_pwm_clk, "bus-pwm", apb0_hws,
> +			  0x7ac, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", ahb_hws,
> +			  0x7bc, BIT(0), 0);
> +
> +static const struct clk_hw *dram_parents[] = {
> +	&pll_ddr_clk.common.hw,
> +	&pll_periph_2x_clk.common.hw,
> +	&pll_periph_800M_clk.common.hw,
> +};
> +static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dram_clk, "dram", dram_parents, 0x800,
> +				     0, 5,	/* M */
> +				     8, 2,	/* P */
> +				     24, 3,	/* mux */
> +				     BIT(31), CLK_IS_CRITICAL);

This clock needs update field to be set to actually apply configuration. So
same comment as on A523 clock version, this needs new flag to be introduced
for such case.

> +
> +static CLK_FIXED_FACTOR_HW(mbus_clk, "mbus",
> +			   &dram_clk.common.hw, 4, 1, 0);
> +
> +static const struct clk_hw *mbus_hws[] = { &mbus_clk.hw };
> +
> +static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
> +			  0x804, BIT(0), 0);
> +static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws,
> +			  0x804, BIT(1), 0);
> +static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws,
> +			  0x804, BIT(2), 0);
> +static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws,
> +			  0x804, BIT(8), 0);
> +static SUNXI_CCU_GATE_HWS(mbus_isp_clk, "mbus-isp", mbus_hws,
> +			  0x804, BIT(9), 0);
> +static SUNXI_CCU_GATE_HWS(mbus_g2d_clk, "mbus-g2d", mbus_hws,
> +			  0x804, BIT(10), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", ahb_hws,
> +			  0x80c, BIT(0), CLK_IS_CRITICAL);
> +
> +
> +static const struct clk_parent_data mmc0_mmc1_parents[] = {
> +	{ .fw_name = "hosc" },
> +	{ .hw = &pll_periph_400M_clk.hw, },
> +	{ .hw = &pll_periph_300M_clk.hw, },
> +};

Just mmc_parents.

> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830,
> +				       0, 4,	/* M */
> +				       8, 2,	/* P */
> +				       24, 3,	/* mux */
> +				       BIT(31),	/* gate */
> +				       0);
> +
> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834,
> +				       0, 4,	/* M */
> +				       8, 2,	/* P */
> +				       24, 3,	/* mux */
> +				       BIT(31),	/* gate */
> +				       0);
> +
> +static const struct clk_parent_data mmc2_parents[] = {
> +	{ .fw_name = "hosc" },
> +	{ .hw = &pll_periph_600M_clk.hw, },
> +	{ .hw = &pll_periph_400M_clk.hw, },
> +};
> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838,
> +				       0, 4,	/* M */
> +				       8, 2,	/* P */
> +				       24, 3,	/* mux */
> +				       BIT(31),	/* gate */
> +				       0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", ahb_hws,
> +			  0x84c, BIT(0), 0);
> +static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", ahb_hws,
> +			  0x84c, BIT(1), 0);
> +static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", ahb_hws,
> +			  0x84c, BIT(2), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws,
> +			  0x90c, BIT(0), 0);
> +static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws,
> +			  0x90c, BIT(1), 0);
> +static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws,
> +			  0x90c, BIT(2), 0);
> +static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws,
> +			  0x90c, BIT(3), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws,
> +			  0x91c, BIT(0), 0);
> +static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws,
> +			  0x91c, BIT(1), 0);
> +static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws,
> +			  0x91c, BIT(2), 0);
> +static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws,
> +			  0x91c, BIT(3), 0);
> +static SUNXI_CCU_GATE_HWS(bus_i2c4_clk, "bus-i2c4", apb1_hws,
> +			  0x91c, BIT(4), 0);
> +
> +static const struct clk_parent_data spi_parents[] = {
> +	{ .fw_name = "hosc" },
> +	{ .hw = &pll_periph_300M_clk.hw, },
> +	{ .hw = &pll_periph_200M_clk.hw, },
> +};
> +
> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
> +				       0, 4,	/* M */
> +				       8, 2,	/* P */
> +				       24, 3,	/* mux */
> +				       BIT(31),	/* gate */
> +				       0);
> +
> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
> +				       0, 4,	/* M */
> +				       8, 2,	/* P */
> +				       24, 3,	/* mux */
> +				       BIT(31),	/* gate */
> +				       0);
> +
> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi2_clk, "spi2", spi_parents, 0x948,
> +				       0, 4,	/* M */
> +				       8, 2,	/* P */
> +				       24, 3,	/* mux */
> +				       BIT(31),	/* gate */
> +				       0);
> +
> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi3_clk, "spi3", spi_parents, 0x94c,
> +				       0, 4,	/* M */
> +				       8, 2,	/* P */
> +				       24, 3,	/* mux */
> +				       BIT(31),	/* gate */
> +				       0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", ahb_hws,
> +			  0x96c, BIT(0), 0);
> +static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", ahb_hws,
> +			  0x96c, BIT(1), 0);
> +static SUNXI_CCU_GATE_HWS(bus_spi2_clk, "bus-spi2", ahb_hws,
> +			  0x96c, BIT(2), 0);
> +static SUNXI_CCU_GATE_HWS(bus_spi3_clk, "bus-spi3", ahb_hws,
> +			  0x96c, BIT(3), 0);
> +
> +
> +static const struct clk_parent_data spif_parents[] = {
> +	{ .fw_name = "hosc" },
> +	{ .hw = &pll_periph_400M_clk.hw, },
> +	{ .hw = &pll_periph_300M_clk.hw, },
> +};
> +
> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(spif_clk, "spif", spif_parents, 0x0950,
> +				      0, 4,	/* M */
> +				      24, 3,	/* mux */
> +				      BIT(31),	/* gate */
> +				      CLK_SET_RATE_PARENT);

This is MP clock, P being at 9:8.

> +
> +static SUNXI_CCU_GATE_HWS(bus_spif_clk, "bus-spif", ahb_hws,
> +			  0x096c, BIT(4), 0);
> +
> +
> +static const struct clk_hw *pll_periph_150M_hws[] = { &pll_periph_150M_clk.hw };
> +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25M_clk, "emac-25M", pll_periph_150M_hws,
> +				      0x970, BIT(31) | BIT(30), 6, 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_emac_clk, "bus-emac", ahb_hws,
> +			  0x97c, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_gpadc_clk, "bus-gpadc", apb0_hws,
> +			  0x9ec, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", ahb_hws,
> +			  0x9fc, BIT(0), 0);
> +
> +
> +static const struct clk_hw *audio_parents[] = {
> +	&pll_audio_1x_clk.common.hw,
> +	&pll_audio_4x_clk.common.hw,
> +};
> +
> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2s0_clk, "i2s0", audio_parents, 0xa10,
> +				    0, 4,	/* M */
> +				    24, 1,	/* mux */
> +				    BIT(31),	/* gate */
> +				    CLK_SET_RATE_PARENT);
> +
> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2s1_clk, "i2s1", audio_parents, 0xa14,
> +				    0, 4,	/* M */
> +				    24, 1,	/* mux */
> +				    BIT(31),	/* gate */
> +				    CLK_SET_RATE_PARENT);
> +
> +static SUNXI_CCU_GATE_HWS(bus_i2s0_clk, "bus-i2s0", ahb_hws,
> +			  0xa20, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_i2s1_clk, "bus-i2s1", ahb_hws,
> +			  0xa20, BIT(1), 0);
> +
> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dmic_clk, "dmic", audio_parents, 0xa40,
> +				    0, 4,	/* M */
> +				    24, 1,	/* mux */
> +				    BIT(31),	/* gate */
> +				    CLK_SET_RATE_PARENT);
> +
> +static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", ahb_hws,
> +			  0xa4c, BIT(0), 0);
> +
> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(audio_codec_dac_clk, "audio-codec-dac", 
> +				    audio_parents, 0xa50,
> +				    0, 4,	/* M */
> +				    24, 1,	/* mux */
> +				    BIT(31),	/* gate */
> +				    CLK_SET_RATE_PARENT);
> +
> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(audio_codec_adc_clk, "audio-codec-adc", 
> +				    audio_parents, 0xa54,
> +				    0, 4,	/* M */
> +				    24, 1,	/* mux */
> +				    BIT(31),	/* gate */
> +				    CLK_SET_RATE_PARENT);
> +
> +static SUNXI_CCU_GATE_HWS(bus_audio_codec_clk, "bus-audio-codec", apb0_hws,
> +			  0xa5c, BIT(0), 0);
> +
> +/*
> + * There are OHCI 12M clock source selection bits for the USB 2.0 port.
> + * We will force them to 0 (12M divided from 48M).
> + */
> +static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
> +
> +#define SUN8I_V853_USB_CLK_REG		0xa70
> +
> +static SUNXI_CCU_GATE(usb_ohci_clk, "usb", "osc12M", 0x0a70, BIT(31), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_ohci_clk, "bus-ohci", ahb_hws, 0xa8c, BIT(0), 0);
> +static SUNXI_CCU_GATE_HWS(bus_ehci_clk, "bus-ehci", ahb_hws, 0xa8c, BIT(4), 0);
> +static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", ahb_hws, 0xa8c, BIT(8), 0);
> +
> +static SUNXI_CCU_GATE_HWS(bus_dpss_top_clk, "bus-dpss-top", ahb_hws,
> +			  0xabc, BIT(0), 0);
> +
> +
> +static const struct clk_parent_data mipi_dsi_parents[] = {
> +	{ .fw_name = "hosc" },
> +	{ .hw = &pll_periph_200M_clk.hw },
> +	{ .hw = &pll_periph_150M_clk.hw },
> +};
> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", mipi_dsi_parents, 
> +				      0xb24,
> +				      0, 4,	/* M */
> +				      24, 3,	/* mux */
> +				      BIT(31),	/* gate */
> +				      CLK_SET_RATE_PARENT);

CLK_SET_RATE_PARENT doesn't do anything for constant clocks.

Best regards,
Jernej

> +
> +static SUNXI_CCU_GATE_HWS(bus_mipi_dsi_clk, "bus-mipi-dsi", ahb_hws,
> +			  0xb4c, BIT(0), 0);
> +
> +
> +static const struct clk_hw *tcon_lcd_parents[] = {
> +	&pll_video_4x_clk.common.hw,
> +	&pll_periph_2x_clk.common.hw,
> +	&pll_csi_4x_clk.common.hw,
> +};
> +static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_lcd_clk, "tcon-lcd", tcon_lcd_parents, 
> +				     0xb60,
> +				     0, 4,	/* M */
> +				     8, 2,	/* P */
> +				     24, 3,	/* mux */
> +				     BIT(31),	/* gate */
> +				     CLK_SET_RATE_PARENT);
> +
> +static SUNXI_CCU_GATE_HWS(bus_tcon_lcd_clk, "bus-tcon-lcd", ahb_hws,
> +			  0xb7c, BIT(0), 0);
> +
> +
> +static const struct clk_hw *csi_top_parents[] = {
> +	&pll_periph_300M_clk.hw,
> +	&pll_periph_400M_clk.hw,
> +	&pll_video_4x_clk.common.hw,
> +	&pll_csi_4x_clk.common.hw,
> +};
> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents, 0xc04,
> +				    0, 5,	/* M */
> +				    24, 3,	/* mux */
> +				    BIT(31),	/* gate */
> +				    0);
> +
> +
> +static const struct clk_parent_data csi_mclk_parents[] = {
> +	{ .fw_name = "hosc" },
> +	{ .hw = &pll_csi_4x_clk.common.hw },
> +	{ .hw = &pll_video_4x_clk.common.hw },
> +	{ .hw = &pll_periph_2x_clk.common.hw },
> +};
> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk0_clk, "csi-mclk0", csi_mclk_parents, 
> +				      0xc08,
> +				      0, 5,	/* M */
> +				      24, 3,	/* mux */
> +				      BIT(31),	/* gate */
> +				      0);
> +
> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk1_clk, "csi-mclk1", csi_mclk_parents, 
> +				      0xc0c,
> +				      0, 5,	/* M */
> +				      24, 3,	/* mux */
> +				      BIT(31),	/* gate */
> +				      0);
> +
> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk2_clk, "csi-mclk2", csi_mclk_parents, 
> +				      0xc10,
> +				      0, 5,	/* M */
> +				      24, 3,	/* mux */
> +				      BIT(31),	/* gate */
> +				      0);

All CSI mclks should be MP type.

> +
> +static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", ahb_hws,
> +			  0xc2c, BIT(0), 0);
> +
> +
> +static SUNXI_CCU_GATE_HWS(bus_wiegand_clk, "bus-wiegand", ahb_hws,
> +			  0xc7c, BIT(0), 0);
> +
> +
> +static const struct clk_parent_data riscv_parents[] = {
> +	{ .fw_name = "hosc" },
> +	{ .fw_name = "losc" },
> +	{ .fw_name = "iosc" },
> +	{ .hw = &pll_periph_600M_clk.hw },
> +	{ .hw = &pll_periph_480M_clk.common.hw },
> +	{ .hw = &pll_cpu_clk.common.hw },
> +};
> +static SUNXI_CCU_M_DATA_WITH_MUX(riscv_clk, "riscv-cpu", riscv_parents, 0xd00,
> +				 0, 5,	/* M */
> +				 24, 3,	/* mux */
> +				 CLK_SET_RATE_PARENT);
> +
> +/* The riscv-axi clk must be divided by at least 2. */
> +static struct clk_div_table riscv_axi_table[] = {
> +	{ .val = 1, .div = 2 },
> +	{ .val = 2, .div = 3 },
> +	{ .val = 3, .div = 4 },
> +	{ /* Sentinel */ }
> +};
> +static SUNXI_CCU_DIV_TABLE_HW(riscv_axi_clk, "riscv-axi", &riscv_clk.common.hw,
> +			      0xd00, 8, 2, riscv_axi_table, 0);
> +
> +static SUNXI_CCU_GATE_HWS_WITH_KEY(riscv_core_gate, "riscv-core-gate", ahb_hws,
> +				   0xd04, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_HWS(riscv_cfg_gate, "riscv-cfg-gate", ahb_hws,
> +			  0xd0c, BIT(0), 0);
> +
> +
> +static const struct clk_hw *pll_periph_160M_hws[] = {
> +	&pll_periph_160M_clk.hw,
> +};
> +
> +static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
> +			   0xf30, BIT(0), 0);
> +static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
> +				       0xf30, BIT(1), 2, 0);
> +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph_160M_hws,
> +				      0xf30, BIT(2), 10, 0);
> +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph_150M_hws,
> +				      0xf30, BIT(3), 6, 0);
> +
> +
> +/* This clock has a second divider that is not modelled and forced to 0. */
> +#define SUN8I_V853_FANOUT_27M_REG	0xf34
> +static const struct clk_hw *fanout_27M_parents[] = {
> +	&pll_video_1x_clk.hw,
> +	&pll_csi_clk.hw,
> +	&pll_periph_300M_clk.hw,
> +};
> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(fanout_27M_clk, "fanout-27M", 
> +				    fanout_27M_parents, 0xf34,
> +				    0, 5,	/* M */
> +				    24, 2,	/* mux */
> +				    BIT(31),	/* gate */
> +				    0);
> +static SUNXI_CCU_M_HWS_WITH_GATE(fanout_pclk_clk, "fanout-pclk", apb0_hws, 0xf38,
> +				 0, 5,		/* M */
> +				 BIT(31),	/* gate */
> +				 0);
> +
> +static const struct clk_parent_data fanout_parents[] = {
> +	{ .fw_name = "losc" },
> +	{ .hw = &fanout_12M_clk.common.hw },
> +	{ .hw = &fanout_16M_clk.common.hw },
> +	{ .hw = &fanout_24M_clk.common.hw },
> +	{ .hw = &fanout_25M_clk.common.hw },
> +	{ .hw = &fanout_27M_clk.common.hw },
> +	{ .hw = &fanout_pclk_clk.common.hw },
> +};
> +
> +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 0xf3c,
> +				    0, 3,	/* mux */
> +				    BIT(21),	/* gate */
> +				    0);
> +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 0xf3c,
> +				    3, 3,	/* mux */
> +				    BIT(22),	/* gate */
> +				    0);
> +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 0xf3c,
> +				    6, 3,	/* mux */
> +				    BIT(23),	/* gate */
> +				    0);
> +
> +
> +static struct ccu_common *sun8i_v853_ccu_clks[] = {
> +	&pll_cpu_clk.common,
> +	&pll_ddr_clk.common,
> +	&pll_periph_4x_clk.common,
> +	&pll_periph_2x_clk.common,
> +	&pll_periph_800M_clk.common,
> +	&pll_periph_480M_clk.common,
> +	&pll_video_4x_clk.common,
> +	&pll_csi_4x_clk.common,
> +	&pll_audio_div2_clk.common,
> +	&pll_audio_div5_clk.common,
> +	&pll_audio_4x_clk.common,
> +	&pll_audio_1x_clk.common,
> +	&pll_npu_4x_clk.common,
> +	&cpu_clk.common,
> +	&cpu_axi_clk.common,
> +	&cpu_apb_clk.common,
> +	&ahb_clk.common,
> +	&apb0_clk.common,
> +	&apb1_clk.common,
> +	&de_clk.common,
> +	&bus_de_clk.common,
> +	&g2d_clk.common,
> +	&bus_g2d_clk.common,
> +	&ce_clk.common,
> +	&bus_ce_clk.common,
> +	&ve_clk.common,
> +	&bus_ve_clk.common,
> +	&npu_clk.common,
> +	&bus_npu_clk.common,
> +	&bus_dma_clk.common,
> +	&bus_msgbox0_clk.common,
> +	&bus_msgbox1_clk.common,
> +	&bus_spinlock_clk.common,
> +	&bus_hstimer_clk.common,
> +	&avs_clk.common,
> +	&bus_dbg_clk.common,
> +	&bus_pwm_clk.common,
> +	&bus_iommu_clk.common,
> +	&dram_clk.common,
> +	&mbus_dma_clk.common,
> +	&mbus_ve_clk.common,
> +	&mbus_ce_clk.common,
> +	&mbus_csi_clk.common,
> +	&mbus_isp_clk.common,
> +	&mbus_g2d_clk.common,
> +	&bus_dram_clk.common,
> +	&mmc0_clk.common,
> +	&mmc1_clk.common,
> +	&mmc2_clk.common,
> +	&bus_mmc0_clk.common,
> +	&bus_mmc1_clk.common,
> +	&bus_mmc2_clk.common,
> +	&bus_uart0_clk.common,
> +	&bus_uart1_clk.common,
> +	&bus_uart2_clk.common,
> +	&bus_uart3_clk.common,
> +	&bus_i2c0_clk.common,
> +	&bus_i2c1_clk.common,
> +	&bus_i2c2_clk.common,
> +	&bus_i2c3_clk.common,
> +	&bus_i2c4_clk.common,
> +	&spi0_clk.common,
> +	&spi1_clk.common,
> +	&spi2_clk.common,
> +	&spi3_clk.common,
> +	&bus_spi0_clk.common,
> +	&bus_spi1_clk.common,
> +	&bus_spi2_clk.common,
> +	&bus_spi3_clk.common,
> +	&spif_clk.common,
> +	&bus_spif_clk.common,
> +	&emac_25M_clk.common,
> +	&bus_emac_clk.common,
> +	&bus_gpadc_clk.common,
> +	&bus_ths_clk.common,
> +	&usb_ohci_clk.common,
> +	&bus_ohci_clk.common,
> +	&bus_ehci_clk.common,
> +	&bus_otg_clk.common,
> +	&i2s0_clk.common,
> +	&i2s1_clk.common,
> +	&bus_i2s0_clk.common,
> +	&bus_i2s1_clk.common,
> +	&dmic_clk.common,
> +	&bus_dmic_clk.common,
> +	&audio_codec_dac_clk.common,
> +	&audio_codec_adc_clk.common,
> +	&bus_audio_codec_clk.common,
> +	&bus_dpss_top_clk.common,
> +	&mipi_dsi_clk.common,
> +	&bus_mipi_dsi_clk.common,
> +	&tcon_lcd_clk.common,
> +	&bus_tcon_lcd_clk.common,
> +	&csi_top_clk.common,
> +	&csi_mclk0_clk.common,
> +	&csi_mclk1_clk.common,
> +	&csi_mclk2_clk.common,
> +	&bus_csi_clk.common,
> +	&bus_wiegand_clk.common,
> +	&riscv_clk.common,
> +	&riscv_axi_clk.common,
> +	&riscv_core_gate.common,
> +	&riscv_cfg_gate.common,
> +	&fanout_24M_clk.common,
> +	&fanout_12M_clk.common,
> +	&fanout_16M_clk.common,
> +	&fanout_25M_clk.common,
> +	&fanout_27M_clk.common,
> +	&fanout_pclk_clk.common,
> +	&fanout0_clk.common,
> +	&fanout1_clk.common,
> +	&fanout2_clk.common,
> +};
> +
> +static struct clk_hw_onecell_data sun8i_v853_hw_clks = {
> +	.num	= CLK_NUMBER,
> +	.hws	= {
> +		[CLK_OSC12M]            = &osc12M_clk.hw,
> +		[CLK_PLL_CPU]		= &pll_cpu_clk.common.hw,
> +		[CLK_PLL_DDR]		= &pll_ddr_clk.common.hw,
> +		[CLK_PLL_PERIPH_4X]	= &pll_periph_4x_clk.common.hw,
> +		[CLK_PLL_PERIPH_2X]	= &pll_periph_2x_clk.common.hw,
> +		[CLK_PLL_PERIPH_800M]	= &pll_periph_800M_clk.common.hw,
> +		[CLK_PLL_PERIPH_480M]	= &pll_periph_480M_clk.common.hw,
> +		[CLK_PLL_PERIPH_600M]	= &pll_periph_600M_clk.hw,
> +		[CLK_PLL_PERIPH_400M]	= &pll_periph_400M_clk.hw,
> +		[CLK_PLL_PERIPH_300M]	= &pll_periph_300M_clk.hw,
> +		[CLK_PLL_PERIPH_200M]	= &pll_periph_200M_clk.hw,
> +		[CLK_PLL_PERIPH_160M]	= &pll_periph_160M_clk.hw,
> +		[CLK_PLL_PERIPH_150M]	= &pll_periph_150M_clk.hw,
> +		[CLK_PLL_VIDEO_4X]	= &pll_video_4x_clk.common.hw,
> +		[CLK_PLL_VIDEO_2X]	= &pll_video_2x_clk.hw,
> +		[CLK_PLL_VIDEO_1X]	= &pll_video_1x_clk.hw,
> +		[CLK_PLL_CSI_4X]	= &pll_csi_4x_clk.common.hw,
> +		[CLK_PLL_AUDIO_DIV2]	= &pll_audio_div2_clk.common.hw,
> +		[CLK_PLL_AUDIO_DIV5]	= &pll_audio_div5_clk.common.hw,
> +		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.common.hw,
> +		[CLK_PLL_AUDIO_1X]	= &pll_audio_1x_clk.common.hw,
> +		[CLK_PLL_NPU_4X]	= &pll_npu_4x_clk.common.hw,
> +		[CLK_CPU]		= &cpu_clk.common.hw,
> +		[CLK_CPU_AXI]		= &cpu_axi_clk.common.hw,
> +		[CLK_CPU_APB]		= &cpu_apb_clk.common.hw,
> +		[CLK_AHB]		= &ahb_clk.common.hw,
> +		[CLK_APB0]		= &apb0_clk.common.hw,
> +		[CLK_APB1]		= &apb1_clk.common.hw,
> +		[CLK_MBUS]		= &mbus_clk.hw,
> +		[CLK_DE]		= &de_clk.common.hw,
> +		[CLK_BUS_DE]		= &bus_de_clk.common.hw,
> +		[CLK_G2D]		= &g2d_clk.common.hw,
> +		[CLK_BUS_G2D]		= &bus_g2d_clk.common.hw,
> +		[CLK_CE]		= &ce_clk.common.hw,
> +		[CLK_BUS_CE]		= &bus_ce_clk.common.hw,
> +		[CLK_VE]		= &ve_clk.common.hw,
> +		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
> +		[CLK_NPU]		= &npu_clk.common.hw,
> +		[CLK_BUS_NPU]		= &bus_npu_clk.common.hw,
> +		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
> +		[CLK_BUS_MSGBOX0]	= &bus_msgbox0_clk.common.hw,
> +		[CLK_BUS_MSGBOX1]	= &bus_msgbox1_clk.common.hw,
> +		[CLK_BUS_SPINLOCK]	= &bus_spinlock_clk.common.hw,
> +		[CLK_BUS_HSTIMER]	= &bus_hstimer_clk.common.hw,
> +		[CLK_AVS]		= &avs_clk.common.hw,
> +		[CLK_BUS_DBG]		= &bus_dbg_clk.common.hw,
> +		[CLK_BUS_PWM]		= &bus_pwm_clk.common.hw,
> +		[CLK_BUS_IOMMU]		= &bus_iommu_clk.common.hw,
> +		[CLK_DRAM]		= &dram_clk.common.hw,
> +		[CLK_MBUS_DMA]		= &mbus_dma_clk.common.hw,
> +		[CLK_MBUS_VE]		= &mbus_ve_clk.common.hw,
> +		[CLK_MBUS_CE]		= &mbus_ce_clk.common.hw,
> +		[CLK_MBUS_CSI]		= &mbus_csi_clk.common.hw,
> +		[CLK_MBUS_ISP]		= &mbus_isp_clk.common.hw,
> +		[CLK_MBUS_G2D]		= &mbus_g2d_clk.common.hw,
> +		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
> +		[CLK_MMC0]		= &mmc0_clk.common.hw,
> +		[CLK_MMC1]		= &mmc1_clk.common.hw,
> +		[CLK_MMC2]		= &mmc2_clk.common.hw,
> +		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
> +		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
> +		[CLK_BUS_MMC2]		= &bus_mmc2_clk.common.hw,
> +		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
> +		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
> +		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
> +		[CLK_BUS_UART3]		= &bus_uart3_clk.common.hw,
> +		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
> +		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
> +		[CLK_BUS_I2C2]		= &bus_i2c2_clk.common.hw,
> +		[CLK_BUS_I2C3]		= &bus_i2c3_clk.common.hw,
> +		[CLK_BUS_I2C4]		= &bus_i2c4_clk.common.hw,
> +		[CLK_SPI0]		= &spi0_clk.common.hw,
> +		[CLK_SPI1]		= &spi1_clk.common.hw,
> +		[CLK_SPI2]		= &spi2_clk.common.hw,
> +		[CLK_SPI3]		= &spi3_clk.common.hw,
> +		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
> +		[CLK_BUS_SPI1]		= &bus_spi1_clk.common.hw,
> +		[CLK_BUS_SPI2]		= &bus_spi2_clk.common.hw,
> +		[CLK_BUS_SPI3]		= &bus_spi3_clk.common.hw,
> +		[CLK_SPIF]		= &spif_clk.common.hw,
> +		[CLK_BUS_SPIF]		= &bus_spif_clk.common.hw,
> +		[CLK_EMAC_25M]		= &emac_25M_clk.common.hw,
> +		[CLK_BUS_EMAC]		= &bus_emac_clk.common.hw,
> +		[CLK_BUS_GPADC]		= &bus_gpadc_clk.common.hw,
> +		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
> +		[CLK_I2S0]		= &i2s0_clk.common.hw,
> +		[CLK_I2S1]		= &i2s1_clk.common.hw,
> +		[CLK_BUS_I2S0]		= &bus_i2s0_clk.common.hw,
> +		[CLK_BUS_I2S1]		= &bus_i2s1_clk.common.hw,
> +		[CLK_DMIC]		= &dmic_clk.common.hw,
> +		[CLK_BUS_DMIC]		= &bus_dmic_clk.common.hw,
> +		[CLK_AUDIO_CODEC_DAC]	= &audio_codec_dac_clk.common.hw,
> +		[CLK_AUDIO_CODEC_ADC]	= &audio_codec_adc_clk.common.hw,
> +		[CLK_BUS_AUDIO_CODEC]	= &bus_audio_codec_clk.common.hw,
> +		[CLK_USB_OHCI]		= &usb_ohci_clk.common.hw,
> +		[CLK_BUS_OHCI]		= &bus_ohci_clk.common.hw,
> +		[CLK_BUS_EHCI]		= &bus_ehci_clk.common.hw,
> +		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
> +		[CLK_BUS_DPSS_TOP]	= &bus_dpss_top_clk.common.hw,
> +		[CLK_MIPI_DSI]		= &mipi_dsi_clk.common.hw,
> +		[CLK_BUS_MIPI_DSI]	= &bus_mipi_dsi_clk.common.hw,
> +		[CLK_TCON_LCD]		= &tcon_lcd_clk.common.hw,
> +		[CLK_BUS_TCON_LCD]	= &bus_tcon_lcd_clk.common.hw,
> +		[CLK_CSI_TOP]		= &csi_top_clk.common.hw,
> +		[CLK_CSI_MCLK0]		= &csi_mclk0_clk.common.hw,
> +		[CLK_CSI_MCLK1]		= &csi_mclk1_clk.common.hw,
> +		[CLK_CSI_MCLK2]		= &csi_mclk2_clk.common.hw,
> +		[CLK_BUS_CSI]		= &bus_csi_clk.common.hw,
> +		[CLK_BUS_WIEGAND]	= &bus_wiegand_clk.common.hw,
> +		[CLK_RISCV]		= &riscv_clk.common.hw,
> +		[CLK_RISCV_AXI]		= &riscv_axi_clk.common.hw,
> +		[CLK_RISCV_CORE_GATE]   = &riscv_core_gate.common.hw,
> +		[CLK_RISCV_CFG_GATE]    = &riscv_cfg_gate.common.hw,
> +		[CLK_FANOUT_24M]	= &fanout_24M_clk.common.hw,
> +		[CLK_FANOUT_16M]	= &fanout_16M_clk.common.hw,
> +		[CLK_FANOUT_12M]	= &fanout_12M_clk.common.hw,
> +		[CLK_FANOUT_25M]	= &fanout_25M_clk.common.hw,
> +		[CLK_FANOUT_27M]	= &fanout_27M_clk.common.hw,
> +		[CLK_FANOUT_PCLK]	= &fanout_pclk_clk.common.hw,
> +		[CLK_FANOUT0]		= &fanout0_clk.common.hw,
> +		[CLK_FANOUT1]		= &fanout1_clk.common.hw,
> +		[CLK_FANOUT2]		= &fanout2_clk.common.hw,
> +	},
> +};
> +
> +static struct ccu_reset_map sun8i_v853_ccu_resets[] = {
> +	[RST_MBUS]		= { 0x540, BIT(30) },
> +	[RST_BUS_DE]		= { 0x60c, BIT(16) },
> +	[RST_BUS_G2D]		= { 0x63c, BIT(16) },
> +	[RST_BUS_CE]		= { 0x68c, BIT(16) | BIT(17)},
> +	[RST_BUS_VE]		= { 0x69c, BIT(16) },
> +	[RST_BUS_NPU]		= { 0x6ec, BIT(16) },
> +	[RST_BUS_DMA]		= { 0x70c, BIT(16) },
> +	[RST_BUS_MSGBOX0]	= { 0x71c, BIT(16) },
> +	[RST_BUS_MSGBOX1]	= { 0x71c, BIT(17) },
> +	[RST_BUS_SPINLOCK]	= { 0x72c, BIT(16) },
> +	[RST_BUS_HSTIMER]	= { 0x73c, BIT(16) },
> +	[RST_BUS_DBG]		= { 0x78c, BIT(16) },
> +	[RST_BUS_PWM]		= { 0x7ac, BIT(16) },
> +	[RST_BUS_DRAM]		= { 0x80c, BIT(16) },
> +	[RST_BUS_MMC0]		= { 0x84c, BIT(16) },
> +	[RST_BUS_MMC1]		= { 0x84c, BIT(17) },
> +	[RST_BUS_MMC2]		= { 0x84c, BIT(18) },
> +	[RST_BUS_UART0]		= { 0x90c, BIT(16) },
> +	[RST_BUS_UART1]		= { 0x90c, BIT(17) },
> +	[RST_BUS_UART2]		= { 0x90c, BIT(18) },
> +	[RST_BUS_UART3]		= { 0x90c, BIT(19) },
> +	[RST_BUS_I2C0]		= { 0x91c, BIT(16) },
> +	[RST_BUS_I2C1]		= { 0x91c, BIT(17) },
> +	[RST_BUS_I2C2]		= { 0x91c, BIT(18) },
> +	[RST_BUS_I2C3]		= { 0x91c, BIT(19) },
> +	[RST_BUS_I2C4]		= { 0x91c, BIT(20) },
> +	[RST_BUS_SPI0]		= { 0x96c, BIT(16) },
> +	[RST_BUS_SPI1]		= { 0x96c, BIT(17) },
> +	[RST_BUS_SPI2]		= { 0x96c, BIT(18) },
> +	[RST_BUS_SPI3]		= { 0x96c, BIT(19) },
> +	[RST_BUS_SPIF]		= { 0x96c, BIT(20) },
> +	[RST_BUS_EMAC]		= { 0x97c, BIT(16) },
> +	[RST_BUS_GPADC]		= { 0x9ec, BIT(16) },
> +	[RST_BUS_THS]		= { 0x9fc, BIT(16) },
> +	[RST_BUS_I2S0]		= { 0xa20, BIT(16) },
> +	[RST_BUS_I2S1]		= { 0xa20, BIT(17) },
> +	[RST_BUS_DMIC]		= { 0xa4c, BIT(16) },
> +	[RST_BUS_AUDIO_CODEC]	= { 0xa5c, BIT(16) },
> +	[RST_USB_PHY]		= { 0xa70, BIT(30) },
> +	[RST_BUS_OHCI]		= { 0xa8c, BIT(16) },
> +	[RST_BUS_EHCI]		= { 0xa8c, BIT(20) },
> +	[RST_BUS_OTG]		= { 0xa8c, BIT(24) },
> +	[RST_BUS_DPSS_TOP]	= { 0xabc, BIT(16) },
> +	[RST_BUS_MIPI_DSI]	= { 0xb4c, BIT(16) },
> +	[RST_BUS_TCON_LCD]	= { 0xb7c, BIT(16) },
> +	[RST_BUS_CSI]		= { 0xc2c, BIT(16) },
> +	[RST_BUS_WIEGAND]	= { 0xc7c, BIT(16) },
> +	[RST_RISCV_SYS_APB]	= { 0xd04, BIT(2), CCU_FEATURE_KEY_FIELD },
> +	[RST_RISCV_SOFT]	= { 0xd04, BIT(1), CCU_FEATURE_KEY_FIELD },
> +	[RST_RISCV_CFG]		= { 0xd0c, BIT(16) }
> +};
> +
> +static const struct sunxi_ccu_desc sun8i_v853_ccu_desc = {
> +	.ccu_clks	= sun8i_v853_ccu_clks,
> +	.num_ccu_clks	= ARRAY_SIZE(sun8i_v853_ccu_clks),
> +
> +	.hw_clks	= &sun8i_v853_hw_clks,
> +
> +	.resets		= sun8i_v853_ccu_resets,
> +	.num_resets	= ARRAY_SIZE(sun8i_v853_ccu_resets),
> +};
> +
> +static const u32 pll_regs[] = {
> +	SUN8I_V853_PLL_CPU_REG,
> +	SUN8I_V853_PLL_DDR_REG,
> +	SUN8I_V853_PLL_PERIPH_REG,
> +	SUN8I_V853_PLL_VIDEO_REG,
> +	SUN8I_V853_PLL_CSI_REG,
> +	SUN8I_V853_PLL_AUDIO_REG,
> +	SUN8I_V853_PLL_NPU_REG,
> +};
> +
> +static int sun8i_v853_ccu_probe(struct platform_device *pdev)
> +{
> +	void __iomem *reg;
> +	u32 val;
> +	int i, ret;
> +
> +	reg = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(reg))
> +		return PTR_ERR(reg);
> +
> +	/* Enable the enable, LDO, and lock bits on all PLLs. */
> +	for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
> +		val = readl(reg + pll_regs[i]);
> +		val |= BIT(31) | BIT(30) | BIT(29);
> +		writel(val, reg + pll_regs[i]);
> +	}
> +
> +	/* Force PLL_CPU factor M to 0. */
> +	val = readl(reg + SUN8I_V853_PLL_CPU_REG);
> +	val &= ~GENMASK(1, 0);
> +	writel(val, reg + SUN8I_V853_PLL_CPU_REG);
> +
> +	/*
> +	 * Force OHCI 12M clock source to 00 (12MHz divided from 48MHz)
> +	 *
> +	 * This clock mux is still mysterious, and the code just enforces
> +	 * it to have a valid clock parent.
> +	 */
> +	val = readl(reg + SUN8I_V853_USB_CLK_REG);
> +	val &= ~GENMASK(25, 24);
> +	writel(val, reg + SUN8I_V853_USB_CLK_REG);
> +
> +	/* Force fanout-27M factor N to 0. */
> +	val = readl(reg + SUN8I_V853_FANOUT_27M_REG);
> +	val &= ~GENMASK(9, 8);
> +	writel(val, reg + SUN8I_V853_FANOUT_27M_REG);
> +
> +	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_v853_ccu_desc);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id sun8i_v853_ccu_ids[] = {
> +	{ .compatible = "allwinner,sun8i-v853-ccu" },
> +	{ }
> +};
> +
> +static struct platform_driver sun8i_v853_ccu_driver = {
> +	.probe	= sun8i_v853_ccu_probe,
> +	.driver	= {
> +		.name			= "sun8i-v853-ccu",
> +		.suppress_bind_attrs	= true,
> +		.of_match_table		= sun8i_v853_ccu_ids,
> +	},
> +};
> +module_platform_driver(sun8i_v853_ccu_driver);
> +
> +MODULE_IMPORT_NS("SUNXI_CCU");
> +MODULE_DESCRIPTION("Support for the Allwinner V853 CCU");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853.h b/drivers/clk/sunxi-ng/ccu-sun8i-v853.h
> new file mode 100644
> index 000000000000..f1b2a4d0bcd3
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com>
> + */
> +
> +#ifndef _CCU_SUN8I_V853_H_
> +#define _CCU_SUN8I_V853_H_
> +
> +#include <dt-bindings/clock/allwinner,sun8i-v853-ccu.h>
> +#include <dt-bindings/reset/allwinner,sun8i-v853-ccu.h>
> +
> +#define CLK_NUMBER		(CLK_FANOUT2 + 1)
> +
> +#endif
> 

Re: [PATCH v2 06/10] pmdomain: sunxi: add V853 ppu support

[Jernej Škrabec]

Dne sreda, 5. februar 2025 ob 13:52:21 Srednjeevropski standardni čas je Andras Szemzo napisal(a):
> V853 has a similar ppu like Allwinner D1, add compatible and the available pd names.
> 
> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

Re: [PATCH v2 08/10] phy: allwinner: add v853 usb phy compatible

[Jernej Škrabec]

Dne sreda, 5. februar 2025 ob 13:52:23 Srednjeevropski standardni čas je Andras Szemzo napisal(a):
> V853 has a dual role USB phy, similar to other Allwinner devices, but with
> only one phy. Add a compatible for it.
> 
> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

Re: [PATCH v2 04/10] clk: sunxi-ng: add CCU drivers for V853

[András Szemző]

Hi,

Thanks for your review!

> On 19 Feb 2025, at 21:21, Jernej Škrabec <jernej.skrabec@gmail.com> wrote:
> 
> Dne sreda, 5. februar 2025 ob 13:52:19 Srednjeevropski standardni čas je Andras Szemzo napisal(a):
>> V853 has similar gates/resets like existing Allwinner SOCs. Add support for it's CCU and PRCM CCU.
>> 
>> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
>> ---
>> drivers/clk/sunxi-ng/Kconfig            |   10 +
>> drivers/clk/sunxi-ng/Makefile           |    4 +
>> drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c |  120 +++
>> drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h |   14 +
>> drivers/clk/sunxi-ng/ccu-sun8i-v853.c   | 1145 +++++++++++++++++++++++
>> drivers/clk/sunxi-ng/ccu-sun8i-v853.h   |   14 +
>> 6 files changed, 1307 insertions(+)
>> create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
>> create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
>> create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.c
>> create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.h
>> 
>> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
>> index b547198a2c65..e257373177e0 100644
>> --- a/drivers/clk/sunxi-ng/Kconfig
>> +++ b/drivers/clk/sunxi-ng/Kconfig
>> @@ -12,6 +12,16 @@ config SUNIV_F1C100S_CCU
>> default y
>> depends on MACH_SUNIV || COMPILE_TEST
>> 
>> +config SUN8I_V853_CCU
>> + tristate "Support for the Allwinner V853/V851s/V851SE CCU"
>> + default MACH_SUN8I
>> + depends on MACH_SUN8I || COMPILE_TEST
>> +
>> +config SUN8I_V853_R_CCU
>> + tristate "Support for the Allwinner V853/V851s/V851SE PRCM CCU"
>> + default MACH_SUN8I
>> + depends on MACH_SUN8I || COMPILE_TEST
> 
> Generally, this are two patches, one for each driver.
> 
>> +
>> config SUN20I_D1_CCU
>> tristate "Support for the Allwinner D1/R528/T113 CCU"
>> default y
>> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
>> index 6b3ae2b620db..b87928462e15 100644
>> --- a/drivers/clk/sunxi-ng/Makefile
>> +++ b/drivers/clk/sunxi-ng/Makefile
>> @@ -25,6 +25,8 @@ sunxi-ccu-y += ccu_mp.o
>> 
>> # SoC support
>> obj-$(CONFIG_SUNIV_F1C100S_CCU) += suniv-f1c100s-ccu.o
>> +obj-$(CONFIG_SUN8I_V853_CCU) += sun8i-v853-ccu.o
>> +obj-$(CONFIG_SUN8I_V853_R_CCU) += sun8i-v853-r-ccu.o
> 
> Put it to other sun8i drivers.
> 
>> obj-$(CONFIG_SUN20I_D1_CCU) += sun20i-d1-ccu.o
>> obj-$(CONFIG_SUN20I_D1_R_CCU) += sun20i-d1-r-ccu.o
>> obj-$(CONFIG_SUN50I_A64_CCU) += sun50i-a64-ccu.o
>> @@ -50,6 +52,8 @@ obj-$(CONFIG_SUN9I_A80_CCU) += sun9i-a80-de-ccu.o
>> obj-$(CONFIG_SUN9I_A80_CCU) += sun9i-a80-usb-ccu.o
>> 
>> suniv-f1c100s-ccu-y += ccu-suniv-f1c100s.o
>> +sun8i-v853-ccu-y += ccu-sun8i-v853.o
>> +sun8i-v853-r-ccu-y += ccu-sun8i-v853-r.o
> 
> Ditto.
> 

ok

>> sun20i-d1-ccu-y += ccu-sun20i-d1.o
>> sun20i-d1-r-ccu-y += ccu-sun20i-d1-r.o
>> sun50i-a64-ccu-y += ccu-sun50i-a64.o
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
>> new file mode 100644
>> index 000000000000..bd60e00cda7f
>> --- /dev/null
>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
>> @@ -0,0 +1,120 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
>> + *
>> + * Based on ccu-sun20i-d1-r.c by Samuel Holland.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include "ccu_common.h"
>> +#include "ccu_reset.h"
>> +
>> +#include "ccu_gate.h"
>> +#include "ccu_mp.h"
>> +
>> +#include "ccu-sun8i-v853-r.h"
>> +
>> +static const struct clk_parent_data r_ahb_apb0_parents[] = {
>> + { .fw_name = "hosc" },
>> + { .fw_name = "losc" },
>> + { .fw_name = "iosc" },
>> + { .fw_name = "pll-periph" },
>> + { .fw_name = "pll-audio" }
>> +};
>> +
>> +static SUNXI_CCU_MP_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
>> +  r_ahb_apb0_parents, 0x000,
>> +  0, 5, /* M */
>> +  8, 2, /* P */
>> +  24, 3, /* mux */
>> +  0);
>> +static const struct clk_hw *r_ahb_hw = &r_ahb_clk.common.hw;
>> +
>> +static SUNXI_CCU_MP_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
>> +  r_ahb_apb0_parents, 0x00c,
>> +  0, 5, /* M */
>> +  8, 2, /* P */
>> +  24, 3, /* mux */
>> +  0);
>> +static const struct clk_hw *r_apb0_hw = &r_apb0_clk.common.hw;
> 
> Where can I look for above clocks? There are not described in BSP driver.
> 

As the original BSP’s PRCM driver has an unacceptable licence, I had to rewrite this driver.  This IP block
isn’t documented in the V853 manual, so as Andre suggested, I used the A523 manual, and the D1/T113
PRCM driver. Than I peek/poke the registers to check if it’s valid or not. 

awboot> read32 0x701000c
0x0701000c: 0x0f00031f
awboot> read32 0x7010000
0x07010000: 0x00000000
awboot> write32 0x7010000 0xffffffff
awboot> read32 0x7010000
0x07010000: 0x0700031f

They are there, I’m not sure about it’s usage.


>> +
>> +static SUNXI_CCU_GATE_HWS(bus_r_twd_clk, "bus-r-twd", &r_apb0_hw, 
>> +  0x12c, BIT(0), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_hw,
>> +  0x1ac, BIT(0), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_r_rtc_clk, "bus-r-rtc", &r_ahb_hw,
>> +  0x20c, BIT(0), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_r_cpucfg_clk, "bus-r-cpucfg", &r_apb0_hw,
>> +  0x22c, BIT(0), 0);
>> +
>> +static struct ccu_common *sun8i_v853_r_ccu_clks[] = {
>> + &r_ahb_clk.common,
>> + &r_apb0_clk.common,
>> + &bus_r_twd_clk.common,
>> + &bus_r_ppu_clk.common,
>> + &bus_r_rtc_clk.common,
>> + &bus_r_cpucfg_clk.common,
>> +};
>> +
>> +static struct clk_hw_onecell_data sun8i_v853_r_hw_clks = {
>> + .num = CLK_NUMBER,
>> + .hws = {
>> + [CLK_R_AHB] = &r_ahb_clk.common.hw,
>> + [CLK_R_APB0] = &r_apb0_clk.common.hw,
>> + [CLK_BUS_R_TWD] = &bus_r_twd_clk.common.hw,
>> + [CLK_BUS_R_PPU] = &bus_r_ppu_clk.common.hw,
>> + [CLK_BUS_R_RTC] = &bus_r_rtc_clk.common.hw,
>> + [CLK_BUS_R_CPUCFG] = &bus_r_cpucfg_clk.common.hw,
>> + },
>> +};
>> +
>> +static const struct ccu_reset_map sun8i_v853_r_ccu_resets[] = {
>> + [RST_BUS_R_TWD] = { 0x12c, BIT(16) },
> 
> Where did you get that? BSP driver that I checked doesn't mentions it.
> 

yes, just double checked and this bit is not valid, sorry, I’ll remove it.

>> + [RST_BUS_R_PPU] = { 0x1ac, BIT(16) },
>> + [RST_BUS_R_RTC] = { 0x20c, BIT(16) },
>> + [RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
>> +};
>> +
>> +static const struct sunxi_ccu_desc sun8i_v853_r_ccu_desc = {
>> + .ccu_clks = sun8i_v853_r_ccu_clks,
>> + .num_ccu_clks = ARRAY_SIZE(sun8i_v853_r_ccu_clks),
>> +
>> + .hw_clks = &sun8i_v853_r_hw_clks,
>> +
>> + .resets = sun8i_v853_r_ccu_resets,
>> + .num_resets = ARRAY_SIZE(sun8i_v853_r_ccu_resets),
>> +};
>> +
>> +static int sun8i_v853_r_ccu_probe(struct platform_device *pdev)
>> +{
>> + void __iomem *reg;
>> +
>> + reg = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(reg))
>> + return PTR_ERR(reg);
>> +
>> + return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_v853_r_ccu_desc);
>> +}
>> +
>> +static const struct of_device_id sun8i_v853_r_ccu_ids[] = {
>> + { .compatible = "allwinner,sun8i-v853-r-ccu" },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, sun8i_v853_r_ccu_ids);
>> +
>> +static struct platform_driver sun8i_v853_r_ccu_driver = {
>> + .probe = sun8i_v853_r_ccu_probe,
>> + .driver = {
>> + .name = "sun8i-v853-r-ccu",
>> + .suppress_bind_attrs = true,
>> + .of_match_table = sun8i_v853_r_ccu_ids,
>> + },
>> +};
>> +module_platform_driver(sun8i_v853_r_ccu_driver);
>> +
>> +MODULE_IMPORT_NS("SUNXI_CCU");
>> +MODULE_DESCRIPTION("Support for the Allwinner V853 PRCM CCU");
>> +MODULE_LICENSE("GPL");
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
>> new file mode 100644
>> index 000000000000..2c6cc7b6f251
>> --- /dev/null
>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
>> @@ -0,0 +1,14 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
>> + */
>> +
>> +#ifndef _CCU_SUN8I_V853_R_H
>> +#define _CCU_SUN8I_V853_R_H
>> +
>> +#include <dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h>
>> +#include <dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h>
>> +
>> +#define CLK_NUMBER (CLK_BUS_R_CPUCFG + 1)
>> +
>> +#endif
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853.c b/drivers/clk/sunxi-ng/ccu-sun8i-v853.c
>> new file mode 100644
>> index 000000000000..4b32f3a913cf
>> --- /dev/null
>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853.c
>> @@ -0,0 +1,1145 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
>> + *
>> + * Based on ccu-sun20i-d1.c by Samuel Holland.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include "../clk.h"
>> +
>> +#include "ccu_common.h"
>> +#include "ccu_reset.h"
>> +
>> +#include "ccu_div.h"
>> +#include "ccu_gate.h"
>> +#include "ccu_mp.h"
>> +#include "ccu_mult.h"
>> +#include "ccu_nk.h"
>> +#include "ccu_nkm.h"
>> +#include "ccu_nkmp.h"
>> +#include "ccu_nm.h"
>> +
>> +#include "ccu-sun8i-v853.h"
>> +
>> +static const struct clk_parent_data osc24M[] = {
>> + { .fw_name = "hosc" }
>> +};
>> +
>> +/*
>> + * For the CPU PLL, the output divider is described as "only for testing"
>> + * in the user manual. So it's not modelled and forced to 0.
>> + */
>> +#define SUN8I_V853_PLL_CPU_REG 0x000
>> +
>> +static struct ccu_mult pll_cpu_clk = {
>> + .enable = BIT(27),
>> + .lock = BIT(28),
>> + .mult = _SUNXI_CCU_MULT_MIN(8, 8, 11),
>> + .common = {
>> + .reg = 0x000,
>> + .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-cpu", osc24M,
>> +   &ccu_mult_ops,
>> +   CLK_SET_RATE_GATE),
>> + },
>> +};
>> +
>> +/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
>> +#define SUN8I_V853_PLL_DDR_REG 0x010
>> +static struct ccu_nkmp pll_ddr_clk = {
>> + .enable = BIT(27),
>> + .lock = BIT(28),
>> + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
>> + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
>> + .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
>> + .common = {
>> + .reg = 0x010,
>> + .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr", osc24M,
>> +   &ccu_nkmp_ops,
>> +   CLK_SET_RATE_GATE),
>> + },
>> +};
>> +
>> +#define SUN8I_V853_PLL_PERIPH_REG 0x020
>> +static struct ccu_nm pll_periph_4x_clk = {
>> + .enable = BIT(27),
>> + .lock = BIT(28),
>> + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
>> + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
>> + .common = {
>> + .reg = 0x020,
>> + .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph-4x", osc24M,
>> +   &ccu_nm_ops,
>> +   CLK_SET_RATE_GATE),
>> + },
>> +};
>> +
>> +static const struct clk_hw *pll_periph_4x_hws[] = {
>> + &pll_periph_4x_clk.common.hw
>> +};
>> +
>> +static SUNXI_CCU_M_HWS(pll_periph_2x_clk, "pll-periph-2x", pll_periph_4x_hws,
>> +       0x020, 16, 3, 0);
>> +
>> +static SUNXI_CCU_M_HWS(pll_periph_800M_clk, "pll-periph-800M", pll_periph_4x_hws,
>> +       0x020, 20, 3, 0);
>> +
>> +static SUNXI_CCU_M_HWS(pll_periph_480M_clk, "pll-periph-480M", pll_periph_4x_hws,
>> +       0x020, 2, 3, 0);
>> +
>> +static CLK_FIXED_FACTOR_HW(pll_periph_600M_clk, "pll-periph-600M",
>> +   &pll_periph_2x_clk.common.hw, 2, 1, 0);
>> +
>> +static CLK_FIXED_FACTOR_HW(pll_periph_400M_clk, "pll-periph-400M",
>> +   &pll_periph_2x_clk.common.hw, 3, 1, 0);
>> +
>> +static CLK_FIXED_FACTOR_HW(pll_periph_300M_clk, "pll-periph-300M",
>> +   &pll_periph_600M_clk.hw, 2, 1, 0);
>> +
>> +static CLK_FIXED_FACTOR_HW(pll_periph_200M_clk, "pll-periph-200M",
>> +   &pll_periph_400M_clk.hw, 2, 1, 0);
>> +
>> +static CLK_FIXED_FACTOR_HW(pll_periph_160M_clk, "pll-periph-160M",
>> +   &pll_periph_480M_clk.common.hw, 3, 1, 0);
>> +
>> +static CLK_FIXED_FACTOR_HW(pll_periph_150M_clk, "pll-periph-150M",
>> +   &pll_periph_300M_clk.hw, 2, 1, 0);
>> +
>> +/*
>> + * For Video PLLs, the output divider is described as "only for testing"
>> + * in the user manual.
>> + */
>> +#define SUN8I_V853_PLL_VIDEO_REG 0x040
>> +static struct ccu_nkmp pll_video_4x_clk = {
>> + .enable = BIT(27),
>> + .lock = BIT(28),
>> + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
>> + .p = _SUNXI_CCU_DIV(1, 1), /* input divider */
>> + .common = {
>> + .reg = 0x040,
>> + .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video-4x", osc24M,
>> +   &ccu_nkmp_ops,
>> +   CLK_SET_RATE_GATE),
>> + },
>> +};
>> +
>> +static const struct clk_hw *pll_video_4x_hws[] = {
>> + &pll_video_4x_clk.common.hw
>> +};
>> +static CLK_FIXED_FACTOR_HWS(pll_video_2x_clk, "pll-video-2x",
>> +    pll_video_4x_hws, 2, 1, CLK_SET_RATE_PARENT);
>> +static CLK_FIXED_FACTOR_HWS(pll_video_1x_clk, "pll-video-1x",
>> +    pll_video_4x_hws, 4, 1, CLK_SET_RATE_PARENT);
>> +
>> +
>> +/*
>> + * For CSI PLLs, the output divider is described as "only for testing"
>> + * in the user manual.
>> + */
>> +#define SUN8I_V853_PLL_CSI_REG 0x048
>> +static struct ccu_nkmp pll_csi_4x_clk = {
>> + .enable = BIT(27),
>> + .lock = BIT(28),
>> + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
>> + .p = _SUNXI_CCU_DIV(1, 1), /* input divider */
>> + .common = {
>> + .reg = 0x048,
>> + .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-csi-4x", osc24M,
>> +   &ccu_nkmp_ops,
>> +   CLK_SET_RATE_GATE),
>> + },
>> +};
>> +
>> +static CLK_FIXED_FACTOR_HW(pll_csi_clk, "pll-csi",
>> +   &pll_csi_4x_clk.common.hw, 4, 1, CLK_SET_RATE_PARENT);
>> +
>> +
>> +#define SUN8I_V853_PLL_AUDIO_REG 0x078
>> +static struct ccu_sdm_setting pll_audio_div5_sdm_table[] = {
>> + { .rate = 196608000, .pattern = 0xc001eb85, .m = 5, .n = 40 }, /* 24.576 */
>> + { .rate = 67737600, .pattern = 0xc001288d, .m = 8, .n = 22 }, /* 22.5792 */
>> +};
>> +
>> +static struct ccu_nm pll_audio_div5_clk = {
>> + .enable = BIT(27),
>> + .lock           = BIT(28),
>> + .n              = _SUNXI_CCU_MULT(8, 8),
>> + .m              = _SUNXI_CCU_DIV(20, 3),
>> + .sdm            = _SUNXI_CCU_SDM(pll_audio_div5_sdm_table,
>> +    BIT(24), 0x0178, BIT(31)),
>> + .common         = {
>> + .reg            = 0x0078,
>> + .features       = CCU_FEATURE_SIGMA_DELTA_MOD,
>> + .hw.init        = CLK_HW_INIT_PARENTS_DATA("pll-audio-div5", osc24M,
>> +   &ccu_nm_ops,
>> +   CLK_SET_RATE_UNGATE),
>> + },
>> +};
>> +
>> +static const struct clk_hw *pll_audio_div5_hws[] = {
>> + &pll_audio_div5_clk.common.hw
>> +};
>> +
>> +static SUNXI_CCU_M_HWS(pll_audio_1x_clk, "pll-audio-1x", pll_audio_div5_hws,
>> +       0xe00, 0, 5, CLK_SET_RATE_PARENT);
>> +
>> +/* pll-audio-div2 and pll-audio-4x not used, because pll-audio-1x can cover 
>> + * 22.5792M and 24.576M 
>> + */
>> +static SUNXI_CCU_M(pll_audio_div2_clk, "pll-audio-div2", "pll-audio",
>> +   0x078, 16, 3, 0);
>> +static SUNXI_CCU_M(pll_audio_4x_clk, "pll-audio-4x", "pll-audio-div2",
>> +   0xe00, 5, 5, 0);
>> +
>> +/*
>> + * For the NPU PLL, the output divider is described as "only for testing"
>> + * in the user manual.
>> + */
>> +#define SUN8I_V853_PLL_NPU_REG 0x080
>> +static struct ccu_nkmp pll_npu_4x_clk = {
>> + .enable = BIT(27),
>> + .lock = BIT(28),
>> + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
>> + .p = _SUNXI_CCU_DIV(1, 1), /* input divider */
>> + .common = {
>> + .reg = 0x080,
>> + .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-npu-4x", osc24M,
>> +   &ccu_nkmp_ops,
>> +   CLK_SET_RATE_UNGATE),
>> + },
>> +};
>> +
>> +/*
>> + * The CPU gate is not modelled - it is in a separate register (0x504)
>> + * and has a special key field. The clock must not be gated anyway by
>> + * the kernel.
>> + */
>> +static const struct clk_parent_data cpu_parents[] = {
>> + { .fw_name = "hosc" },
>> + { .fw_name = "losc" },
>> + { .fw_name = "iosc" },
>> + { .hw = &pll_cpu_clk.common.hw },
>> + { .hw = &pll_periph_600M_clk.hw },
>> + { .hw = &pll_periph_800M_clk.common.hw },
>> +};
>> +
>> +/*
>> + * There is a P factor (PLL_OUT_EXT_DIVP[17:16]) in this register, but it is not modeled.
>> + * The manual states that it should be used only, when the output clock is less than 288 MHz.
>> + */
>> +static SUNXI_CCU_MUX_DATA(cpu_clk, "cpu", cpu_parents,
>> +  0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
>> +
>> +static const struct clk_hw *cpu_hws[] = { &cpu_clk.common.hw };
>> +
>> +static SUNXI_CCU_M_HWS(cpu_axi_clk, "cpu-axi", cpu_hws,
>> +       0x500, 0, 2, 0);
>> +static SUNXI_CCU_M_HWS(cpu_apb_clk, "cpu-apb", cpu_hws,
>> +       0x500, 8, 2, 0);
>> +
>> +static const struct clk_parent_data ahb_parents[] = {
>> + { .fw_name = "hosc" },
>> + { .fw_name = "losc" },
>> + { .fw_name = "iosc" },
>> + { .hw = &pll_periph_600M_clk.hw },
>> +};
>> +static SUNXI_CCU_MP_DATA_WITH_MUX(ahb_clk, "ahb", ahb_parents, 0x510,
>> +  0, 5, /* M */
>> +  8, 2, /* P */
>> +  24, 2, /* mux */
>> +  0);
>> +
>> +static SUNXI_CCU_MP_DATA_WITH_MUX(apb0_clk, "apb0", ahb_parents, 0x520,
>> +  0, 5, /* M */
>> +  8, 2, /* P */
>> +  24, 2, /* mux */
>> +  0);
>> +
>> +static SUNXI_CCU_MP_DATA_WITH_MUX(apb1_clk, "apb1", ahb_parents, 0x524,
>> +  0, 5, /* M */
>> +  8, 2, /* P */
>> +  24, 2, /* mux */
>> +  0);
>> +
>> +static const struct clk_hw *ahb_hws[] = { &ahb_clk.common.hw };
>> +static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw };
>> +static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw };
>> +
>> +
>> +static const struct clk_hw *de_g2d_parents[] = {
>> + &pll_periph_300M_clk.hw,
>> + &pll_video_1x_clk.hw,
>> +};
>> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_g2d_parents, 0x600,
>> +    0, 5, /* M */
>> +    24, 1, /* mux */
>> +    BIT(31), /* gate */
>> +    CLK_SET_RATE_PARENT);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", ahb_hws,
>> +  0x60c, BIT(0), 0);
>> +
>> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", de_g2d_parents, 0x630,
>> +    0, 5, /* M */
>> +    24, 1, /* mux */
>> +    BIT(31), /* gate */
>> +    CLK_SET_RATE_PARENT);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb_hws,
>> +  0x63c, BIT(0), 0);
>> +
>> +
>> +static const struct clk_parent_data ce_parents[] = {
>> + { .fw_name = "hosc" },
> 
> Where this come from? V853 manual v1.1 doesn't have it.

There is a sun8iw21 ccu driver [1], where hosc is the first parent:

[1]:
https://github.com/YuzukiHD/TinyVision/blob/main/kernel/bsp/drivers/clk/sunxi-ng/ccu-sun8iw21.c#L262

I don’t know if the manual or if this driver is the correct.

> 
>> + { .hw = &pll_periph_400M_clk.hw, },
>> + { .hw = &pll_periph_300M_clk.hw, }
>> +};
>> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
>> +      0, 4, /* M */
>> +      24, 3, /* mux */
>> +      BIT(31), /* gate */
>> +      CLK_SET_RATE_PARENT);
> 
> Set rate parent flag doesn't make sense on constant parents.

yes

> 
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", ahb_hws,
>> +  0x68c, BIT(0) | BIT(1), 0);
>> +
>> +static const struct clk_hw *ve_parents[] = {
>> + &pll_periph_300M_clk.hw,
>> + &pll_periph_400M_clk.hw,
>> + &pll_periph_480M_clk.common.hw,
>> + &pll_npu_4x_clk.common.hw,
>> + &pll_video_4x_clk.common.hw,
>> + &pll_csi_4x_clk.common.hw,
>> +};
>> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
>> +    0, 5, /* M */
>> +    24, 3, /* mux */
>> +    BIT(31), /* gate */
>> +    0);
> 
> CLK_SET_RATE_PARENT flag? Cedrus driver set working clock at the beginning.
> 

ok

>> +
>> +static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", ahb_hws,
>> +  0x69c, BIT(0), 0);
>> +
>> +
>> +static const struct clk_hw *npu_parents[] = {
>> + &pll_periph_480M_clk.common.hw,
>> + &pll_periph_600M_clk.hw,
>> + &pll_periph_800M_clk.common.hw,
>> + &pll_npu_4x_clk.common.hw,
>> +};
>> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0x6e0,
>> +    0, 5, /* M */
>> +    24, 3, /* mux */
>> +    BIT(31), /* gate */
>> +    0);
> 
> I think CLK_SET_RATE_PARENT would also be beneficial here.

I tried to mimic how the BSP setup the NPU clocks (as I think, not sure), in the dts I setup it like:

                npu: npu@3050000 {
                        compatible = "vivante,gc";
                        reg = <0x03050000 0x1000>;
                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "npu";
                        clocks = <&ccu CLK_BUS_NPU>, <&ccu CLK_NPU>;
                        clock-names = "bus", "core";
                        assigned-clocks = <&ccu CLK_PLL_NPU_4X>, <&ccu CLK_NPU>;
                        assigned-clock-parents = <&dcxo>, <&ccu CLK_PLL_NPU_4X>;
                        assigned-clock-rates =  <1392000000>, <348000000>;
                        resets = <&ccu RST_BUS_NPU>;
                        iommus = <&iommu 6>;
                        power-domains = <&ppu PD_NPU>;
                };

With these settings (after adding a reset support to the etnaviv driver) at least I'm able to dump some registers via debugfs.
Do you think I should add the CLK_SET_RATE_PARENT flag?

> 
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_npu_clk, "bus-npu", ahb_hws,
>> +  0x6ec, BIT(0), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", ahb_hws,
>> +  0x70c, BIT(0), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", ahb_hws,
>> +  0x71c, BIT(0), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_msgbox1_clk, "bus-msgbox1", ahb_hws,
>> +  0x71c, BIT(1), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", ahb_hws,
>> +  0x72c, BIT(0), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", ahb_hws,
>> +  0x73c, BIT(0), 0);
>> +
>> +static SUNXI_CCU_GATE_DATA(avs_clk, "avs", osc24M,
>> +   0x740, BIT(31), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", ahb_hws,
>> +  0x78c, BIT(0), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_pwm_clk, "bus-pwm", apb0_hws,
>> +  0x7ac, BIT(0), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", ahb_hws,
>> +  0x7bc, BIT(0), 0);
>> +
>> +static const struct clk_hw *dram_parents[] = {
>> + &pll_ddr_clk.common.hw,
>> + &pll_periph_2x_clk.common.hw,
>> + &pll_periph_800M_clk.common.hw,
>> +};
>> +static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dram_clk, "dram", dram_parents, 0x800,
>> +     0, 5, /* M */
>> +     8, 2, /* P */
>> +     24, 3, /* mux */
>> +     BIT(31), CLK_IS_CRITICAL);
> 
> This clock needs update field to be set to actually apply configuration. So
> same comment as on A523 clock version, this needs new flag to be introduced
> for such case.
> 

ok

>> +
>> +static CLK_FIXED_FACTOR_HW(mbus_clk, "mbus",
>> +   &dram_clk.common.hw, 4, 1, 0);
>> +
>> +static const struct clk_hw *mbus_hws[] = { &mbus_clk.hw };
>> +
>> +static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
>> +  0x804, BIT(0), 0);
>> +static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws,
>> +  0x804, BIT(1), 0);
>> +static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws,
>> +  0x804, BIT(2), 0);
>> +static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws,
>> +  0x804, BIT(8), 0);
>> +static SUNXI_CCU_GATE_HWS(mbus_isp_clk, "mbus-isp", mbus_hws,
>> +  0x804, BIT(9), 0);
>> +static SUNXI_CCU_GATE_HWS(mbus_g2d_clk, "mbus-g2d", mbus_hws,
>> +  0x804, BIT(10), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", ahb_hws,
>> +  0x80c, BIT(0), CLK_IS_CRITICAL);
>> +
>> +
>> +static const struct clk_parent_data mmc0_mmc1_parents[] = {
>> + { .fw_name = "hosc" },
>> + { .hw = &pll_periph_400M_clk.hw, },
>> + { .hw = &pll_periph_300M_clk.hw, },
>> +};
> 
> Just mmc_parents.

ok

> 
>> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830,
>> +       0, 4, /* M */
>> +       8, 2, /* P */
>> +       24, 3, /* mux */
>> +       BIT(31), /* gate */
>> +       0);
>> +
>> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834,
>> +       0, 4, /* M */
>> +       8, 2, /* P */
>> +       24, 3, /* mux */
>> +       BIT(31), /* gate */
>> +       0);
>> +
>> +static const struct clk_parent_data mmc2_parents[] = {
>> + { .fw_name = "hosc" },
>> + { .hw = &pll_periph_600M_clk.hw, },
>> + { .hw = &pll_periph_400M_clk.hw, },
>> +};
>> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838,
>> +       0, 4, /* M */
>> +       8, 2, /* P */
>> +       24, 3, /* mux */
>> +       BIT(31), /* gate */
>> +       0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", ahb_hws,
>> +  0x84c, BIT(0), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", ahb_hws,
>> +  0x84c, BIT(1), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", ahb_hws,
>> +  0x84c, BIT(2), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws,
>> +  0x90c, BIT(0), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws,
>> +  0x90c, BIT(1), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws,
>> +  0x90c, BIT(2), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws,
>> +  0x90c, BIT(3), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws,
>> +  0x91c, BIT(0), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws,
>> +  0x91c, BIT(1), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws,
>> +  0x91c, BIT(2), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws,
>> +  0x91c, BIT(3), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_i2c4_clk, "bus-i2c4", apb1_hws,
>> +  0x91c, BIT(4), 0);
>> +
>> +static const struct clk_parent_data spi_parents[] = {
>> + { .fw_name = "hosc" },
>> + { .hw = &pll_periph_300M_clk.hw, },
>> + { .hw = &pll_periph_200M_clk.hw, },
>> +};
>> +
>> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
>> +       0, 4, /* M */
>> +       8, 2, /* P */
>> +       24, 3, /* mux */
>> +       BIT(31), /* gate */
>> +       0);
>> +
>> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
>> +       0, 4, /* M */
>> +       8, 2, /* P */
>> +       24, 3, /* mux */
>> +       BIT(31), /* gate */
>> +       0);
>> +
>> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi2_clk, "spi2", spi_parents, 0x948,
>> +       0, 4, /* M */
>> +       8, 2, /* P */
>> +       24, 3, /* mux */
>> +       BIT(31), /* gate */
>> +       0);
>> +
>> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi3_clk, "spi3", spi_parents, 0x94c,
>> +       0, 4, /* M */
>> +       8, 2, /* P */
>> +       24, 3, /* mux */
>> +       BIT(31), /* gate */
>> +       0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", ahb_hws,
>> +  0x96c, BIT(0), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", ahb_hws,
>> +  0x96c, BIT(1), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_spi2_clk, "bus-spi2", ahb_hws,
>> +  0x96c, BIT(2), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_spi3_clk, "bus-spi3", ahb_hws,
>> +  0x96c, BIT(3), 0);
>> +
>> +
>> +static const struct clk_parent_data spif_parents[] = {
>> + { .fw_name = "hosc" },
>> + { .hw = &pll_periph_400M_clk.hw, },
>> + { .hw = &pll_periph_300M_clk.hw, },
>> +};
>> +
>> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(spif_clk, "spif", spif_parents, 0x0950,
>> +      0, 4, /* M */
>> +      24, 3, /* mux */
>> +      BIT(31), /* gate */
>> +      CLK_SET_RATE_PARENT);
> 
> This is MP clock, P being at 9:8.

yes, the BSP driver [1] model it with only M, I’ll update it to MP.

> 
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_spif_clk, "bus-spif", ahb_hws,
>> +  0x096c, BIT(4), 0);
>> +
>> +
>> +static const struct clk_hw *pll_periph_150M_hws[] = { &pll_periph_150M_clk.hw };
>> +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25M_clk, "emac-25M", pll_periph_150M_hws,
>> +      0x970, BIT(31) | BIT(30), 6, 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_emac_clk, "bus-emac", ahb_hws,
>> +  0x97c, BIT(0), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_gpadc_clk, "bus-gpadc", apb0_hws,
>> +  0x9ec, BIT(0), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", ahb_hws,
>> +  0x9fc, BIT(0), 0);
>> +
>> +
>> +static const struct clk_hw *audio_parents[] = {
>> + &pll_audio_1x_clk.common.hw,
>> + &pll_audio_4x_clk.common.hw,
>> +};
>> +
>> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2s0_clk, "i2s0", audio_parents, 0xa10,
>> +    0, 4, /* M */
>> +    24, 1, /* mux */
>> +    BIT(31), /* gate */
>> +    CLK_SET_RATE_PARENT);
>> +
>> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2s1_clk, "i2s1", audio_parents, 0xa14,
>> +    0, 4, /* M */
>> +    24, 1, /* mux */
>> +    BIT(31), /* gate */
>> +    CLK_SET_RATE_PARENT);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_i2s0_clk, "bus-i2s0", ahb_hws,
>> +  0xa20, BIT(0), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_i2s1_clk, "bus-i2s1", ahb_hws,
>> +  0xa20, BIT(1), 0);
>> +
>> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dmic_clk, "dmic", audio_parents, 0xa40,
>> +    0, 4, /* M */
>> +    24, 1, /* mux */
>> +    BIT(31), /* gate */
>> +    CLK_SET_RATE_PARENT);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", ahb_hws,
>> +  0xa4c, BIT(0), 0);
>> +
>> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(audio_codec_dac_clk, "audio-codec-dac", 
>> +    audio_parents, 0xa50,
>> +    0, 4, /* M */
>> +    24, 1, /* mux */
>> +    BIT(31), /* gate */
>> +    CLK_SET_RATE_PARENT);
>> +
>> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(audio_codec_adc_clk, "audio-codec-adc", 
>> +    audio_parents, 0xa54,
>> +    0, 4, /* M */
>> +    24, 1, /* mux */
>> +    BIT(31), /* gate */
>> +    CLK_SET_RATE_PARENT);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_audio_codec_clk, "bus-audio-codec", apb0_hws,
>> +  0xa5c, BIT(0), 0);
>> +
>> +/*
>> + * There are OHCI 12M clock source selection bits for the USB 2.0 port.
>> + * We will force them to 0 (12M divided from 48M).
>> + */
>> +static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
>> +
>> +#define SUN8I_V853_USB_CLK_REG 0xa70
>> +
>> +static SUNXI_CCU_GATE(usb_ohci_clk, "usb", "osc12M", 0x0a70, BIT(31), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_ohci_clk, "bus-ohci", ahb_hws, 0xa8c, BIT(0), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_ehci_clk, "bus-ehci", ahb_hws, 0xa8c, BIT(4), 0);
>> +static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", ahb_hws, 0xa8c, BIT(8), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_dpss_top_clk, "bus-dpss-top", ahb_hws,
>> +  0xabc, BIT(0), 0);
>> +
>> +
>> +static const struct clk_parent_data mipi_dsi_parents[] = {
>> + { .fw_name = "hosc" },
>> + { .hw = &pll_periph_200M_clk.hw },
>> + { .hw = &pll_periph_150M_clk.hw },
>> +};
>> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", mipi_dsi_parents, 
>> +      0xb24,
>> +      0, 4, /* M */
>> +      24, 3, /* mux */
>> +      BIT(31), /* gate */
>> +      CLK_SET_RATE_PARENT);
> 
> CLK_SET_RATE_PARENT doesn't do anything for constant clocks.
> 

ok

> Best regards,
> Jernej
> 
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_mipi_dsi_clk, "bus-mipi-dsi", ahb_hws,
>> +  0xb4c, BIT(0), 0);
>> +
>> +
>> +static const struct clk_hw *tcon_lcd_parents[] = {
>> + &pll_video_4x_clk.common.hw,
>> + &pll_periph_2x_clk.common.hw,
>> + &pll_csi_4x_clk.common.hw,
>> +};
>> +static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_lcd_clk, "tcon-lcd", tcon_lcd_parents, 
>> +     0xb60,
>> +     0, 4, /* M */
>> +     8, 2, /* P */
>> +     24, 3, /* mux */
>> +     BIT(31), /* gate */
>> +     CLK_SET_RATE_PARENT);
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_tcon_lcd_clk, "bus-tcon-lcd", ahb_hws,
>> +  0xb7c, BIT(0), 0);
>> +
>> +
>> +static const struct clk_hw *csi_top_parents[] = {
>> + &pll_periph_300M_clk.hw,
>> + &pll_periph_400M_clk.hw,
>> + &pll_video_4x_clk.common.hw,
>> + &pll_csi_4x_clk.common.hw,
>> +};
>> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents, 0xc04,
>> +    0, 5, /* M */
>> +    24, 3, /* mux */
>> +    BIT(31), /* gate */
>> +    0);
>> +
>> +
>> +static const struct clk_parent_data csi_mclk_parents[] = {
>> + { .fw_name = "hosc" },
>> + { .hw = &pll_csi_4x_clk.common.hw },
>> + { .hw = &pll_video_4x_clk.common.hw },
>> + { .hw = &pll_periph_2x_clk.common.hw },
>> +};
>> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk0_clk, "csi-mclk0", csi_mclk_parents, 
>> +      0xc08,
>> +      0, 5, /* M */
>> +      24, 3, /* mux */
>> +      BIT(31), /* gate */
>> +      0);
>> +
>> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk1_clk, "csi-mclk1", csi_mclk_parents, 
>> +      0xc0c,
>> +      0, 5, /* M */
>> +      24, 3, /* mux */
>> +      BIT(31), /* gate */
>> +      0);
>> +
>> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk2_clk, "csi-mclk2", csi_mclk_parents, 
>> +      0xc10,
>> +      0, 5, /* M */
>> +      24, 3, /* mux */
>> +      BIT(31), /* gate */
>> +      0);
> 
> All CSI mclks should be MP type.
> 

Again, these are from the BSP, I’ll update them.

>> +
>> +static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", ahb_hws,
>> +  0xc2c, BIT(0), 0);
>> +
>> +
>> +static SUNXI_CCU_GATE_HWS(bus_wiegand_clk, "bus-wiegand", ahb_hws,
>> +  0xc7c, BIT(0), 0);
>> +
>> +
>> +static const struct clk_parent_data riscv_parents[] = {
>> + { .fw_name = "hosc" },
>> + { .fw_name = "losc" },
>> + { .fw_name = "iosc" },
>> + { .hw = &pll_periph_600M_clk.hw },
>> + { .hw = &pll_periph_480M_clk.common.hw },
>> + { .hw = &pll_cpu_clk.common.hw },
>> +};
>> +static SUNXI_CCU_M_DATA_WITH_MUX(riscv_clk, "riscv-cpu", riscv_parents, 0xd00,
>> + 0, 5, /* M */
>> + 24, 3, /* mux */
>> + CLK_SET_RATE_PARENT);
>> +
>> +/* The riscv-axi clk must be divided by at least 2. */
>> +static struct clk_div_table riscv_axi_table[] = {
>> + { .val = 1, .div = 2 },
>> + { .val = 2, .div = 3 },
>> + { .val = 3, .div = 4 },
>> + { /* Sentinel */ }
>> +};
>> +static SUNXI_CCU_DIV_TABLE_HW(riscv_axi_clk, "riscv-axi", &riscv_clk.common.hw,
>> +      0xd00, 8, 2, riscv_axi_table, 0);
>> +
>> +static SUNXI_CCU_GATE_HWS_WITH_KEY(riscv_core_gate, "riscv-core-gate", ahb_hws,
>> +   0xd04, BIT(0), 0);
>> +
>> +static SUNXI_CCU_GATE_HWS(riscv_cfg_gate, "riscv-cfg-gate", ahb_hws,
>> +  0xd0c, BIT(0), 0);
>> +
>> +
>> +static const struct clk_hw *pll_periph_160M_hws[] = {
>> + &pll_periph_160M_clk.hw,
>> +};
>> +
>> +static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
>> +   0xf30, BIT(0), 0);
>> +static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
>> +       0xf30, BIT(1), 2, 0);
>> +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph_160M_hws,
>> +      0xf30, BIT(2), 10, 0);
>> +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph_150M_hws,
>> +      0xf30, BIT(3), 6, 0);
>> +
>> +
>> +/* This clock has a second divider that is not modelled and forced to 0. */
>> +#define SUN8I_V853_FANOUT_27M_REG 0xf34
>> +static const struct clk_hw *fanout_27M_parents[] = {
>> + &pll_video_1x_clk.hw,
>> + &pll_csi_clk.hw,
>> + &pll_periph_300M_clk.hw,
>> +};
>> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(fanout_27M_clk, "fanout-27M", 
>> +    fanout_27M_parents, 0xf34,
>> +    0, 5, /* M */
>> +    24, 2, /* mux */
>> +    BIT(31), /* gate */
>> +    0);
>> +static SUNXI_CCU_M_HWS_WITH_GATE(fanout_pclk_clk, "fanout-pclk", apb0_hws, 0xf38,
>> + 0, 5, /* M */
>> + BIT(31), /* gate */
>> + 0);
>> +
>> +static const struct clk_parent_data fanout_parents[] = {
>> + { .fw_name = "losc" },
>> + { .hw = &fanout_12M_clk.common.hw },
>> + { .hw = &fanout_16M_clk.common.hw },
>> + { .hw = &fanout_24M_clk.common.hw },
>> + { .hw = &fanout_25M_clk.common.hw },
>> + { .hw = &fanout_27M_clk.common.hw },
>> + { .hw = &fanout_pclk_clk.common.hw },
>> +};
>> +
>> +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 0xf3c,
>> +    0, 3, /* mux */
>> +    BIT(21), /* gate */
>> +    0);
>> +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 0xf3c,
>> +    3, 3, /* mux */
>> +    BIT(22), /* gate */
>> +    0);
>> +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 0xf3c,
>> +    6, 3, /* mux */
>> +    BIT(23), /* gate */
>> +    0);
>> +
>> +
>> +static struct ccu_common *sun8i_v853_ccu_clks[] = {
>> + &pll_cpu_clk.common,
>> + &pll_ddr_clk.common,
>> + &pll_periph_4x_clk.common,
>> + &pll_periph_2x_clk.common,
>> + &pll_periph_800M_clk.common,
>> + &pll_periph_480M_clk.common,
>> + &pll_video_4x_clk.common,
>> + &pll_csi_4x_clk.common,
>> + &pll_audio_div2_clk.common,
>> + &pll_audio_div5_clk.common,
>> + &pll_audio_4x_clk.common,
>> + &pll_audio_1x_clk.common,
>> + &pll_npu_4x_clk.common,
>> + &cpu_clk.common,
>> + &cpu_axi_clk.common,
>> + &cpu_apb_clk.common,
>> + &ahb_clk.common,
>> + &apb0_clk.common,
>> + &apb1_clk.common,
>> + &de_clk.common,
>> + &bus_de_clk.common,
>> + &g2d_clk.common,
>> + &bus_g2d_clk.common,
>> + &ce_clk.common,
>> + &bus_ce_clk.common,
>> + &ve_clk.common,
>> + &bus_ve_clk.common,
>> + &npu_clk.common,
>> + &bus_npu_clk.common,
>> + &bus_dma_clk.common,
>> + &bus_msgbox0_clk.common,
>> + &bus_msgbox1_clk.common,
>> + &bus_spinlock_clk.common,
>> + &bus_hstimer_clk.common,
>> + &avs_clk.common,
>> + &bus_dbg_clk.common,
>> + &bus_pwm_clk.common,
>> + &bus_iommu_clk.common,
>> + &dram_clk.common,
>> + &mbus_dma_clk.common,
>> + &mbus_ve_clk.common,
>> + &mbus_ce_clk.common,
>> + &mbus_csi_clk.common,
>> + &mbus_isp_clk.common,
>> + &mbus_g2d_clk.common,
>> + &bus_dram_clk.common,
>> + &mmc0_clk.common,
>> + &mmc1_clk.common,
>> + &mmc2_clk.common,
>> + &bus_mmc0_clk.common,
>> + &bus_mmc1_clk.common,
>> + &bus_mmc2_clk.common,
>> + &bus_uart0_clk.common,
>> + &bus_uart1_clk.common,
>> + &bus_uart2_clk.common,
>> + &bus_uart3_clk.common,
>> + &bus_i2c0_clk.common,
>> + &bus_i2c1_clk.common,
>> + &bus_i2c2_clk.common,
>> + &bus_i2c3_clk.common,
>> + &bus_i2c4_clk.common,
>> + &spi0_clk.common,
>> + &spi1_clk.common,
>> + &spi2_clk.common,
>> + &spi3_clk.common,
>> + &bus_spi0_clk.common,
>> + &bus_spi1_clk.common,
>> + &bus_spi2_clk.common,
>> + &bus_spi3_clk.common,
>> + &spif_clk.common,
>> + &bus_spif_clk.common,
>> + &emac_25M_clk.common,
>> + &bus_emac_clk.common,
>> + &bus_gpadc_clk.common,
>> + &bus_ths_clk.common,
>> + &usb_ohci_clk.common,
>> + &bus_ohci_clk.common,
>> + &bus_ehci_clk.common,
>> + &bus_otg_clk.common,
>> + &i2s0_clk.common,
>> + &i2s1_clk.common,
>> + &bus_i2s0_clk.common,
>> + &bus_i2s1_clk.common,
>> + &dmic_clk.common,
>> + &bus_dmic_clk.common,
>> + &audio_codec_dac_clk.common,
>> + &audio_codec_adc_clk.common,
>> + &bus_audio_codec_clk.common,
>> + &bus_dpss_top_clk.common,
>> + &mipi_dsi_clk.common,
>> + &bus_mipi_dsi_clk.common,
>> + &tcon_lcd_clk.common,
>> + &bus_tcon_lcd_clk.common,
>> + &csi_top_clk.common,
>> + &csi_mclk0_clk.common,
>> + &csi_mclk1_clk.common,
>> + &csi_mclk2_clk.common,
>> + &bus_csi_clk.common,
>> + &bus_wiegand_clk.common,
>> + &riscv_clk.common,
>> + &riscv_axi_clk.common,
>> + &riscv_core_gate.common,
>> + &riscv_cfg_gate.common,
>> + &fanout_24M_clk.common,
>> + &fanout_12M_clk.common,
>> + &fanout_16M_clk.common,
>> + &fanout_25M_clk.common,
>> + &fanout_27M_clk.common,
>> + &fanout_pclk_clk.common,
>> + &fanout0_clk.common,
>> + &fanout1_clk.common,
>> + &fanout2_clk.common,
>> +};
>> +
>> +static struct clk_hw_onecell_data sun8i_v853_hw_clks = {
>> + .num = CLK_NUMBER,
>> + .hws = {
>> + [CLK_OSC12M]            = &osc12M_clk.hw,
>> + [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
>> + [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
>> + [CLK_PLL_PERIPH_4X] = &pll_periph_4x_clk.common.hw,
>> + [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.common.hw,
>> + [CLK_PLL_PERIPH_800M] = &pll_periph_800M_clk.common.hw,
>> + [CLK_PLL_PERIPH_480M] = &pll_periph_480M_clk.common.hw,
>> + [CLK_PLL_PERIPH_600M] = &pll_periph_600M_clk.hw,
>> + [CLK_PLL_PERIPH_400M] = &pll_periph_400M_clk.hw,
>> + [CLK_PLL_PERIPH_300M] = &pll_periph_300M_clk.hw,
>> + [CLK_PLL_PERIPH_200M] = &pll_periph_200M_clk.hw,
>> + [CLK_PLL_PERIPH_160M] = &pll_periph_160M_clk.hw,
>> + [CLK_PLL_PERIPH_150M] = &pll_periph_150M_clk.hw,
>> + [CLK_PLL_VIDEO_4X] = &pll_video_4x_clk.common.hw,
>> + [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
>> + [CLK_PLL_VIDEO_1X] = &pll_video_1x_clk.hw,
>> + [CLK_PLL_CSI_4X] = &pll_csi_4x_clk.common.hw,
>> + [CLK_PLL_AUDIO_DIV2] = &pll_audio_div2_clk.common.hw,
>> + [CLK_PLL_AUDIO_DIV5] = &pll_audio_div5_clk.common.hw,
>> + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.common.hw,
>> + [CLK_PLL_AUDIO_1X] = &pll_audio_1x_clk.common.hw,
>> + [CLK_PLL_NPU_4X] = &pll_npu_4x_clk.common.hw,
>> + [CLK_CPU] = &cpu_clk.common.hw,
>> + [CLK_CPU_AXI] = &cpu_axi_clk.common.hw,
>> + [CLK_CPU_APB] = &cpu_apb_clk.common.hw,
>> + [CLK_AHB] = &ahb_clk.common.hw,
>> + [CLK_APB0] = &apb0_clk.common.hw,
>> + [CLK_APB1] = &apb1_clk.common.hw,
>> + [CLK_MBUS] = &mbus_clk.hw,
>> + [CLK_DE] = &de_clk.common.hw,
>> + [CLK_BUS_DE] = &bus_de_clk.common.hw,
>> + [CLK_G2D] = &g2d_clk.common.hw,
>> + [CLK_BUS_G2D] = &bus_g2d_clk.common.hw,
>> + [CLK_CE] = &ce_clk.common.hw,
>> + [CLK_BUS_CE] = &bus_ce_clk.common.hw,
>> + [CLK_VE] = &ve_clk.common.hw,
>> + [CLK_BUS_VE] = &bus_ve_clk.common.hw,
>> + [CLK_NPU] = &npu_clk.common.hw,
>> + [CLK_BUS_NPU] = &bus_npu_clk.common.hw,
>> + [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
>> + [CLK_BUS_MSGBOX0] = &bus_msgbox0_clk.common.hw,
>> + [CLK_BUS_MSGBOX1] = &bus_msgbox1_clk.common.hw,
>> + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
>> + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
>> + [CLK_AVS] = &avs_clk.common.hw,
>> + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
>> + [CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
>> + [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
>> + [CLK_DRAM] = &dram_clk.common.hw,
>> + [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
>> + [CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
>> + [CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
>> + [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
>> + [CLK_MBUS_ISP] = &mbus_isp_clk.common.hw,
>> + [CLK_MBUS_G2D] = &mbus_g2d_clk.common.hw,
>> + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
>> + [CLK_MMC0] = &mmc0_clk.common.hw,
>> + [CLK_MMC1] = &mmc1_clk.common.hw,
>> + [CLK_MMC2] = &mmc2_clk.common.hw,
>> + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
>> + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
>> + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
>> + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
>> + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
>> + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
>> + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
>> + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
>> + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
>> + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
>> + [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
>> + [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
>> + [CLK_SPI0] = &spi0_clk.common.hw,
>> + [CLK_SPI1] = &spi1_clk.common.hw,
>> + [CLK_SPI2] = &spi2_clk.common.hw,
>> + [CLK_SPI3] = &spi3_clk.common.hw,
>> + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
>> + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
>> + [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
>> + [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw,
>> + [CLK_SPIF] = &spif_clk.common.hw,
>> + [CLK_BUS_SPIF] = &bus_spif_clk.common.hw,
>> + [CLK_EMAC_25M] = &emac_25M_clk.common.hw,
>> + [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
>> + [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
>> + [CLK_BUS_THS] = &bus_ths_clk.common.hw,
>> + [CLK_I2S0] = &i2s0_clk.common.hw,
>> + [CLK_I2S1] = &i2s1_clk.common.hw,
>> + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
>> + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
>> + [CLK_DMIC] = &dmic_clk.common.hw,
>> + [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
>> + [CLK_AUDIO_CODEC_DAC] = &audio_codec_dac_clk.common.hw,
>> + [CLK_AUDIO_CODEC_ADC] = &audio_codec_adc_clk.common.hw,
>> + [CLK_BUS_AUDIO_CODEC] = &bus_audio_codec_clk.common.hw,
>> + [CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
>> + [CLK_BUS_OHCI] = &bus_ohci_clk.common.hw,
>> + [CLK_BUS_EHCI] = &bus_ehci_clk.common.hw,
>> + [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
>> + [CLK_BUS_DPSS_TOP] = &bus_dpss_top_clk.common.hw,
>> + [CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
>> + [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
>> + [CLK_TCON_LCD] = &tcon_lcd_clk.common.hw,
>> + [CLK_BUS_TCON_LCD] = &bus_tcon_lcd_clk.common.hw,
>> + [CLK_CSI_TOP] = &csi_top_clk.common.hw,
>> + [CLK_CSI_MCLK0] = &csi_mclk0_clk.common.hw,
>> + [CLK_CSI_MCLK1] = &csi_mclk1_clk.common.hw,
>> + [CLK_CSI_MCLK2] = &csi_mclk2_clk.common.hw,
>> + [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
>> + [CLK_BUS_WIEGAND] = &bus_wiegand_clk.common.hw,
>> + [CLK_RISCV] = &riscv_clk.common.hw,
>> + [CLK_RISCV_AXI] = &riscv_axi_clk.common.hw,
>> + [CLK_RISCV_CORE_GATE]   = &riscv_core_gate.common.hw,
>> + [CLK_RISCV_CFG_GATE]    = &riscv_cfg_gate.common.hw,
>> + [CLK_FANOUT_24M] = &fanout_24M_clk.common.hw,
>> + [CLK_FANOUT_16M] = &fanout_16M_clk.common.hw,
>> + [CLK_FANOUT_12M] = &fanout_12M_clk.common.hw,
>> + [CLK_FANOUT_25M] = &fanout_25M_clk.common.hw,
>> + [CLK_FANOUT_27M] = &fanout_27M_clk.common.hw,
>> + [CLK_FANOUT_PCLK] = &fanout_pclk_clk.common.hw,
>> + [CLK_FANOUT0] = &fanout0_clk.common.hw,
>> + [CLK_FANOUT1] = &fanout1_clk.common.hw,
>> + [CLK_FANOUT2] = &fanout2_clk.common.hw,
>> + },
>> +};
>> +
>> +static struct ccu_reset_map sun8i_v853_ccu_resets[] = {
>> + [RST_MBUS] = { 0x540, BIT(30) },
>> + [RST_BUS_DE] = { 0x60c, BIT(16) },
>> + [RST_BUS_G2D] = { 0x63c, BIT(16) },
>> + [RST_BUS_CE] = { 0x68c, BIT(16) | BIT(17)},
>> + [RST_BUS_VE] = { 0x69c, BIT(16) },
>> + [RST_BUS_NPU] = { 0x6ec, BIT(16) },
>> + [RST_BUS_DMA] = { 0x70c, BIT(16) },
>> + [RST_BUS_MSGBOX0] = { 0x71c, BIT(16) },
>> + [RST_BUS_MSGBOX1] = { 0x71c, BIT(17) },
>> + [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
>> + [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
>> + [RST_BUS_DBG] = { 0x78c, BIT(16) },
>> + [RST_BUS_PWM] = { 0x7ac, BIT(16) },
>> + [RST_BUS_DRAM] = { 0x80c, BIT(16) },
>> + [RST_BUS_MMC0] = { 0x84c, BIT(16) },
>> + [RST_BUS_MMC1] = { 0x84c, BIT(17) },
>> + [RST_BUS_MMC2] = { 0x84c, BIT(18) },
>> + [RST_BUS_UART0] = { 0x90c, BIT(16) },
>> + [RST_BUS_UART1] = { 0x90c, BIT(17) },
>> + [RST_BUS_UART2] = { 0x90c, BIT(18) },
>> + [RST_BUS_UART3] = { 0x90c, BIT(19) },
>> + [RST_BUS_I2C0] = { 0x91c, BIT(16) },
>> + [RST_BUS_I2C1] = { 0x91c, BIT(17) },
>> + [RST_BUS_I2C2] = { 0x91c, BIT(18) },
>> + [RST_BUS_I2C3] = { 0x91c, BIT(19) },
>> + [RST_BUS_I2C4] = { 0x91c, BIT(20) },
>> + [RST_BUS_SPI0] = { 0x96c, BIT(16) },
>> + [RST_BUS_SPI1] = { 0x96c, BIT(17) },
>> + [RST_BUS_SPI2] = { 0x96c, BIT(18) },
>> + [RST_BUS_SPI3] = { 0x96c, BIT(19) },
>> + [RST_BUS_SPIF] = { 0x96c, BIT(20) },
>> + [RST_BUS_EMAC] = { 0x97c, BIT(16) },
>> + [RST_BUS_GPADC] = { 0x9ec, BIT(16) },
>> + [RST_BUS_THS] = { 0x9fc, BIT(16) },
>> + [RST_BUS_I2S0] = { 0xa20, BIT(16) },
>> + [RST_BUS_I2S1] = { 0xa20, BIT(17) },
>> + [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
>> + [RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) },
>> + [RST_USB_PHY] = { 0xa70, BIT(30) },
>> + [RST_BUS_OHCI] = { 0xa8c, BIT(16) },
>> + [RST_BUS_EHCI] = { 0xa8c, BIT(20) },
>> + [RST_BUS_OTG] = { 0xa8c, BIT(24) },
>> + [RST_BUS_DPSS_TOP] = { 0xabc, BIT(16) },
>> + [RST_BUS_MIPI_DSI] = { 0xb4c, BIT(16) },
>> + [RST_BUS_TCON_LCD] = { 0xb7c, BIT(16) },
>> + [RST_BUS_CSI] = { 0xc2c, BIT(16) },
>> + [RST_BUS_WIEGAND] = { 0xc7c, BIT(16) },
>> + [RST_RISCV_SYS_APB] = { 0xd04, BIT(2), CCU_FEATURE_KEY_FIELD },
>> + [RST_RISCV_SOFT] = { 0xd04, BIT(1), CCU_FEATURE_KEY_FIELD },
>> + [RST_RISCV_CFG] = { 0xd0c, BIT(16) }
>> +};
>> +
>> +static const struct sunxi_ccu_desc sun8i_v853_ccu_desc = {
>> + .ccu_clks = sun8i_v853_ccu_clks,
>> + .num_ccu_clks = ARRAY_SIZE(sun8i_v853_ccu_clks),
>> +
>> + .hw_clks = &sun8i_v853_hw_clks,
>> +
>> + .resets = sun8i_v853_ccu_resets,
>> + .num_resets = ARRAY_SIZE(sun8i_v853_ccu_resets),
>> +};
>> +
>> +static const u32 pll_regs[] = {
>> + SUN8I_V853_PLL_CPU_REG,
>> + SUN8I_V853_PLL_DDR_REG,
>> + SUN8I_V853_PLL_PERIPH_REG,
>> + SUN8I_V853_PLL_VIDEO_REG,
>> + SUN8I_V853_PLL_CSI_REG,
>> + SUN8I_V853_PLL_AUDIO_REG,
>> + SUN8I_V853_PLL_NPU_REG,
>> +};
>> +
>> +static int sun8i_v853_ccu_probe(struct platform_device *pdev)
>> +{
>> + void __iomem *reg;
>> + u32 val;
>> + int i, ret;
>> +
>> + reg = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(reg))
>> + return PTR_ERR(reg);
>> +
>> + /* Enable the enable, LDO, and lock bits on all PLLs. */
>> + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
>> + val = readl(reg + pll_regs[i]);
>> + val |= BIT(31) | BIT(30) | BIT(29);
>> + writel(val, reg + pll_regs[i]);
>> + }
>> +
>> + /* Force PLL_CPU factor M to 0. */
>> + val = readl(reg + SUN8I_V853_PLL_CPU_REG);
>> + val &= ~GENMASK(1, 0);
>> + writel(val, reg + SUN8I_V853_PLL_CPU_REG);
>> +
>> + /*
>> + * Force OHCI 12M clock source to 00 (12MHz divided from 48MHz)
>> + *
>> + * This clock mux is still mysterious, and the code just enforces
>> + * it to have a valid clock parent.
>> + */
>> + val = readl(reg + SUN8I_V853_USB_CLK_REG);
>> + val &= ~GENMASK(25, 24);
>> + writel(val, reg + SUN8I_V853_USB_CLK_REG);
>> +
>> + /* Force fanout-27M factor N to 0. */
>> + val = readl(reg + SUN8I_V853_FANOUT_27M_REG);
>> + val &= ~GENMASK(9, 8);
>> + writel(val, reg + SUN8I_V853_FANOUT_27M_REG);
>> +
>> + ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_v853_ccu_desc);
>> + if (ret)
>> + return ret;
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id sun8i_v853_ccu_ids[] = {
>> + { .compatible = "allwinner,sun8i-v853-ccu" },
>> + { }
>> +};
>> +
>> +static struct platform_driver sun8i_v853_ccu_driver = {
>> + .probe = sun8i_v853_ccu_probe,
>> + .driver = {
>> + .name = "sun8i-v853-ccu",
>> + .suppress_bind_attrs = true,
>> + .of_match_table = sun8i_v853_ccu_ids,
>> + },
>> +};
>> +module_platform_driver(sun8i_v853_ccu_driver);
>> +
>> +MODULE_IMPORT_NS("SUNXI_CCU");
>> +MODULE_DESCRIPTION("Support for the Allwinner V853 CCU");
>> +MODULE_LICENSE("GPL");
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853.h b/drivers/clk/sunxi-ng/ccu-sun8i-v853.h
>> new file mode 100644
>> index 000000000000..f1b2a4d0bcd3
>> --- /dev/null
>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853.h
>> @@ -0,0 +1,14 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com>
>> + */
>> +
>> +#ifndef _CCU_SUN8I_V853_H_
>> +#define _CCU_SUN8I_V853_H_
>> +
>> +#include <dt-bindings/clock/allwinner,sun8i-v853-ccu.h>
>> +#include <dt-bindings/reset/allwinner,sun8i-v853-ccu.h>
>> +
>> +#define CLK_NUMBER (CLK_FANOUT2 + 1)
>> +
>> +#endif
>> 
> 
> 
> 
> 

Re: [PATCH v2 04/10] clk: sunxi-ng: add CCU drivers for V853

[Jernej Škrabec]

Dne četrtek, 20. februar 2025 ob 10:28:43 Srednjeevropski standardni čas je András Szemző napisal(a):
> Hi,
> 
> Thanks for your review!
> 
> > On 19 Feb 2025, at 21:21, Jernej Škrabec <jernej.skrabec@gmail.com> wrote:
> > 
> > Dne sreda, 5. februar 2025 ob 13:52:19 Srednjeevropski standardni čas je Andras Szemzo napisal(a):
> >> V853 has similar gates/resets like existing Allwinner SOCs. Add support for it's CCU and PRCM CCU.
> >> 
> >> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
> >> ---
> >> drivers/clk/sunxi-ng/Kconfig            |   10 +
> >> drivers/clk/sunxi-ng/Makefile           |    4 +
> >> drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c |  120 +++
> >> drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h |   14 +
> >> drivers/clk/sunxi-ng/ccu-sun8i-v853.c   | 1145 +++++++++++++++++++++++
> >> drivers/clk/sunxi-ng/ccu-sun8i-v853.h   |   14 +
> >> 6 files changed, 1307 insertions(+)
> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.c
> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v853.h
> >> 
> >> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> >> index b547198a2c65..e257373177e0 100644
> >> --- a/drivers/clk/sunxi-ng/Kconfig
> >> +++ b/drivers/clk/sunxi-ng/Kconfig
> >> @@ -12,6 +12,16 @@ config SUNIV_F1C100S_CCU
> >> default y
> >> depends on MACH_SUNIV || COMPILE_TEST
> >> 
> >> +config SUN8I_V853_CCU
> >> + tristate "Support for the Allwinner V853/V851s/V851SE CCU"
> >> + default MACH_SUN8I
> >> + depends on MACH_SUN8I || COMPILE_TEST
> >> +
> >> +config SUN8I_V853_R_CCU
> >> + tristate "Support for the Allwinner V853/V851s/V851SE PRCM CCU"
> >> + default MACH_SUN8I
> >> + depends on MACH_SUN8I || COMPILE_TEST
> > 
> > Generally, this are two patches, one for each driver.
> > 
> >> +
> >> config SUN20I_D1_CCU
> >> tristate "Support for the Allwinner D1/R528/T113 CCU"
> >> default y
> >> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> >> index 6b3ae2b620db..b87928462e15 100644
> >> --- a/drivers/clk/sunxi-ng/Makefile
> >> +++ b/drivers/clk/sunxi-ng/Makefile
> >> @@ -25,6 +25,8 @@ sunxi-ccu-y += ccu_mp.o
> >> 
> >> # SoC support
> >> obj-$(CONFIG_SUNIV_F1C100S_CCU) += suniv-f1c100s-ccu.o
> >> +obj-$(CONFIG_SUN8I_V853_CCU) += sun8i-v853-ccu.o
> >> +obj-$(CONFIG_SUN8I_V853_R_CCU) += sun8i-v853-r-ccu.o
> > 
> > Put it to other sun8i drivers.
> > 
> >> obj-$(CONFIG_SUN20I_D1_CCU) += sun20i-d1-ccu.o
> >> obj-$(CONFIG_SUN20I_D1_R_CCU) += sun20i-d1-r-ccu.o
> >> obj-$(CONFIG_SUN50I_A64_CCU) += sun50i-a64-ccu.o
> >> @@ -50,6 +52,8 @@ obj-$(CONFIG_SUN9I_A80_CCU) += sun9i-a80-de-ccu.o
> >> obj-$(CONFIG_SUN9I_A80_CCU) += sun9i-a80-usb-ccu.o
> >> 
> >> suniv-f1c100s-ccu-y += ccu-suniv-f1c100s.o
> >> +sun8i-v853-ccu-y += ccu-sun8i-v853.o
> >> +sun8i-v853-r-ccu-y += ccu-sun8i-v853-r.o
> > 
> > Ditto.
> > 
> 
> ok
> 
> >> sun20i-d1-ccu-y += ccu-sun20i-d1.o
> >> sun20i-d1-r-ccu-y += ccu-sun20i-d1-r.o
> >> sun50i-a64-ccu-y += ccu-sun50i-a64.o
> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
> >> new file mode 100644
> >> index 000000000000..bd60e00cda7f
> >> --- /dev/null
> >> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.c
> >> @@ -0,0 +1,120 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
> >> + *
> >> + * Based on ccu-sun20i-d1-r.c by Samuel Holland.
> >> + */
> >> +
> >> +#include <linux/clk-provider.h>
> >> +#include <linux/module.h>
> >> +#include <linux/platform_device.h>
> >> +
> >> +#include "ccu_common.h"
> >> +#include "ccu_reset.h"
> >> +
> >> +#include "ccu_gate.h"
> >> +#include "ccu_mp.h"
> >> +
> >> +#include "ccu-sun8i-v853-r.h"
> >> +
> >> +static const struct clk_parent_data r_ahb_apb0_parents[] = {
> >> + { .fw_name = "hosc" },
> >> + { .fw_name = "losc" },
> >> + { .fw_name = "iosc" },
> >> + { .fw_name = "pll-periph" },
> >> + { .fw_name = "pll-audio" }
> >> +};
> >> +
> >> +static SUNXI_CCU_MP_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
> >> +  r_ahb_apb0_parents, 0x000,
> >> +  0, 5, /* M */
> >> +  8, 2, /* P */
> >> +  24, 3, /* mux */
> >> +  0);
> >> +static const struct clk_hw *r_ahb_hw = &r_ahb_clk.common.hw;
> >> +
> >> +static SUNXI_CCU_MP_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
> >> +  r_ahb_apb0_parents, 0x00c,
> >> +  0, 5, /* M */
> >> +  8, 2, /* P */
> >> +  24, 3, /* mux */
> >> +  0);
> >> +static const struct clk_hw *r_apb0_hw = &r_apb0_clk.common.hw;
> > 
> > Where can I look for above clocks? There are not described in BSP driver.
> > 
> 
> As the original BSP’s PRCM driver has an unacceptable licence, I had to rewrite this driver.  This IP block
> isn’t documented in the V853 manual, so as Andre suggested, I used the A523 manual, and the D1/T113
> PRCM driver. Than I peek/poke the registers to check if it’s valid or not. 
> 
> awboot> read32 0x701000c
> 0x0701000c: 0x0f00031f
> awboot> read32 0x7010000
> 0x07010000: 0x00000000
> awboot> write32 0x7010000 0xffffffff
> awboot> read32 0x7010000
> 0x07010000: 0x0700031f
> 
> They are there, I’m not sure about it’s usage.

Ok, so they exist and format is ok too. Only question is if parents are correct.
I checked ccu-sun8iw20-r.c from one BSP and it has similar clocks. However,
it's missing pll-audio and pll-periph is pre-divided by 3, which is same as on
A523.

So my suggestion is to remove pll-audio and adjust pll-periph to have
predivider.

> 
> 
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_r_twd_clk, "bus-r-twd", &r_apb0_hw, 
> >> +  0x12c, BIT(0), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_hw,
> >> +  0x1ac, BIT(0), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_r_rtc_clk, "bus-r-rtc", &r_ahb_hw,
> >> +  0x20c, BIT(0), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_r_cpucfg_clk, "bus-r-cpucfg", &r_apb0_hw,
> >> +  0x22c, BIT(0), 0);
> >> +
> >> +static struct ccu_common *sun8i_v853_r_ccu_clks[] = {
> >> + &r_ahb_clk.common,
> >> + &r_apb0_clk.common,
> >> + &bus_r_twd_clk.common,
> >> + &bus_r_ppu_clk.common,
> >> + &bus_r_rtc_clk.common,
> >> + &bus_r_cpucfg_clk.common,
> >> +};
> >> +
> >> +static struct clk_hw_onecell_data sun8i_v853_r_hw_clks = {
> >> + .num = CLK_NUMBER,
> >> + .hws = {
> >> + [CLK_R_AHB] = &r_ahb_clk.common.hw,
> >> + [CLK_R_APB0] = &r_apb0_clk.common.hw,
> >> + [CLK_BUS_R_TWD] = &bus_r_twd_clk.common.hw,
> >> + [CLK_BUS_R_PPU] = &bus_r_ppu_clk.common.hw,
> >> + [CLK_BUS_R_RTC] = &bus_r_rtc_clk.common.hw,
> >> + [CLK_BUS_R_CPUCFG] = &bus_r_cpucfg_clk.common.hw,
> >> + },
> >> +};
> >> +
> >> +static const struct ccu_reset_map sun8i_v853_r_ccu_resets[] = {
> >> + [RST_BUS_R_TWD] = { 0x12c, BIT(16) },
> > 
> > Where did you get that? BSP driver that I checked doesn't mentions it.
> > 
> 
> yes, just double checked and this bit is not valid, sorry, I’ll remove it.
> 
> >> + [RST_BUS_R_PPU] = { 0x1ac, BIT(16) },
> >> + [RST_BUS_R_RTC] = { 0x20c, BIT(16) },
> >> + [RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
> >> +};
> >> +
> >> +static const struct sunxi_ccu_desc sun8i_v853_r_ccu_desc = {
> >> + .ccu_clks = sun8i_v853_r_ccu_clks,
> >> + .num_ccu_clks = ARRAY_SIZE(sun8i_v853_r_ccu_clks),
> >> +
> >> + .hw_clks = &sun8i_v853_r_hw_clks,
> >> +
> >> + .resets = sun8i_v853_r_ccu_resets,
> >> + .num_resets = ARRAY_SIZE(sun8i_v853_r_ccu_resets),
> >> +};
> >> +
> >> +static int sun8i_v853_r_ccu_probe(struct platform_device *pdev)
> >> +{
> >> + void __iomem *reg;
> >> +
> >> + reg = devm_platform_ioremap_resource(pdev, 0);
> >> + if (IS_ERR(reg))
> >> + return PTR_ERR(reg);
> >> +
> >> + return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_v853_r_ccu_desc);
> >> +}
> >> +
> >> +static const struct of_device_id sun8i_v853_r_ccu_ids[] = {
> >> + { .compatible = "allwinner,sun8i-v853-r-ccu" },
> >> + { }
> >> +};
> >> +MODULE_DEVICE_TABLE(of, sun8i_v853_r_ccu_ids);
> >> +
> >> +static struct platform_driver sun8i_v853_r_ccu_driver = {
> >> + .probe = sun8i_v853_r_ccu_probe,
> >> + .driver = {
> >> + .name = "sun8i-v853-r-ccu",
> >> + .suppress_bind_attrs = true,
> >> + .of_match_table = sun8i_v853_r_ccu_ids,
> >> + },
> >> +};
> >> +module_platform_driver(sun8i_v853_r_ccu_driver);
> >> +
> >> +MODULE_IMPORT_NS("SUNXI_CCU");
> >> +MODULE_DESCRIPTION("Support for the Allwinner V853 PRCM CCU");
> >> +MODULE_LICENSE("GPL");
> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
> >> new file mode 100644
> >> index 000000000000..2c6cc7b6f251
> >> --- /dev/null
> >> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853-r.h
> >> @@ -0,0 +1,14 @@
> >> +/* SPDX-License-Identifier: GPL-2.0 */
> >> +/*
> >> + * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
> >> + */
> >> +
> >> +#ifndef _CCU_SUN8I_V853_R_H
> >> +#define _CCU_SUN8I_V853_R_H
> >> +
> >> +#include <dt-bindings/clock/allwinner,sun8i-v853-r-ccu.h>
> >> +#include <dt-bindings/reset/allwinner,sun8i-v853-r-ccu.h>
> >> +
> >> +#define CLK_NUMBER (CLK_BUS_R_CPUCFG + 1)
> >> +
> >> +#endif
> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853.c b/drivers/clk/sunxi-ng/ccu-sun8i-v853.c
> >> new file mode 100644
> >> index 000000000000..4b32f3a913cf
> >> --- /dev/null
> >> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853.c
> >> @@ -0,0 +1,1145 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright (C) 2025 Andras Szemzo <szemzo.andras@gmail.com>
> >> + *
> >> + * Based on ccu-sun20i-d1.c by Samuel Holland.
> >> + */
> >> +
> >> +#include <linux/clk-provider.h>
> >> +#include <linux/io.h>
> >> +#include <linux/module.h>
> >> +#include <linux/platform_device.h>
> >> +
> >> +#include "../clk.h"
> >> +
> >> +#include "ccu_common.h"
> >> +#include "ccu_reset.h"
> >> +
> >> +#include "ccu_div.h"
> >> +#include "ccu_gate.h"
> >> +#include "ccu_mp.h"
> >> +#include "ccu_mult.h"
> >> +#include "ccu_nk.h"
> >> +#include "ccu_nkm.h"
> >> +#include "ccu_nkmp.h"
> >> +#include "ccu_nm.h"
> >> +
> >> +#include "ccu-sun8i-v853.h"
> >> +
> >> +static const struct clk_parent_data osc24M[] = {
> >> + { .fw_name = "hosc" }
> >> +};
> >> +
> >> +/*
> >> + * For the CPU PLL, the output divider is described as "only for testing"
> >> + * in the user manual. So it's not modelled and forced to 0.
> >> + */
> >> +#define SUN8I_V853_PLL_CPU_REG 0x000
> >> +
> >> +static struct ccu_mult pll_cpu_clk = {
> >> + .enable = BIT(27),
> >> + .lock = BIT(28),
> >> + .mult = _SUNXI_CCU_MULT_MIN(8, 8, 11),
> >> + .common = {
> >> + .reg = 0x000,
> >> + .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-cpu", osc24M,
> >> +   &ccu_mult_ops,
> >> +   CLK_SET_RATE_GATE),
> >> + },
> >> +};
> >> +
> >> +/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
> >> +#define SUN8I_V853_PLL_DDR_REG 0x010
> >> +static struct ccu_nkmp pll_ddr_clk = {
> >> + .enable = BIT(27),
> >> + .lock = BIT(28),
> >> + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
> >> + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
> >> + .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
> >> + .common = {
> >> + .reg = 0x010,
> >> + .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr", osc24M,
> >> +   &ccu_nkmp_ops,
> >> +   CLK_SET_RATE_GATE),
> >> + },
> >> +};
> >> +
> >> +#define SUN8I_V853_PLL_PERIPH_REG 0x020
> >> +static struct ccu_nm pll_periph_4x_clk = {
> >> + .enable = BIT(27),
> >> + .lock = BIT(28),
> >> + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
> >> + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
> >> + .common = {
> >> + .reg = 0x020,
> >> + .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph-4x", osc24M,
> >> +   &ccu_nm_ops,
> >> +   CLK_SET_RATE_GATE),
> >> + },
> >> +};
> >> +
> >> +static const struct clk_hw *pll_periph_4x_hws[] = {
> >> + &pll_periph_4x_clk.common.hw
> >> +};
> >> +
> >> +static SUNXI_CCU_M_HWS(pll_periph_2x_clk, "pll-periph-2x", pll_periph_4x_hws,
> >> +       0x020, 16, 3, 0);
> >> +
> >> +static SUNXI_CCU_M_HWS(pll_periph_800M_clk, "pll-periph-800M", pll_periph_4x_hws,
> >> +       0x020, 20, 3, 0);
> >> +
> >> +static SUNXI_CCU_M_HWS(pll_periph_480M_clk, "pll-periph-480M", pll_periph_4x_hws,
> >> +       0x020, 2, 3, 0);
> >> +
> >> +static CLK_FIXED_FACTOR_HW(pll_periph_600M_clk, "pll-periph-600M",
> >> +   &pll_periph_2x_clk.common.hw, 2, 1, 0);
> >> +
> >> +static CLK_FIXED_FACTOR_HW(pll_periph_400M_clk, "pll-periph-400M",
> >> +   &pll_periph_2x_clk.common.hw, 3, 1, 0);
> >> +
> >> +static CLK_FIXED_FACTOR_HW(pll_periph_300M_clk, "pll-periph-300M",
> >> +   &pll_periph_600M_clk.hw, 2, 1, 0);
> >> +
> >> +static CLK_FIXED_FACTOR_HW(pll_periph_200M_clk, "pll-periph-200M",
> >> +   &pll_periph_400M_clk.hw, 2, 1, 0);
> >> +
> >> +static CLK_FIXED_FACTOR_HW(pll_periph_160M_clk, "pll-periph-160M",
> >> +   &pll_periph_480M_clk.common.hw, 3, 1, 0);
> >> +
> >> +static CLK_FIXED_FACTOR_HW(pll_periph_150M_clk, "pll-periph-150M",
> >> +   &pll_periph_300M_clk.hw, 2, 1, 0);
> >> +
> >> +/*
> >> + * For Video PLLs, the output divider is described as "only for testing"
> >> + * in the user manual.
> >> + */
> >> +#define SUN8I_V853_PLL_VIDEO_REG 0x040
> >> +static struct ccu_nkmp pll_video_4x_clk = {
> >> + .enable = BIT(27),
> >> + .lock = BIT(28),
> >> + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
> >> + .p = _SUNXI_CCU_DIV(1, 1), /* input divider */
> >> + .common = {
> >> + .reg = 0x040,
> >> + .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video-4x", osc24M,
> >> +   &ccu_nkmp_ops,
> >> +   CLK_SET_RATE_GATE),
> >> + },
> >> +};
> >> +
> >> +static const struct clk_hw *pll_video_4x_hws[] = {
> >> + &pll_video_4x_clk.common.hw
> >> +};
> >> +static CLK_FIXED_FACTOR_HWS(pll_video_2x_clk, "pll-video-2x",
> >> +    pll_video_4x_hws, 2, 1, CLK_SET_RATE_PARENT);
> >> +static CLK_FIXED_FACTOR_HWS(pll_video_1x_clk, "pll-video-1x",
> >> +    pll_video_4x_hws, 4, 1, CLK_SET_RATE_PARENT);
> >> +
> >> +
> >> +/*
> >> + * For CSI PLLs, the output divider is described as "only for testing"
> >> + * in the user manual.
> >> + */
> >> +#define SUN8I_V853_PLL_CSI_REG 0x048
> >> +static struct ccu_nkmp pll_csi_4x_clk = {
> >> + .enable = BIT(27),
> >> + .lock = BIT(28),
> >> + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
> >> + .p = _SUNXI_CCU_DIV(1, 1), /* input divider */
> >> + .common = {
> >> + .reg = 0x048,
> >> + .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-csi-4x", osc24M,
> >> +   &ccu_nkmp_ops,
> >> +   CLK_SET_RATE_GATE),
> >> + },
> >> +};
> >> +
> >> +static CLK_FIXED_FACTOR_HW(pll_csi_clk, "pll-csi",
> >> +   &pll_csi_4x_clk.common.hw, 4, 1, CLK_SET_RATE_PARENT);
> >> +
> >> +
> >> +#define SUN8I_V853_PLL_AUDIO_REG 0x078
> >> +static struct ccu_sdm_setting pll_audio_div5_sdm_table[] = {
> >> + { .rate = 196608000, .pattern = 0xc001eb85, .m = 5, .n = 40 }, /* 24.576 */
> >> + { .rate = 67737600, .pattern = 0xc001288d, .m = 8, .n = 22 }, /* 22.5792 */
> >> +};
> >> +
> >> +static struct ccu_nm pll_audio_div5_clk = {
> >> + .enable = BIT(27),
> >> + .lock           = BIT(28),
> >> + .n              = _SUNXI_CCU_MULT(8, 8),
> >> + .m              = _SUNXI_CCU_DIV(20, 3),
> >> + .sdm            = _SUNXI_CCU_SDM(pll_audio_div5_sdm_table,
> >> +    BIT(24), 0x0178, BIT(31)),
> >> + .common         = {
> >> + .reg            = 0x0078,
> >> + .features       = CCU_FEATURE_SIGMA_DELTA_MOD,
> >> + .hw.init        = CLK_HW_INIT_PARENTS_DATA("pll-audio-div5", osc24M,
> >> +   &ccu_nm_ops,
> >> +   CLK_SET_RATE_UNGATE),
> >> + },
> >> +};
> >> +
> >> +static const struct clk_hw *pll_audio_div5_hws[] = {
> >> + &pll_audio_div5_clk.common.hw
> >> +};
> >> +
> >> +static SUNXI_CCU_M_HWS(pll_audio_1x_clk, "pll-audio-1x", pll_audio_div5_hws,
> >> +       0xe00, 0, 5, CLK_SET_RATE_PARENT);
> >> +
> >> +/* pll-audio-div2 and pll-audio-4x not used, because pll-audio-1x can cover 
> >> + * 22.5792M and 24.576M 
> >> + */
> >> +static SUNXI_CCU_M(pll_audio_div2_clk, "pll-audio-div2", "pll-audio",
> >> +   0x078, 16, 3, 0);
> >> +static SUNXI_CCU_M(pll_audio_4x_clk, "pll-audio-4x", "pll-audio-div2",
> >> +   0xe00, 5, 5, 0);
> >> +
> >> +/*
> >> + * For the NPU PLL, the output divider is described as "only for testing"
> >> + * in the user manual.
> >> + */
> >> +#define SUN8I_V853_PLL_NPU_REG 0x080
> >> +static struct ccu_nkmp pll_npu_4x_clk = {
> >> + .enable = BIT(27),
> >> + .lock = BIT(28),
> >> + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
> >> + .p = _SUNXI_CCU_DIV(1, 1), /* input divider */
> >> + .common = {
> >> + .reg = 0x080,
> >> + .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-npu-4x", osc24M,
> >> +   &ccu_nkmp_ops,
> >> +   CLK_SET_RATE_UNGATE),
> >> + },
> >> +};
> >> +
> >> +/*
> >> + * The CPU gate is not modelled - it is in a separate register (0x504)
> >> + * and has a special key field. The clock must not be gated anyway by
> >> + * the kernel.
> >> + */
> >> +static const struct clk_parent_data cpu_parents[] = {
> >> + { .fw_name = "hosc" },
> >> + { .fw_name = "losc" },
> >> + { .fw_name = "iosc" },
> >> + { .hw = &pll_cpu_clk.common.hw },
> >> + { .hw = &pll_periph_600M_clk.hw },
> >> + { .hw = &pll_periph_800M_clk.common.hw },
> >> +};
> >> +
> >> +/*
> >> + * There is a P factor (PLL_OUT_EXT_DIVP[17:16]) in this register, but it is not modeled.
> >> + * The manual states that it should be used only, when the output clock is less than 288 MHz.
> >> + */
> >> +static SUNXI_CCU_MUX_DATA(cpu_clk, "cpu", cpu_parents,
> >> +  0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
> >> +
> >> +static const struct clk_hw *cpu_hws[] = { &cpu_clk.common.hw };
> >> +
> >> +static SUNXI_CCU_M_HWS(cpu_axi_clk, "cpu-axi", cpu_hws,
> >> +       0x500, 0, 2, 0);
> >> +static SUNXI_CCU_M_HWS(cpu_apb_clk, "cpu-apb", cpu_hws,
> >> +       0x500, 8, 2, 0);
> >> +
> >> +static const struct clk_parent_data ahb_parents[] = {
> >> + { .fw_name = "hosc" },
> >> + { .fw_name = "losc" },
> >> + { .fw_name = "iosc" },
> >> + { .hw = &pll_periph_600M_clk.hw },
> >> +};
> >> +static SUNXI_CCU_MP_DATA_WITH_MUX(ahb_clk, "ahb", ahb_parents, 0x510,
> >> +  0, 5, /* M */
> >> +  8, 2, /* P */
> >> +  24, 2, /* mux */
> >> +  0);
> >> +
> >> +static SUNXI_CCU_MP_DATA_WITH_MUX(apb0_clk, "apb0", ahb_parents, 0x520,
> >> +  0, 5, /* M */
> >> +  8, 2, /* P */
> >> +  24, 2, /* mux */
> >> +  0);
> >> +
> >> +static SUNXI_CCU_MP_DATA_WITH_MUX(apb1_clk, "apb1", ahb_parents, 0x524,
> >> +  0, 5, /* M */
> >> +  8, 2, /* P */
> >> +  24, 2, /* mux */
> >> +  0);
> >> +
> >> +static const struct clk_hw *ahb_hws[] = { &ahb_clk.common.hw };
> >> +static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw };
> >> +static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw };
> >> +
> >> +
> >> +static const struct clk_hw *de_g2d_parents[] = {
> >> + &pll_periph_300M_clk.hw,
> >> + &pll_video_1x_clk.hw,
> >> +};
> >> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_g2d_parents, 0x600,
> >> +    0, 5, /* M */
> >> +    24, 1, /* mux */
> >> +    BIT(31), /* gate */
> >> +    CLK_SET_RATE_PARENT);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", ahb_hws,
> >> +  0x60c, BIT(0), 0);
> >> +
> >> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", de_g2d_parents, 0x630,
> >> +    0, 5, /* M */
> >> +    24, 1, /* mux */
> >> +    BIT(31), /* gate */
> >> +    CLK_SET_RATE_PARENT);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb_hws,
> >> +  0x63c, BIT(0), 0);
> >> +
> >> +
> >> +static const struct clk_parent_data ce_parents[] = {
> >> + { .fw_name = "hosc" },
> > 
> > Where this come from? V853 manual v1.1 doesn't have it.
> 
> There is a sun8iw21 ccu driver [1], where hosc is the first parent:
> 
> [1]:
> https://github.com/YuzukiHD/TinyVision/blob/main/kernel/bsp/drivers/clk/sunxi-ng/ccu-sun8iw21.c#L262
> 
> I don’t know if the manual or if this driver is the correct.

It's ok.

> 
> > 
> >> + { .hw = &pll_periph_400M_clk.hw, },
> >> + { .hw = &pll_periph_300M_clk.hw, }
> >> +};
> >> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
> >> +      0, 4, /* M */
> >> +      24, 3, /* mux */
> >> +      BIT(31), /* gate */
> >> +      CLK_SET_RATE_PARENT);
> > 
> > Set rate parent flag doesn't make sense on constant parents.
> 
> yes
> 
> > 
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", ahb_hws,
> >> +  0x68c, BIT(0) | BIT(1), 0);
> >> +
> >> +static const struct clk_hw *ve_parents[] = {
> >> + &pll_periph_300M_clk.hw,
> >> + &pll_periph_400M_clk.hw,
> >> + &pll_periph_480M_clk.common.hw,
> >> + &pll_npu_4x_clk.common.hw,
> >> + &pll_video_4x_clk.common.hw,
> >> + &pll_csi_4x_clk.common.hw,
> >> +};
> >> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
> >> +    0, 5, /* M */
> >> +    24, 3, /* mux */
> >> +    BIT(31), /* gate */
> >> +    0);
> > 
> > CLK_SET_RATE_PARENT flag? Cedrus driver set working clock at the beginning.
> > 
> 
> ok
> 
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", ahb_hws,
> >> +  0x69c, BIT(0), 0);
> >> +
> >> +
> >> +static const struct clk_hw *npu_parents[] = {
> >> + &pll_periph_480M_clk.common.hw,
> >> + &pll_periph_600M_clk.hw,
> >> + &pll_periph_800M_clk.common.hw,
> >> + &pll_npu_4x_clk.common.hw,
> >> +};
> >> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0x6e0,
> >> +    0, 5, /* M */
> >> +    24, 3, /* mux */
> >> +    BIT(31), /* gate */
> >> +    0);
> > 
> > I think CLK_SET_RATE_PARENT would also be beneficial here.
> 
> I tried to mimic how the BSP setup the NPU clocks (as I think, not sure), in the dts I setup it like:
> 
>                 npu: npu@3050000 {
>                         compatible = "vivante,gc";
>                         reg = <0x03050000 0x1000>;
>                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
>                         interrupt-names = "npu";
>                         clocks = <&ccu CLK_BUS_NPU>, <&ccu CLK_NPU>;
>                         clock-names = "bus", "core";
>                         assigned-clocks = <&ccu CLK_PLL_NPU_4X>, <&ccu CLK_NPU>;
>                         assigned-clock-parents = <&dcxo>, <&ccu CLK_PLL_NPU_4X>;
>                         assigned-clock-rates =  <1392000000>, <348000000>;
>                         resets = <&ccu RST_BUS_NPU>;
>                         iommus = <&iommu 6>;
>                         power-domains = <&ppu PD_NPU>;
>                 };
> 
> With these settings (after adding a reset support to the etnaviv driver) at least I'm able to dump some registers via debugfs.
> Do you think I should add the CLK_SET_RATE_PARENT flag?

Yes, because those assigned clock properties are not really how things should
be done.

Best regards,
Jernej

> 
> > 
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_npu_clk, "bus-npu", ahb_hws,
> >> +  0x6ec, BIT(0), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", ahb_hws,
> >> +  0x70c, BIT(0), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", ahb_hws,
> >> +  0x71c, BIT(0), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_msgbox1_clk, "bus-msgbox1", ahb_hws,
> >> +  0x71c, BIT(1), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", ahb_hws,
> >> +  0x72c, BIT(0), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", ahb_hws,
> >> +  0x73c, BIT(0), 0);
> >> +
> >> +static SUNXI_CCU_GATE_DATA(avs_clk, "avs", osc24M,
> >> +   0x740, BIT(31), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", ahb_hws,
> >> +  0x78c, BIT(0), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_pwm_clk, "bus-pwm", apb0_hws,
> >> +  0x7ac, BIT(0), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", ahb_hws,
> >> +  0x7bc, BIT(0), 0);
> >> +
> >> +static const struct clk_hw *dram_parents[] = {
> >> + &pll_ddr_clk.common.hw,
> >> + &pll_periph_2x_clk.common.hw,
> >> + &pll_periph_800M_clk.common.hw,
> >> +};
> >> +static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dram_clk, "dram", dram_parents, 0x800,
> >> +     0, 5, /* M */
> >> +     8, 2, /* P */
> >> +     24, 3, /* mux */
> >> +     BIT(31), CLK_IS_CRITICAL);
> > 
> > This clock needs update field to be set to actually apply configuration. So
> > same comment as on A523 clock version, this needs new flag to be introduced
> > for such case.
> > 
> 
> ok
> 
> >> +
> >> +static CLK_FIXED_FACTOR_HW(mbus_clk, "mbus",
> >> +   &dram_clk.common.hw, 4, 1, 0);
> >> +
> >> +static const struct clk_hw *mbus_hws[] = { &mbus_clk.hw };
> >> +
> >> +static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
> >> +  0x804, BIT(0), 0);
> >> +static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws,
> >> +  0x804, BIT(1), 0);
> >> +static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws,
> >> +  0x804, BIT(2), 0);
> >> +static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws,
> >> +  0x804, BIT(8), 0);
> >> +static SUNXI_CCU_GATE_HWS(mbus_isp_clk, "mbus-isp", mbus_hws,
> >> +  0x804, BIT(9), 0);
> >> +static SUNXI_CCU_GATE_HWS(mbus_g2d_clk, "mbus-g2d", mbus_hws,
> >> +  0x804, BIT(10), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", ahb_hws,
> >> +  0x80c, BIT(0), CLK_IS_CRITICAL);
> >> +
> >> +
> >> +static const struct clk_parent_data mmc0_mmc1_parents[] = {
> >> + { .fw_name = "hosc" },
> >> + { .hw = &pll_periph_400M_clk.hw, },
> >> + { .hw = &pll_periph_300M_clk.hw, },
> >> +};
> > 
> > Just mmc_parents.
> 
> ok
> 
> > 
> >> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830,
> >> +       0, 4, /* M */
> >> +       8, 2, /* P */
> >> +       24, 3, /* mux */
> >> +       BIT(31), /* gate */
> >> +       0);
> >> +
> >> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834,
> >> +       0, 4, /* M */
> >> +       8, 2, /* P */
> >> +       24, 3, /* mux */
> >> +       BIT(31), /* gate */
> >> +       0);
> >> +
> >> +static const struct clk_parent_data mmc2_parents[] = {
> >> + { .fw_name = "hosc" },
> >> + { .hw = &pll_periph_600M_clk.hw, },
> >> + { .hw = &pll_periph_400M_clk.hw, },
> >> +};
> >> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838,
> >> +       0, 4, /* M */
> >> +       8, 2, /* P */
> >> +       24, 3, /* mux */
> >> +       BIT(31), /* gate */
> >> +       0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", ahb_hws,
> >> +  0x84c, BIT(0), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", ahb_hws,
> >> +  0x84c, BIT(1), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", ahb_hws,
> >> +  0x84c, BIT(2), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws,
> >> +  0x90c, BIT(0), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws,
> >> +  0x90c, BIT(1), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws,
> >> +  0x90c, BIT(2), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws,
> >> +  0x90c, BIT(3), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws,
> >> +  0x91c, BIT(0), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws,
> >> +  0x91c, BIT(1), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws,
> >> +  0x91c, BIT(2), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws,
> >> +  0x91c, BIT(3), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_i2c4_clk, "bus-i2c4", apb1_hws,
> >> +  0x91c, BIT(4), 0);
> >> +
> >> +static const struct clk_parent_data spi_parents[] = {
> >> + { .fw_name = "hosc" },
> >> + { .hw = &pll_periph_300M_clk.hw, },
> >> + { .hw = &pll_periph_200M_clk.hw, },
> >> +};
> >> +
> >> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
> >> +       0, 4, /* M */
> >> +       8, 2, /* P */
> >> +       24, 3, /* mux */
> >> +       BIT(31), /* gate */
> >> +       0);
> >> +
> >> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
> >> +       0, 4, /* M */
> >> +       8, 2, /* P */
> >> +       24, 3, /* mux */
> >> +       BIT(31), /* gate */
> >> +       0);
> >> +
> >> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi2_clk, "spi2", spi_parents, 0x948,
> >> +       0, 4, /* M */
> >> +       8, 2, /* P */
> >> +       24, 3, /* mux */
> >> +       BIT(31), /* gate */
> >> +       0);
> >> +
> >> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi3_clk, "spi3", spi_parents, 0x94c,
> >> +       0, 4, /* M */
> >> +       8, 2, /* P */
> >> +       24, 3, /* mux */
> >> +       BIT(31), /* gate */
> >> +       0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", ahb_hws,
> >> +  0x96c, BIT(0), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", ahb_hws,
> >> +  0x96c, BIT(1), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_spi2_clk, "bus-spi2", ahb_hws,
> >> +  0x96c, BIT(2), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_spi3_clk, "bus-spi3", ahb_hws,
> >> +  0x96c, BIT(3), 0);
> >> +
> >> +
> >> +static const struct clk_parent_data spif_parents[] = {
> >> + { .fw_name = "hosc" },
> >> + { .hw = &pll_periph_400M_clk.hw, },
> >> + { .hw = &pll_periph_300M_clk.hw, },
> >> +};
> >> +
> >> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(spif_clk, "spif", spif_parents, 0x0950,
> >> +      0, 4, /* M */
> >> +      24, 3, /* mux */
> >> +      BIT(31), /* gate */
> >> +      CLK_SET_RATE_PARENT);
> > 
> > This is MP clock, P being at 9:8.
> 
> yes, the BSP driver [1] model it with only M, I’ll update it to MP.
> 
> > 
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_spif_clk, "bus-spif", ahb_hws,
> >> +  0x096c, BIT(4), 0);
> >> +
> >> +
> >> +static const struct clk_hw *pll_periph_150M_hws[] = { &pll_periph_150M_clk.hw };
> >> +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25M_clk, "emac-25M", pll_periph_150M_hws,
> >> +      0x970, BIT(31) | BIT(30), 6, 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_emac_clk, "bus-emac", ahb_hws,
> >> +  0x97c, BIT(0), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_gpadc_clk, "bus-gpadc", apb0_hws,
> >> +  0x9ec, BIT(0), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", ahb_hws,
> >> +  0x9fc, BIT(0), 0);
> >> +
> >> +
> >> +static const struct clk_hw *audio_parents[] = {
> >> + &pll_audio_1x_clk.common.hw,
> >> + &pll_audio_4x_clk.common.hw,
> >> +};
> >> +
> >> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2s0_clk, "i2s0", audio_parents, 0xa10,
> >> +    0, 4, /* M */
> >> +    24, 1, /* mux */
> >> +    BIT(31), /* gate */
> >> +    CLK_SET_RATE_PARENT);
> >> +
> >> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2s1_clk, "i2s1", audio_parents, 0xa14,
> >> +    0, 4, /* M */
> >> +    24, 1, /* mux */
> >> +    BIT(31), /* gate */
> >> +    CLK_SET_RATE_PARENT);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_i2s0_clk, "bus-i2s0", ahb_hws,
> >> +  0xa20, BIT(0), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_i2s1_clk, "bus-i2s1", ahb_hws,
> >> +  0xa20, BIT(1), 0);
> >> +
> >> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dmic_clk, "dmic", audio_parents, 0xa40,
> >> +    0, 4, /* M */
> >> +    24, 1, /* mux */
> >> +    BIT(31), /* gate */
> >> +    CLK_SET_RATE_PARENT);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", ahb_hws,
> >> +  0xa4c, BIT(0), 0);
> >> +
> >> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(audio_codec_dac_clk, "audio-codec-dac", 
> >> +    audio_parents, 0xa50,
> >> +    0, 4, /* M */
> >> +    24, 1, /* mux */
> >> +    BIT(31), /* gate */
> >> +    CLK_SET_RATE_PARENT);
> >> +
> >> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(audio_codec_adc_clk, "audio-codec-adc", 
> >> +    audio_parents, 0xa54,
> >> +    0, 4, /* M */
> >> +    24, 1, /* mux */
> >> +    BIT(31), /* gate */
> >> +    CLK_SET_RATE_PARENT);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_audio_codec_clk, "bus-audio-codec", apb0_hws,
> >> +  0xa5c, BIT(0), 0);
> >> +
> >> +/*
> >> + * There are OHCI 12M clock source selection bits for the USB 2.0 port.
> >> + * We will force them to 0 (12M divided from 48M).
> >> + */
> >> +static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
> >> +
> >> +#define SUN8I_V853_USB_CLK_REG 0xa70
> >> +
> >> +static SUNXI_CCU_GATE(usb_ohci_clk, "usb", "osc12M", 0x0a70, BIT(31), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_ohci_clk, "bus-ohci", ahb_hws, 0xa8c, BIT(0), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_ehci_clk, "bus-ehci", ahb_hws, 0xa8c, BIT(4), 0);
> >> +static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", ahb_hws, 0xa8c, BIT(8), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_dpss_top_clk, "bus-dpss-top", ahb_hws,
> >> +  0xabc, BIT(0), 0);
> >> +
> >> +
> >> +static const struct clk_parent_data mipi_dsi_parents[] = {
> >> + { .fw_name = "hosc" },
> >> + { .hw = &pll_periph_200M_clk.hw },
> >> + { .hw = &pll_periph_150M_clk.hw },
> >> +};
> >> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", mipi_dsi_parents, 
> >> +      0xb24,
> >> +      0, 4, /* M */
> >> +      24, 3, /* mux */
> >> +      BIT(31), /* gate */
> >> +      CLK_SET_RATE_PARENT);
> > 
> > CLK_SET_RATE_PARENT doesn't do anything for constant clocks.
> > 
> 
> ok
> 
> > Best regards,
> > Jernej
> > 
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_mipi_dsi_clk, "bus-mipi-dsi", ahb_hws,
> >> +  0xb4c, BIT(0), 0);
> >> +
> >> +
> >> +static const struct clk_hw *tcon_lcd_parents[] = {
> >> + &pll_video_4x_clk.common.hw,
> >> + &pll_periph_2x_clk.common.hw,
> >> + &pll_csi_4x_clk.common.hw,
> >> +};
> >> +static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_lcd_clk, "tcon-lcd", tcon_lcd_parents, 
> >> +     0xb60,
> >> +     0, 4, /* M */
> >> +     8, 2, /* P */
> >> +     24, 3, /* mux */
> >> +     BIT(31), /* gate */
> >> +     CLK_SET_RATE_PARENT);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_tcon_lcd_clk, "bus-tcon-lcd", ahb_hws,
> >> +  0xb7c, BIT(0), 0);
> >> +
> >> +
> >> +static const struct clk_hw *csi_top_parents[] = {
> >> + &pll_periph_300M_clk.hw,
> >> + &pll_periph_400M_clk.hw,
> >> + &pll_video_4x_clk.common.hw,
> >> + &pll_csi_4x_clk.common.hw,
> >> +};
> >> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents, 0xc04,
> >> +    0, 5, /* M */
> >> +    24, 3, /* mux */
> >> +    BIT(31), /* gate */
> >> +    0);
> >> +
> >> +
> >> +static const struct clk_parent_data csi_mclk_parents[] = {
> >> + { .fw_name = "hosc" },
> >> + { .hw = &pll_csi_4x_clk.common.hw },
> >> + { .hw = &pll_video_4x_clk.common.hw },
> >> + { .hw = &pll_periph_2x_clk.common.hw },
> >> +};
> >> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk0_clk, "csi-mclk0", csi_mclk_parents, 
> >> +      0xc08,
> >> +      0, 5, /* M */
> >> +      24, 3, /* mux */
> >> +      BIT(31), /* gate */
> >> +      0);
> >> +
> >> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk1_clk, "csi-mclk1", csi_mclk_parents, 
> >> +      0xc0c,
> >> +      0, 5, /* M */
> >> +      24, 3, /* mux */
> >> +      BIT(31), /* gate */
> >> +      0);
> >> +
> >> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk2_clk, "csi-mclk2", csi_mclk_parents, 
> >> +      0xc10,
> >> +      0, 5, /* M */
> >> +      24, 3, /* mux */
> >> +      BIT(31), /* gate */
> >> +      0);
> > 
> > All CSI mclks should be MP type.
> > 
> 
> Again, these are from the BSP, I’ll update them.
> 
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", ahb_hws,
> >> +  0xc2c, BIT(0), 0);
> >> +
> >> +
> >> +static SUNXI_CCU_GATE_HWS(bus_wiegand_clk, "bus-wiegand", ahb_hws,
> >> +  0xc7c, BIT(0), 0);
> >> +
> >> +
> >> +static const struct clk_parent_data riscv_parents[] = {
> >> + { .fw_name = "hosc" },
> >> + { .fw_name = "losc" },
> >> + { .fw_name = "iosc" },
> >> + { .hw = &pll_periph_600M_clk.hw },
> >> + { .hw = &pll_periph_480M_clk.common.hw },
> >> + { .hw = &pll_cpu_clk.common.hw },
> >> +};
> >> +static SUNXI_CCU_M_DATA_WITH_MUX(riscv_clk, "riscv-cpu", riscv_parents, 0xd00,
> >> + 0, 5, /* M */
> >> + 24, 3, /* mux */
> >> + CLK_SET_RATE_PARENT);
> >> +
> >> +/* The riscv-axi clk must be divided by at least 2. */
> >> +static struct clk_div_table riscv_axi_table[] = {
> >> + { .val = 1, .div = 2 },
> >> + { .val = 2, .div = 3 },
> >> + { .val = 3, .div = 4 },
> >> + { /* Sentinel */ }
> >> +};
> >> +static SUNXI_CCU_DIV_TABLE_HW(riscv_axi_clk, "riscv-axi", &riscv_clk.common.hw,
> >> +      0xd00, 8, 2, riscv_axi_table, 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS_WITH_KEY(riscv_core_gate, "riscv-core-gate", ahb_hws,
> >> +   0xd04, BIT(0), 0);
> >> +
> >> +static SUNXI_CCU_GATE_HWS(riscv_cfg_gate, "riscv-cfg-gate", ahb_hws,
> >> +  0xd0c, BIT(0), 0);
> >> +
> >> +
> >> +static const struct clk_hw *pll_periph_160M_hws[] = {
> >> + &pll_periph_160M_clk.hw,
> >> +};
> >> +
> >> +static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
> >> +   0xf30, BIT(0), 0);
> >> +static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
> >> +       0xf30, BIT(1), 2, 0);
> >> +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph_160M_hws,
> >> +      0xf30, BIT(2), 10, 0);
> >> +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph_150M_hws,
> >> +      0xf30, BIT(3), 6, 0);
> >> +
> >> +
> >> +/* This clock has a second divider that is not modelled and forced to 0. */
> >> +#define SUN8I_V853_FANOUT_27M_REG 0xf34
> >> +static const struct clk_hw *fanout_27M_parents[] = {
> >> + &pll_video_1x_clk.hw,
> >> + &pll_csi_clk.hw,
> >> + &pll_periph_300M_clk.hw,
> >> +};
> >> +static SUNXI_CCU_M_HW_WITH_MUX_GATE(fanout_27M_clk, "fanout-27M", 
> >> +    fanout_27M_parents, 0xf34,
> >> +    0, 5, /* M */
> >> +    24, 2, /* mux */
> >> +    BIT(31), /* gate */
> >> +    0);
> >> +static SUNXI_CCU_M_HWS_WITH_GATE(fanout_pclk_clk, "fanout-pclk", apb0_hws, 0xf38,
> >> + 0, 5, /* M */
> >> + BIT(31), /* gate */
> >> + 0);
> >> +
> >> +static const struct clk_parent_data fanout_parents[] = {
> >> + { .fw_name = "losc" },
> >> + { .hw = &fanout_12M_clk.common.hw },
> >> + { .hw = &fanout_16M_clk.common.hw },
> >> + { .hw = &fanout_24M_clk.common.hw },
> >> + { .hw = &fanout_25M_clk.common.hw },
> >> + { .hw = &fanout_27M_clk.common.hw },
> >> + { .hw = &fanout_pclk_clk.common.hw },
> >> +};
> >> +
> >> +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 0xf3c,
> >> +    0, 3, /* mux */
> >> +    BIT(21), /* gate */
> >> +    0);
> >> +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 0xf3c,
> >> +    3, 3, /* mux */
> >> +    BIT(22), /* gate */
> >> +    0);
> >> +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 0xf3c,
> >> +    6, 3, /* mux */
> >> +    BIT(23), /* gate */
> >> +    0);
> >> +
> >> +
> >> +static struct ccu_common *sun8i_v853_ccu_clks[] = {
> >> + &pll_cpu_clk.common,
> >> + &pll_ddr_clk.common,
> >> + &pll_periph_4x_clk.common,
> >> + &pll_periph_2x_clk.common,
> >> + &pll_periph_800M_clk.common,
> >> + &pll_periph_480M_clk.common,
> >> + &pll_video_4x_clk.common,
> >> + &pll_csi_4x_clk.common,
> >> + &pll_audio_div2_clk.common,
> >> + &pll_audio_div5_clk.common,
> >> + &pll_audio_4x_clk.common,
> >> + &pll_audio_1x_clk.common,
> >> + &pll_npu_4x_clk.common,
> >> + &cpu_clk.common,
> >> + &cpu_axi_clk.common,
> >> + &cpu_apb_clk.common,
> >> + &ahb_clk.common,
> >> + &apb0_clk.common,
> >> + &apb1_clk.common,
> >> + &de_clk.common,
> >> + &bus_de_clk.common,
> >> + &g2d_clk.common,
> >> + &bus_g2d_clk.common,
> >> + &ce_clk.common,
> >> + &bus_ce_clk.common,
> >> + &ve_clk.common,
> >> + &bus_ve_clk.common,
> >> + &npu_clk.common,
> >> + &bus_npu_clk.common,
> >> + &bus_dma_clk.common,
> >> + &bus_msgbox0_clk.common,
> >> + &bus_msgbox1_clk.common,
> >> + &bus_spinlock_clk.common,
> >> + &bus_hstimer_clk.common,
> >> + &avs_clk.common,
> >> + &bus_dbg_clk.common,
> >> + &bus_pwm_clk.common,
> >> + &bus_iommu_clk.common,
> >> + &dram_clk.common,
> >> + &mbus_dma_clk.common,
> >> + &mbus_ve_clk.common,
> >> + &mbus_ce_clk.common,
> >> + &mbus_csi_clk.common,
> >> + &mbus_isp_clk.common,
> >> + &mbus_g2d_clk.common,
> >> + &bus_dram_clk.common,
> >> + &mmc0_clk.common,
> >> + &mmc1_clk.common,
> >> + &mmc2_clk.common,
> >> + &bus_mmc0_clk.common,
> >> + &bus_mmc1_clk.common,
> >> + &bus_mmc2_clk.common,
> >> + &bus_uart0_clk.common,
> >> + &bus_uart1_clk.common,
> >> + &bus_uart2_clk.common,
> >> + &bus_uart3_clk.common,
> >> + &bus_i2c0_clk.common,
> >> + &bus_i2c1_clk.common,
> >> + &bus_i2c2_clk.common,
> >> + &bus_i2c3_clk.common,
> >> + &bus_i2c4_clk.common,
> >> + &spi0_clk.common,
> >> + &spi1_clk.common,
> >> + &spi2_clk.common,
> >> + &spi3_clk.common,
> >> + &bus_spi0_clk.common,
> >> + &bus_spi1_clk.common,
> >> + &bus_spi2_clk.common,
> >> + &bus_spi3_clk.common,
> >> + &spif_clk.common,
> >> + &bus_spif_clk.common,
> >> + &emac_25M_clk.common,
> >> + &bus_emac_clk.common,
> >> + &bus_gpadc_clk.common,
> >> + &bus_ths_clk.common,
> >> + &usb_ohci_clk.common,
> >> + &bus_ohci_clk.common,
> >> + &bus_ehci_clk.common,
> >> + &bus_otg_clk.common,
> >> + &i2s0_clk.common,
> >> + &i2s1_clk.common,
> >> + &bus_i2s0_clk.common,
> >> + &bus_i2s1_clk.common,
> >> + &dmic_clk.common,
> >> + &bus_dmic_clk.common,
> >> + &audio_codec_dac_clk.common,
> >> + &audio_codec_adc_clk.common,
> >> + &bus_audio_codec_clk.common,
> >> + &bus_dpss_top_clk.common,
> >> + &mipi_dsi_clk.common,
> >> + &bus_mipi_dsi_clk.common,
> >> + &tcon_lcd_clk.common,
> >> + &bus_tcon_lcd_clk.common,
> >> + &csi_top_clk.common,
> >> + &csi_mclk0_clk.common,
> >> + &csi_mclk1_clk.common,
> >> + &csi_mclk2_clk.common,
> >> + &bus_csi_clk.common,
> >> + &bus_wiegand_clk.common,
> >> + &riscv_clk.common,
> >> + &riscv_axi_clk.common,
> >> + &riscv_core_gate.common,
> >> + &riscv_cfg_gate.common,
> >> + &fanout_24M_clk.common,
> >> + &fanout_12M_clk.common,
> >> + &fanout_16M_clk.common,
> >> + &fanout_25M_clk.common,
> >> + &fanout_27M_clk.common,
> >> + &fanout_pclk_clk.common,
> >> + &fanout0_clk.common,
> >> + &fanout1_clk.common,
> >> + &fanout2_clk.common,
> >> +};
> >> +
> >> +static struct clk_hw_onecell_data sun8i_v853_hw_clks = {
> >> + .num = CLK_NUMBER,
> >> + .hws = {
> >> + [CLK_OSC12M]            = &osc12M_clk.hw,
> >> + [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
> >> + [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
> >> + [CLK_PLL_PERIPH_4X] = &pll_periph_4x_clk.common.hw,
> >> + [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.common.hw,
> >> + [CLK_PLL_PERIPH_800M] = &pll_periph_800M_clk.common.hw,
> >> + [CLK_PLL_PERIPH_480M] = &pll_periph_480M_clk.common.hw,
> >> + [CLK_PLL_PERIPH_600M] = &pll_periph_600M_clk.hw,
> >> + [CLK_PLL_PERIPH_400M] = &pll_periph_400M_clk.hw,
> >> + [CLK_PLL_PERIPH_300M] = &pll_periph_300M_clk.hw,
> >> + [CLK_PLL_PERIPH_200M] = &pll_periph_200M_clk.hw,
> >> + [CLK_PLL_PERIPH_160M] = &pll_periph_160M_clk.hw,
> >> + [CLK_PLL_PERIPH_150M] = &pll_periph_150M_clk.hw,
> >> + [CLK_PLL_VIDEO_4X] = &pll_video_4x_clk.common.hw,
> >> + [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
> >> + [CLK_PLL_VIDEO_1X] = &pll_video_1x_clk.hw,
> >> + [CLK_PLL_CSI_4X] = &pll_csi_4x_clk.common.hw,
> >> + [CLK_PLL_AUDIO_DIV2] = &pll_audio_div2_clk.common.hw,
> >> + [CLK_PLL_AUDIO_DIV5] = &pll_audio_div5_clk.common.hw,
> >> + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.common.hw,
> >> + [CLK_PLL_AUDIO_1X] = &pll_audio_1x_clk.common.hw,
> >> + [CLK_PLL_NPU_4X] = &pll_npu_4x_clk.common.hw,
> >> + [CLK_CPU] = &cpu_clk.common.hw,
> >> + [CLK_CPU_AXI] = &cpu_axi_clk.common.hw,
> >> + [CLK_CPU_APB] = &cpu_apb_clk.common.hw,
> >> + [CLK_AHB] = &ahb_clk.common.hw,
> >> + [CLK_APB0] = &apb0_clk.common.hw,
> >> + [CLK_APB1] = &apb1_clk.common.hw,
> >> + [CLK_MBUS] = &mbus_clk.hw,
> >> + [CLK_DE] = &de_clk.common.hw,
> >> + [CLK_BUS_DE] = &bus_de_clk.common.hw,
> >> + [CLK_G2D] = &g2d_clk.common.hw,
> >> + [CLK_BUS_G2D] = &bus_g2d_clk.common.hw,
> >> + [CLK_CE] = &ce_clk.common.hw,
> >> + [CLK_BUS_CE] = &bus_ce_clk.common.hw,
> >> + [CLK_VE] = &ve_clk.common.hw,
> >> + [CLK_BUS_VE] = &bus_ve_clk.common.hw,
> >> + [CLK_NPU] = &npu_clk.common.hw,
> >> + [CLK_BUS_NPU] = &bus_npu_clk.common.hw,
> >> + [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
> >> + [CLK_BUS_MSGBOX0] = &bus_msgbox0_clk.common.hw,
> >> + [CLK_BUS_MSGBOX1] = &bus_msgbox1_clk.common.hw,
> >> + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
> >> + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
> >> + [CLK_AVS] = &avs_clk.common.hw,
> >> + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
> >> + [CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
> >> + [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
> >> + [CLK_DRAM] = &dram_clk.common.hw,
> >> + [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
> >> + [CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
> >> + [CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
> >> + [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
> >> + [CLK_MBUS_ISP] = &mbus_isp_clk.common.hw,
> >> + [CLK_MBUS_G2D] = &mbus_g2d_clk.common.hw,
> >> + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
> >> + [CLK_MMC0] = &mmc0_clk.common.hw,
> >> + [CLK_MMC1] = &mmc1_clk.common.hw,
> >> + [CLK_MMC2] = &mmc2_clk.common.hw,
> >> + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
> >> + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
> >> + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
> >> + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
> >> + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
> >> + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
> >> + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
> >> + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
> >> + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
> >> + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
> >> + [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
> >> + [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
> >> + [CLK_SPI0] = &spi0_clk.common.hw,
> >> + [CLK_SPI1] = &spi1_clk.common.hw,
> >> + [CLK_SPI2] = &spi2_clk.common.hw,
> >> + [CLK_SPI3] = &spi3_clk.common.hw,
> >> + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
> >> + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
> >> + [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
> >> + [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw,
> >> + [CLK_SPIF] = &spif_clk.common.hw,
> >> + [CLK_BUS_SPIF] = &bus_spif_clk.common.hw,
> >> + [CLK_EMAC_25M] = &emac_25M_clk.common.hw,
> >> + [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
> >> + [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
> >> + [CLK_BUS_THS] = &bus_ths_clk.common.hw,
> >> + [CLK_I2S0] = &i2s0_clk.common.hw,
> >> + [CLK_I2S1] = &i2s1_clk.common.hw,
> >> + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
> >> + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
> >> + [CLK_DMIC] = &dmic_clk.common.hw,
> >> + [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
> >> + [CLK_AUDIO_CODEC_DAC] = &audio_codec_dac_clk.common.hw,
> >> + [CLK_AUDIO_CODEC_ADC] = &audio_codec_adc_clk.common.hw,
> >> + [CLK_BUS_AUDIO_CODEC] = &bus_audio_codec_clk.common.hw,
> >> + [CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
> >> + [CLK_BUS_OHCI] = &bus_ohci_clk.common.hw,
> >> + [CLK_BUS_EHCI] = &bus_ehci_clk.common.hw,
> >> + [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
> >> + [CLK_BUS_DPSS_TOP] = &bus_dpss_top_clk.common.hw,
> >> + [CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
> >> + [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
> >> + [CLK_TCON_LCD] = &tcon_lcd_clk.common.hw,
> >> + [CLK_BUS_TCON_LCD] = &bus_tcon_lcd_clk.common.hw,
> >> + [CLK_CSI_TOP] = &csi_top_clk.common.hw,
> >> + [CLK_CSI_MCLK0] = &csi_mclk0_clk.common.hw,
> >> + [CLK_CSI_MCLK1] = &csi_mclk1_clk.common.hw,
> >> + [CLK_CSI_MCLK2] = &csi_mclk2_clk.common.hw,
> >> + [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
> >> + [CLK_BUS_WIEGAND] = &bus_wiegand_clk.common.hw,
> >> + [CLK_RISCV] = &riscv_clk.common.hw,
> >> + [CLK_RISCV_AXI] = &riscv_axi_clk.common.hw,
> >> + [CLK_RISCV_CORE_GATE]   = &riscv_core_gate.common.hw,
> >> + [CLK_RISCV_CFG_GATE]    = &riscv_cfg_gate.common.hw,
> >> + [CLK_FANOUT_24M] = &fanout_24M_clk.common.hw,
> >> + [CLK_FANOUT_16M] = &fanout_16M_clk.common.hw,
> >> + [CLK_FANOUT_12M] = &fanout_12M_clk.common.hw,
> >> + [CLK_FANOUT_25M] = &fanout_25M_clk.common.hw,
> >> + [CLK_FANOUT_27M] = &fanout_27M_clk.common.hw,
> >> + [CLK_FANOUT_PCLK] = &fanout_pclk_clk.common.hw,
> >> + [CLK_FANOUT0] = &fanout0_clk.common.hw,
> >> + [CLK_FANOUT1] = &fanout1_clk.common.hw,
> >> + [CLK_FANOUT2] = &fanout2_clk.common.hw,
> >> + },
> >> +};
> >> +
> >> +static struct ccu_reset_map sun8i_v853_ccu_resets[] = {
> >> + [RST_MBUS] = { 0x540, BIT(30) },
> >> + [RST_BUS_DE] = { 0x60c, BIT(16) },
> >> + [RST_BUS_G2D] = { 0x63c, BIT(16) },
> >> + [RST_BUS_CE] = { 0x68c, BIT(16) | BIT(17)},
> >> + [RST_BUS_VE] = { 0x69c, BIT(16) },
> >> + [RST_BUS_NPU] = { 0x6ec, BIT(16) },
> >> + [RST_BUS_DMA] = { 0x70c, BIT(16) },
> >> + [RST_BUS_MSGBOX0] = { 0x71c, BIT(16) },
> >> + [RST_BUS_MSGBOX1] = { 0x71c, BIT(17) },
> >> + [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
> >> + [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
> >> + [RST_BUS_DBG] = { 0x78c, BIT(16) },
> >> + [RST_BUS_PWM] = { 0x7ac, BIT(16) },
> >> + [RST_BUS_DRAM] = { 0x80c, BIT(16) },
> >> + [RST_BUS_MMC0] = { 0x84c, BIT(16) },
> >> + [RST_BUS_MMC1] = { 0x84c, BIT(17) },
> >> + [RST_BUS_MMC2] = { 0x84c, BIT(18) },
> >> + [RST_BUS_UART0] = { 0x90c, BIT(16) },
> >> + [RST_BUS_UART1] = { 0x90c, BIT(17) },
> >> + [RST_BUS_UART2] = { 0x90c, BIT(18) },
> >> + [RST_BUS_UART3] = { 0x90c, BIT(19) },
> >> + [RST_BUS_I2C0] = { 0x91c, BIT(16) },
> >> + [RST_BUS_I2C1] = { 0x91c, BIT(17) },
> >> + [RST_BUS_I2C2] = { 0x91c, BIT(18) },
> >> + [RST_BUS_I2C3] = { 0x91c, BIT(19) },
> >> + [RST_BUS_I2C4] = { 0x91c, BIT(20) },
> >> + [RST_BUS_SPI0] = { 0x96c, BIT(16) },
> >> + [RST_BUS_SPI1] = { 0x96c, BIT(17) },
> >> + [RST_BUS_SPI2] = { 0x96c, BIT(18) },
> >> + [RST_BUS_SPI3] = { 0x96c, BIT(19) },
> >> + [RST_BUS_SPIF] = { 0x96c, BIT(20) },
> >> + [RST_BUS_EMAC] = { 0x97c, BIT(16) },
> >> + [RST_BUS_GPADC] = { 0x9ec, BIT(16) },
> >> + [RST_BUS_THS] = { 0x9fc, BIT(16) },
> >> + [RST_BUS_I2S0] = { 0xa20, BIT(16) },
> >> + [RST_BUS_I2S1] = { 0xa20, BIT(17) },
> >> + [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
> >> + [RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) },
> >> + [RST_USB_PHY] = { 0xa70, BIT(30) },
> >> + [RST_BUS_OHCI] = { 0xa8c, BIT(16) },
> >> + [RST_BUS_EHCI] = { 0xa8c, BIT(20) },
> >> + [RST_BUS_OTG] = { 0xa8c, BIT(24) },
> >> + [RST_BUS_DPSS_TOP] = { 0xabc, BIT(16) },
> >> + [RST_BUS_MIPI_DSI] = { 0xb4c, BIT(16) },
> >> + [RST_BUS_TCON_LCD] = { 0xb7c, BIT(16) },
> >> + [RST_BUS_CSI] = { 0xc2c, BIT(16) },
> >> + [RST_BUS_WIEGAND] = { 0xc7c, BIT(16) },
> >> + [RST_RISCV_SYS_APB] = { 0xd04, BIT(2), CCU_FEATURE_KEY_FIELD },
> >> + [RST_RISCV_SOFT] = { 0xd04, BIT(1), CCU_FEATURE_KEY_FIELD },
> >> + [RST_RISCV_CFG] = { 0xd0c, BIT(16) }
> >> +};
> >> +
> >> +static const struct sunxi_ccu_desc sun8i_v853_ccu_desc = {
> >> + .ccu_clks = sun8i_v853_ccu_clks,
> >> + .num_ccu_clks = ARRAY_SIZE(sun8i_v853_ccu_clks),
> >> +
> >> + .hw_clks = &sun8i_v853_hw_clks,
> >> +
> >> + .resets = sun8i_v853_ccu_resets,
> >> + .num_resets = ARRAY_SIZE(sun8i_v853_ccu_resets),
> >> +};
> >> +
> >> +static const u32 pll_regs[] = {
> >> + SUN8I_V853_PLL_CPU_REG,
> >> + SUN8I_V853_PLL_DDR_REG,
> >> + SUN8I_V853_PLL_PERIPH_REG,
> >> + SUN8I_V853_PLL_VIDEO_REG,
> >> + SUN8I_V853_PLL_CSI_REG,
> >> + SUN8I_V853_PLL_AUDIO_REG,
> >> + SUN8I_V853_PLL_NPU_REG,
> >> +};
> >> +
> >> +static int sun8i_v853_ccu_probe(struct platform_device *pdev)
> >> +{
> >> + void __iomem *reg;
> >> + u32 val;
> >> + int i, ret;
> >> +
> >> + reg = devm_platform_ioremap_resource(pdev, 0);
> >> + if (IS_ERR(reg))
> >> + return PTR_ERR(reg);
> >> +
> >> + /* Enable the enable, LDO, and lock bits on all PLLs. */
> >> + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
> >> + val = readl(reg + pll_regs[i]);
> >> + val |= BIT(31) | BIT(30) | BIT(29);
> >> + writel(val, reg + pll_regs[i]);
> >> + }
> >> +
> >> + /* Force PLL_CPU factor M to 0. */
> >> + val = readl(reg + SUN8I_V853_PLL_CPU_REG);
> >> + val &= ~GENMASK(1, 0);
> >> + writel(val, reg + SUN8I_V853_PLL_CPU_REG);
> >> +
> >> + /*
> >> + * Force OHCI 12M clock source to 00 (12MHz divided from 48MHz)
> >> + *
> >> + * This clock mux is still mysterious, and the code just enforces
> >> + * it to have a valid clock parent.
> >> + */
> >> + val = readl(reg + SUN8I_V853_USB_CLK_REG);
> >> + val &= ~GENMASK(25, 24);
> >> + writel(val, reg + SUN8I_V853_USB_CLK_REG);
> >> +
> >> + /* Force fanout-27M factor N to 0. */
> >> + val = readl(reg + SUN8I_V853_FANOUT_27M_REG);
> >> + val &= ~GENMASK(9, 8);
> >> + writel(val, reg + SUN8I_V853_FANOUT_27M_REG);
> >> +
> >> + ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_v853_ccu_desc);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static const struct of_device_id sun8i_v853_ccu_ids[] = {
> >> + { .compatible = "allwinner,sun8i-v853-ccu" },
> >> + { }
> >> +};
> >> +
> >> +static struct platform_driver sun8i_v853_ccu_driver = {
> >> + .probe = sun8i_v853_ccu_probe,
> >> + .driver = {
> >> + .name = "sun8i-v853-ccu",
> >> + .suppress_bind_attrs = true,
> >> + .of_match_table = sun8i_v853_ccu_ids,
> >> + },
> >> +};
> >> +module_platform_driver(sun8i_v853_ccu_driver);
> >> +
> >> +MODULE_IMPORT_NS("SUNXI_CCU");
> >> +MODULE_DESCRIPTION("Support for the Allwinner V853 CCU");
> >> +MODULE_LICENSE("GPL");
> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v853.h b/drivers/clk/sunxi-ng/ccu-sun8i-v853.h
> >> new file mode 100644
> >> index 000000000000..f1b2a4d0bcd3
> >> --- /dev/null
> >> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v853.h
> >> @@ -0,0 +1,14 @@
> >> +/* SPDX-License-Identifier: GPL-2.0 */
> >> +/*
> >> + * Copyright (C) 2024 Andras Szemzo <szemzo.andras@gmail.com>
> >> + */
> >> +
> >> +#ifndef _CCU_SUN8I_V853_H_
> >> +#define _CCU_SUN8I_V853_H_
> >> +
> >> +#include <dt-bindings/clock/allwinner,sun8i-v853-ccu.h>
> >> +#include <dt-bindings/reset/allwinner,sun8i-v853-ccu.h>
> >> +
> >> +#define CLK_NUMBER (CLK_FANOUT2 + 1)
> >> +
> >> +#endif
> >> 
> > 
> > 
> > 
> > 
> 
> 

Re: [PATCH v2 02/10] pinctrl: sunxi: add driver for Allwinner V853

[Andre Przywara]

On Wed,  5 Feb 2025 13:52:17 +0100
Andras Szemzo <szemzo.andras@gmail.com> wrote:

Hi,

> The V853 family has multiple package variants, from BGA to QFN88.
> The latter has co-packaged DRAM and fewer pins, and less features (pin muxes).
> All family members can be supported by a single driver, as the available pins
> with allowed muxes is the same across the devices.
> 
> This new pinctrl driver depends on the new sunxi device-tree based mux support
> patch series [1].
> 
> [1]: https://lore.kernel.org/linux-sunxi/20241111005750.13071-1-andre.przywara@arm.com/T/
> 
> Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com>
> ---
>  drivers/pinctrl/sunxi/Kconfig              |  5 ++
>  drivers/pinctrl/sunxi/Makefile             |  1 +
>  drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c | 53 ++++++++++++++++++++++
>  3 files changed, 59 insertions(+)
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c
> 
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index a78fdbbdfc0c..fac9c61039e2 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -81,6 +81,11 @@ config PINCTRL_SUN9I_A80_R
>  	default MACH_SUN9I
>  	select PINCTRL_SUNXI
>  
> +config PINCTRL_SUN8I_V853
> +	bool "Support for the Allwinner V853/V851S/V851SE PIO"
> +	default MACH_SUN8I
> +	select PINCTRL_SUNXI
> +
>  config PINCTRL_SUN20I_D1
>  	bool "Support for the Allwinner D1 PIO"
>  	default MACH_SUN8I || (RISCV && ARCH_SUNXI)
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index 2ff5a55927ad..8937b56b2ef4 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A83T_R)	+= pinctrl-sun8i-a83t-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o
>  obj-$(CONFIG_PINCTRL_SUN8I_H3_R)	+= pinctrl-sun8i-h3-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_V3S)		+= pinctrl-sun8i-v3s.o
> +obj-$(CONFIG_PINCTRL_SUN8I_V853)	+= pinctrl-sun8i-v853.o
>  obj-$(CONFIG_PINCTRL_SUN20I_D1)		+= pinctrl-sun20i-d1.o
>  obj-$(CONFIG_PINCTRL_SUN50I_H5)		+= pinctrl-sun50i-h5.o
>  obj-$(CONFIG_PINCTRL_SUN50I_H6)		+= pinctrl-sun50i-h6.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c
> new file mode 100644
> index 000000000000..fb2112ee12d0
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Allwinner V853 SoC pinctrl driver.
> + *
> + * Copyright (c) 2025 Andras Szemzo <szemzo.andras@gmail.com>
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const u8 v853_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] =
> +/*	  PA  PB  PC  PD  PE  PF  PG  PH  PI  */
> +	{ 22,  0, 12, 23, 18,  7,  8, 16,  5 };
> +
> +static const unsigned int v853_irq_bank_map[] = { 0, 2, 3, 4, 5, 6, 7, 8 };
> +
> +static const u8 v853_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
> +/*	  PA  PB  PC  PD  PE  PF  PG  PH  PI */
> +	{ 14,  0, 14, 14, 14, 14, 14, 14, 14 };
> +
> +static struct sunxi_pinctrl_desc v853_pinctrl_data = {
> +	.irq_banks = ARRAY_SIZE(v853_irq_bank_map),
> +	.irq_bank_map = v853_irq_bank_map,
> +	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
> +};
> +
> +static int v853_pinctrl_probe(struct platform_device *pdev)
> +{
> +	return sunxi_pinctrl_dt_table_init(pdev, v853_nr_bank_pins,
> +					   v853_irq_bank_muxes,
> +					   &v853_pinctrl_data,
> +					   SUNXI_PINCTRL_NEW_REG_LAYOUT |
> +					   SUNXI_PINCTRL_ELEVEN_BANKS);

This last flag doesn't apply: it would put the offset for the
POW_MOD_SEL registers at 0x380, but the manual says it's 0x340, as with
the previous SoCs.
I compared the rest against the A523 driver, and the V853 specific bits
against the manual: they match, so with that line removed:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> +}
> +
> +static const struct of_device_id v853_pinctrl_match[] = {
> +	{ .compatible = "allwinner,sun8i-v853-pinctrl", },
> +	{}
> +};
> +
> +static struct platform_driver v853_pinctrl_driver = {
> +	.probe	= v853_pinctrl_probe,
> +	.driver	= {
> +		.name		= "sun8i-v853-pinctrl",
> +		.of_match_table	= v853_pinctrl_match,
> +	},
> +};
> +builtin_platform_driver(v853_pinctrl_driver);