From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8902C433F5 for ; Thu, 3 Feb 2022 13:56:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234548AbiBCN45 (ORCPT ); Thu, 3 Feb 2022 08:56:57 -0500 Received: from gloria.sntech.de ([185.11.138.130]:54912 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232957AbiBCN44 (ORCPT ); Thu, 3 Feb 2022 08:56:56 -0500 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nFcbM-0002C8-Tr; Thu, 03 Feb 2022 14:56:44 +0100 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Palmer Dabbelt , Tsukasa OI , linux-riscv@lists.infradead.org Cc: "linux-kernel@vger.kernel.org List" , Atish Patra , Albert Ou , Anup Patel , Damien Le Moal , devicetree , Jisheng Zhang , Krzysztof Kozlowski , linux-riscv , Paul Walmsley , Rob Herring , Atish Patra Subject: Re: [PATCH v1 0/2] Provide a fraemework for RISC-V ISA extensions Date: Thu, 03 Feb 2022 14:56:43 +0100 Message-ID: <1859467.Zi3Bu27KEa@diego> In-Reply-To: References: <20211224211632.1698523-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Atish, Am Samstag, 8. Januar 2022, 03:24:12 CET schrieb Atish Patra: > On Fri, Jan 7, 2022 at 1:58 PM Palmer Dabbelt wrote: > > > > On Fri, 24 Dec 2021 13:16:30 PST (-0800), atishp@atishpatra.org wrote: > > > This series implements a generic framework to parse multi-letter ISA > > > extensions. It introduces a new DT node that can be under /cpus or > > > individual cpu depends on the platforms with homogeneous or heterogeneous > > > harts. This version of the series only allows adds support for homogeneous > > > harts as there are no platforms with heterogeneous harts yet. However, > > > the DT binding allows both. > > > > > > The patch also indicates the user space about the available ISA extensions > > > via /proc/cpuinfo. > > > > > > Here is the example output of /proc/cpuinfo: > > > (with debug patches in Qemu and Linux kernel) > > > > > > / # cat /proc/cpuinfo > > > processor : 0 > > > hart : 0 > > > isa : rv64imafdcsu > > > isa-ext : sstc,sscofpmf > > > mmu : sv48 > > > > IMO this is the wrong way to go. I get that the ISA string is very > > complicated to parse, but we've tried to come up with other > > representations of this we've ended up having that interface break when > > the ISA string rules eventually change. We should just stick to the ISA > > string for these interfaces, as that's at least something everyone can > > agree on because they're defined by the spec. > > > > Fair enough. > > > That said, we should add the spec versions into this interface. At > > least the user spec version is relevant here, but given that we're > > passing through some other priv-level details we might as well pass that > > though too. > > > > Tsukasa already has a version that extends the isa string parsing for > multi-letter extensions > and versions parsing. We just need to add the ISA bitmap support on top of it. > > I will coordinate with Tsukasa to have a complete framework based on > string parsing. > It would be good to have this series asap as all other series (perf, > svpbmt) will rely on it. out of curiosity, did this go anywhere yet in terms of the coordinated approach you wrote about? Thanks Heiko