From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40954C4320A for ; Tue, 31 Aug 2021 15:29:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A3EE61053 for ; Tue, 31 Aug 2021 15:29:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238632AbhHaPaC (ORCPT ); Tue, 31 Aug 2021 11:30:02 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:60894 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238853AbhHaPaC (ORCPT ); Tue, 31 Aug 2021 11:30:02 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1630423747; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=JU0ORv8xALIzRyTc2G/fAIzydYETp5J0m/dw8byxgP4=; b=QmIR3KshjDC0BpRvx8N16wQrLz7AE8+lhXlUiusLPNDmQCGfNAIAa0ATBk6zFBXi+r4A3uRd Z9Uugc5DWbNAIDC4FBhoihqz0rcNZIuzZAeAjdSLskQ44jUNnJoPB9J0dW//oIiUBHB27OC2 E2fKpX5elOfsWgZcL0jrZEvgthQ= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n07.prod.us-west-2.postgun.com with SMTP id 612e4ab440d2129ac1eb7c4c (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Tue, 31 Aug 2021 15:28:52 GMT Sender: rajpat=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 39800C43460; Tue, 31 Aug 2021 15:28:52 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: rajpat) by smtp.codeaurora.org (Postfix) with ESMTPSA id A55BEC4338F; Tue, 31 Aug 2021 15:28:51 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Tue, 31 Aug 2021 20:58:51 +0530 From: rajpat@codeaurora.org To: Stephen Boyd Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, rnayak@codeaurora.org, saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com, skakit@codeaurora.org Subject: Re: [PATCH V6 6/7] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes In-Reply-To: References: <1629983731-10595-1-git-send-email-rajpat@codeaurora.org> <1629983731-10595-7-git-send-email-rajpat@codeaurora.org> Message-ID: <18995b9913c9acb7880b01a4f61ee5d0@codeaurora.org> X-Sender: rajpat@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2021-08-26 23:41, Stephen Boyd wrote: > Quoting Rajesh Patil (2021-08-26 06:15:30) >> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >> index 7c106c0..65126a7 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >> @@ -225,6 +225,10 @@ >> status = "okay"; >> }; >> >> +&qupv3_id_1 { >> + status = "okay"; >> +}; >> + > > Why enable this here but not any of the i2c/spi/uart devices that are a > child? Can this hunk be split off to a different patch? > Currently there is no usecase on qup1 and hence not enabled. Regarding splitting this, I did not get the exact reason why we need to split. This patch adds all the qup wrapper1 nodes and we are enabling it in board file. >> &sdhc_1 { >> status = "okay"; >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index a3c11b0..32f411f 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -2040,6 +2469,46 @@ >> function = "qup07"; >> }; >> >> + qup_i2c8_data_clk:qup-i2c8-data-clk { > > Unstick please. > OKay. >> + pins = "gpio32", "gpio33"; >> + function = "qup10"; >> + }; >> + >> + qup_i2c9_data_clk:qup-i2c9-data-clk { >> + pins = "gpio36", "gpio37"; >> + function = "qup11"; >> + }; >> + >> + qup_i2c10_data_clk:qup-i2c10-data-clk { >> + pins = "gpio40", "gpio41"; >> + function = "qup12"; >> + }; >> + >> + qup_i2c11_data_clk:qup-i2c11-data-clk { >> + pins = "gpio44", "gpio45"; >> + function = "qup13"; >> + }; >> + >> + qup_i2c12_data_clk:qup-i2c12-data-clk { >> + pins = "gpio48", "gpio49"; >> + function = "qup14"; >> + }; >> + >> + qup_i2c13_data_clk:qup-i2c13-data-clk { >> + pins = "gpio52", "gpio53"; >> + function = "qup15"; >> + }; >> + >> + qup_i2c14_data_clk:qup-i2c14-data-clk { >> + pins = "gpio56", "gpio57"; >> + function = "qup16"; >> + }; >> + >> + qup_i2c15_data_clk:qup-i2c15-data-clk { >> + pins = "gpio60", "gpio61"; >> + function = "qup17"; >> + }; > > All of these. > >> + >> qup_spi0_data_clk: qup-spi0-data-clk { >> pins = "gpio0", "gpio1", "gpio2"; >> function = "qup00";