From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: Wolfram Sang <wsa+renesas@sang-engineering.com>,
linux-renesas-soc@vger.kernel.org
Cc: Quynh Nguyen <quynh.nguyen.xb@renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH 1/4] arm64: dts: renesas: r9a08g045: Add I3C node
Date: Sat, 9 Aug 2025 08:05:48 +0300 [thread overview]
Message-ID: <18e948c8-96ed-4520-b25d-32ed1c845aff@tuxon.dev> (raw)
In-Reply-To: <20250807151434.5241-7-wsa+renesas@sang-engineering.com>
Hi, Wolfram,
On 07.08.2025 18:14, Wolfram Sang wrote:
> From: Quynh Nguyen <quynh.nguyen.xb@renesas.com>
>
> Add the I3C node to RZ/G3S SoC DTSI.
>
> Signed-off-by: Quynh Nguyen <quynh.nguyen.xb@renesas.com>
> [wsa: adapted to upstream driver, moved bus frequencies to board file]
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
> arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 35 ++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> index 0364f89776e6..6e372e222557 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> @@ -272,6 +272,41 @@ channel@8 {
> };
> };
>
> + i3c: i3c@1005b000 {
> + compatible = "renesas,r9a08g045-i3c";
> + reg = <0 0x1005b000 0 0x1000>;
> + clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>,
> + <&cpg CPG_MOD R9A08G045_I3C_TCLK>;
> + clock-names = "pclk", "tclk";
> + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "ierr", "terr", "abort", "resp", "cmd",
> + "ibi", "rx", "tx", "rcv","st", "sp",
Missing a space before "st".
Other than this:
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Thank you,
Claudiu
> + "tend", "nack", "al", "tmo", "wu", "exit";
> + resets = <&cpg R9A08G045_I3C_PRESETN>,
> + <&cpg R9A08G045_I3C_TRESETN>;
> + reset-names = "presetn", "tresetn";
> + power-domains = <&cpg>;
> + #address-cells = <3>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> vbattb: clock-controller@1005c000 {
> compatible = "renesas,r9a08g045-vbattb";
> reg = <0 0x1005c000 0 0x1000>;
next prev parent reply other threads:[~2025-08-09 5:05 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-07 15:14 [PATCH 0/4] arm64: dts: renesas: Enable I3C on RZ G3S/E Wolfram Sang
2025-08-07 15:14 ` [PATCH 1/4] arm64: dts: renesas: r9a08g045: Add I3C node Wolfram Sang
2025-08-09 5:05 ` Claudiu Beznea [this message]
2025-08-18 12:10 ` Geert Uytterhoeven
2025-08-07 15:14 ` [PATCH 2/4] arm64: dts: renesas: r9a09g047: " Wolfram Sang
2025-08-12 7:26 ` Geert Uytterhoeven
2025-08-18 12:24 ` Geert Uytterhoeven
2025-08-07 15:14 ` [PATCH 3/4] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C Wolfram Sang
2025-08-09 5:09 ` Claudiu Beznea
2025-08-09 9:17 ` Wolfram Sang
2025-08-07 15:14 ` [PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: " Wolfram Sang
2025-08-07 15:52 ` Biju Das
2025-08-07 17:00 ` wsa+renesas
2025-08-07 17:34 ` Biju Das
2025-08-08 14:55 ` kernel test robot
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