From: Dinh Nguyen <dinguyen@kernel.org>
To: Rob Herring <robh@kernel.org>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, sboyd@kernel.org,
mturquette@baylibre.com, mark.rutland@arm.com
Subject: Re: [PATCH 4/5] dt-bindings: documentation: add clock bindings information for Agilex
Date: Tue, 31 Mar 2020 16:56:11 -0500 [thread overview]
Message-ID: <1904132c-9211-6c23-028a-45788a55e420@kernel.org> (raw)
In-Reply-To: <20200331172356.GA17436@bogus>
On 3/31/20 12:23 PM, Rob Herring wrote:
> On Fri, Mar 20, 2020 at 12:02:10PM -0500, Dinh Nguyen wrote:
>> Document the Agilex clock bindings, and add the clock header file. The
>> clock header is an enumeration of all the different clocks on the Agilex
>> platform.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>> ---
>> v4: really fix build error(comment formatting was wrong)
>> v3: address comments from Stephen Boyd
>> fix build error(tab removed in line 37)
>> renamed to intel,agilex.yaml
>> v2: convert original document to YAML
>> ---
>> .../bindings/clock/intel,agilex.yaml | 36 ++++++++++
>> include/dt-bindings/clock/agilex-clock.h | 70 +++++++++++++++++++
>> 2 files changed, 106 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml
>> create mode 100644 include/dt-bindings/clock/agilex-clock.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/intel,agilex.yaml b/Documentation/devicetree/bindings/clock/intel,agilex.yaml
>> new file mode 100644
>> index 000000000000..5cf2ee5d6fcc
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/intel,agilex.yaml
>> @@ -0,0 +1,36 @@
>> +# SPDX-License-Identifier: GPL-2.0
>
> Dual license new bindings please:
>
> (GPL-2.0-only OR BSD-2-Clause)
>
Okay...
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/intel,agilex.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Intel SoCFPGA Agilex platform clock controller binding
>> +
>> +maintainers:
>> + - Dinh Nguyen <dinguyen@kernel.org>
>> +
>> +description:
>> + The Intel Agilex Clock controller is an integrated clock controller, which
>> + generates and supplies to all modules.
>> +
>> +properties:
>> + compatible:
>> + const: intel,agilex-clkmgr
>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - '#clock-cells'
>
> Add:
>
> additionalProperties: false
>
Okay..
>> +
>> +examples:
>> + # Clock controller node:
>> + - |
>> + clkmgr: clock-controller@ffd10000 {
>> + compatible = "intel,agilex-clkmgr";
>> + reg = <0xffd10000 0x1000>;
>> + #clock-cells = <1>;
>
> No clock inputs?
>
The clock controller is fed the onboard OSC1. So yes, I'll update it.
Dinh
next prev parent reply other threads:[~2020-03-31 21:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-20 17:02 [PATCHv4 0/5] clk: agilex: add clock driver Dinh Nguyen
2020-03-20 17:02 ` [PATCHv4 1/5] clk: socfpga: stratix10: use new parent data scheme Dinh Nguyen
2020-03-20 17:02 ` [PATCH 2/5] clk: socfpga: remove clk_ops enable/disable methods Dinh Nguyen
2020-03-20 17:02 ` [PATCH 3/5] clk: socfpga: add const to _ops data structures Dinh Nguyen
2020-03-20 17:02 ` [PATCH 4/5] dt-bindings: documentation: add clock bindings information for Agilex Dinh Nguyen
2020-03-31 17:23 ` Rob Herring
2020-03-31 21:56 ` Dinh Nguyen [this message]
2020-03-20 17:02 ` [PATCH 5/5] clk: socfpga: agilex: add clock driver for the Agilex platform Dinh Nguyen
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