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From: Mikko Perttunen <mperttunen@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Thierry Reding <treding@nvidia.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Sowjanya Komatineni <skomatineni@nvidia.com>,
	Luca Ceresoli <luca.ceresoli@bootlin.com>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Svyatoslav Ryhel <clamor95@gmail.com>,
	Dmitry Osipenko <digetx@gmail.com>,
	Charan Pedumuru <charan.pedumuru@gmail.com>,
	Svyatoslav Ryhel <clamor95@gmail.com>
Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org,
	dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-staging@lists.linux.dev
Subject: Re: [PATCH v1 01/19] clk: tegra: init CSUS clock for Tegra20 and Tegra30
Date: Wed, 27 Aug 2025 13:09:45 +0900	[thread overview]
Message-ID: <1909286.atdPhlSkOF@senjougahara> (raw)
In-Reply-To: <20250819121631.84280-2-clamor95@gmail.com>

On Tuesday, August 19, 2025 9:16 PM Svyatoslav Ryhel wrote:
> CSUS clock is required to be enabled on camera device configuration or
> else camera module refuses to initiate properly.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/clk/tegra/clk-tegra20.c | 1 +
>  drivers/clk/tegra/clk-tegra30.c | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/tegra/clk-tegra20.c
> b/drivers/clk/tegra/clk-tegra20.c index 551ef0cf0c9a..42f8150c6110 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -1043,6 +1043,7 @@ static struct tegra_clk_init_table init_table[] = {
>  	{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
>  	{ TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 },
>  	{ TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 },
> +	{ TEGRA20_CLK_CSUS, TEGRA20_CLK_CLK_MAX, 6000000, 1 },
>  	/* must be the last entry */
>  	{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
>  };
> diff --git a/drivers/clk/tegra/clk-tegra30.c
> b/drivers/clk/tegra/clk-tegra30.c index 82a8cb9545eb..70e85e2949e0 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -1237,6 +1237,7 @@ static struct tegra_clk_init_table init_table[] = {
>  	{ TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },
>  	{ TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },
>  	{ TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 },
> +	{ TEGRA30_CLK_CSUS, TEGRA30_CLK_CLK_MAX, 6000000, 1 },
>  	/* must be the last entry */
>  	{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
>  };

I looked into what this clock does and it seems to be a gate for the CSUS pin, 
which provides an output clock for camera sensors (VI MCLK). Default source 
seems to be PLLC_OUT1. It would be good to note that on the commit message, as 
I can't find any documentation about the CSUS clock elsewhere.

What is the 6MHz rate based on?

Since this seems to be a clock consumed by the sensor, it seems to me that 
rather than making it always on, we could point to it in the sensor's device 
tree entry.

Cheers,
Mikko




  reply	other threads:[~2025-08-27  4:09 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-19 12:16 [PATCH v1 00/19] tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 01/19] clk: tegra: init CSUS clock " Svyatoslav Ryhel
2025-08-27  4:09   ` Mikko Perttunen [this message]
2025-08-27  4:32     ` Svyatoslav
2025-08-27 10:36       ` Mikko Perttunen
2025-08-27 10:45         ` Svyatoslav Ryhel
2025-08-28  8:13           ` Mikko Perttunen
2025-08-28  8:28             ` Svyatoslav Ryhel
2025-08-28 10:15               ` Mikko Perttunen
2025-08-28 10:23                 ` Svyatoslav Ryhel
2025-08-29  0:29                   ` Mikko Perttunen
2025-08-29  7:05                     ` Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 02/19] dt-bindings: clock: tegra20: Add IDs for CSI PAD clocks Svyatoslav Ryhel
2025-08-22 13:59   ` Rob Herring
2025-08-27  4:19   ` Mikko Perttunen
2025-08-27  4:28     ` Svyatoslav
2025-08-27 10:27       ` Mikko Perttunen
2025-08-29  6:54         ` Krzysztof Kozlowski
2025-08-19 12:16 ` [PATCH v1 03/19] clk: tegra30: add CSI PAD clock gates Svyatoslav Ryhel
2025-08-27  4:26   ` Mikko Perttunen
2025-08-29  0:44   ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 04/19] dt-bindings: display: tegra: document Tegra30 VIP Svyatoslav Ryhel
2025-08-19 20:27   ` Rob Herring
2025-08-20  5:36     ` Svyatoslav Ryhel
2025-08-29  6:42     ` Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 05/19] staging: media: tegra-video: expand VI and VIP support to Tegra30 Svyatoslav Ryhel
2025-08-27  4:29   ` Mikko Perttunen
2025-08-27  4:47     ` Svyatoslav
2025-08-29  0:56       ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 06/19] staging: media: tegra-video: csi: move CSI helpers to header Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 07/19] staging: media: tegra-video: csi: parametrize MIPI calibration device presence Svyatoslav Ryhel
2025-09-02  0:46   ` Mikko Perttunen
2025-09-02  5:05     ` Svyatoslav Ryhel
2025-09-02  6:35       ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 08/19] staging: media: tegra-video: vi: adjust get_selection op check Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 09/19] staging: media: tegra-video: vi: add flip controls only if no source controls are provided Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 10/19] staging: media: tegra-video: tegra20: set correct maximum width and height Svyatoslav Ryhel
2025-09-02  0:51   ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 11/19] staging: media: tegra-video: tegra20: add support for second output of VI Svyatoslav Ryhel
2025-09-02  1:00   ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 12/19] staging: media: tegra-video: tegra20: simplify format align calculations Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 13/19] staging: media: tegra-video: tegra20: set VI HW revision Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 14/19] staging: media: tegra-video: tegra20: increase maximum VI clock frequency Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 15/19] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422 1X16 Svyatoslav Ryhel
2025-09-02  1:09   ` Mikko Perttunen
2025-09-02  5:11     ` Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 16/19] staging: media: tegra-video: tegra20: adjust luma buffer stride Svyatoslav Ryhel
2025-09-02  1:16   ` Mikko Perttunen
2025-08-19 12:16 ` [PATCH v1 17/19] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Svyatoslav Ryhel
2025-08-19 20:30   ` Rob Herring
2025-08-20  5:39     ` Svyatoslav Ryhel
2025-08-22 14:06       ` Rob Herring
2025-08-19 12:16 ` [PATCH v1 18/19] ARM: tegra: add CSI binding for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-08-19 12:16 ` [PATCH v1 19/19] staging: media: tegra-video: add CSI support " Svyatoslav Ryhel
2025-09-02  2:38   ` Mikko Perttunen
2025-09-02  5:51     ` Svyatoslav Ryhel
2025-09-02  6:17       ` Mikko Perttunen
2025-09-02  6:21         ` Svyatoslav Ryhel
2025-09-02  7:11     ` Dan Carpenter

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