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[89.212.118.115]) by smtp.gmail.com with ESMTPSA id s25-20020a170906285900b006f3c813f51fsm2227173ejc.128.2022.04.27.22.43.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Apr 2022 22:43:26 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Joerg Roedel , Will Deacon , iommu@lists.linux-foundation.org, Samuel Holland Cc: Heiko Stuebner , Palmer Dabbelt , linux-riscv@lists.infradead.org, Samuel Holland , Chen-Yu Tsai , Krzysztof Kozlowski , Maxime Ripard , Philipp Zabel , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: Re: [PATCH 3/5] iommu/sun50i: Ensure bypass is disabled Date: Thu, 28 Apr 2022 07:43:25 +0200 Message-ID: <1922960.8hb0ThOEGa@jernej-laptop> In-Reply-To: <20220428010401.11323-4-samuel@sholland.org> References: <20220428010401.11323-1-samuel@sholland.org> <20220428010401.11323-4-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Dne =C4=8Detrtek, 28. april 2022 ob 03:03:58 CEST je Samuel Holland napisal= (a): > The H6 variant of the hardware disables bypass by default. The D1 > variant of the hardware enables bypass for all masters by default. >=20 > Since the driver expects bypass to be disabled, ensure that is the case. >=20 > Signed-off-by: Samuel Holland Actually, it would be better to set bypass to 0xff and in=20 sun50i_iommu_attach_device() clear bypass bit for that particular device. A= s=20 you might notice, index in phandle is currently not used. This would also h= elp=20 expose bugs, like missing second iommu channel for Cedrus on H6, but that's= =20 easy to fix. Best regards, Jernej > --- >=20 > drivers/iommu/sun50i-iommu.c | 2 ++ > 1 file changed, 2 insertions(+) >=20 > diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c > index ec07b60016d3..b9e644b93637 100644 > --- a/drivers/iommu/sun50i-iommu.c > +++ b/drivers/iommu/sun50i-iommu.c > @@ -374,6 +374,8 @@ static int sun50i_iommu_enable(struct sun50i_iommu > *iommu) >=20 > spin_lock_irqsave(&iommu->iommu_lock, flags); >=20 > + iommu_write(iommu, IOMMU_BYPASS_REG, 0); > + > iommu_write(iommu, IOMMU_TTB_REG, sun50i_domain->dt_dma); > iommu_write(iommu, IOMMU_TLB_PREFETCH_REG, > IOMMU_TLB_PREFETCH_MASTER_ENABLE(0) |