From: "Heiko Stübner" <heiko@sntech.de>
To: Douglas Anderson <dianders@chromium.org>
Cc: ulf.hansson@linaro.org, kishon@ti.com, robh+dt@kernel.org,
shawn.lin@rock-chips.com, xzy.xu@rock-chips.com,
briannorris@chromium.org, adrian.hunter@intel.com,
linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org,
devicetree@vger.kernel.org, pawel.moll@arm.com,
mark.rutland@arm.com, ijc+devicetree@hellion.org.uk,
galak@codeaurora.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 03/11] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs
Date: Sat, 18 Jun 2016 16:15:01 +0200 [thread overview]
Message-ID: <1933773.0TPXapTvBs@diego> (raw)
In-Reply-To: <1465859076-4868-4-git-send-email-dianders@chromium.org>
Am Montag, 13. Juni 2016, 16:04:27 schrieb Douglas Anderson:
> As can be seen in Arasan's datasheet [1] there are several "corecfg"
> settings in their SDHCI IP Block that are supposed to be controlled by
> software. Although the datasheet referenced is a bit vague about how to
> access corecfg, in Figure 5 you can see that for Arasan's PHY (a
> separate component than their SDHCI component) they describe the
> "phyctrl" registers as being "FROM SOC CTL REG", implying that it's up
> to the licensee of the Arasan IP block to implement these registers. It
> seems sane to assume that the "corecfg" registers in their SDHCI IP
> block works in a similar way for all licensees of the IP Block.
>
> Device tree has a model that allows a device to get a reference to
> random registers located elsewhere in the SoC: sysctl. Let's leverage
> this model and allow adding a sysctl reference to access the control
> registers for the Arasan SDHCI PHYs.
>
> Having a reference to the control registers doesn't do much for us on
> its own since the Arasan spec doesn't specify how these corecfg values
> are laid out in memory. In the SDHCI driver we'll need a map detailing
> where each corecfg can be found in each implementation. This map can be
> found using the primary compatible string of the SDHCI device. In that
> spirit, document that existing rk3399 device trees already have a
> specific compatible string, though up to now they've always been relying
> on the driver supporting the generic.
>
> Note that since existing devices seem to work fairly well as-is, we'll
> list the syscon reference as "optional", but it's likely that we'll run
> into much fewer problems if we can actually set the proper values in the
> syscon, so it is strongly suggested that any SoCs where we have a map to
> set the corecfg also include a reference to the syscon.
>
> [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Acked-by: Rob Herring <robh@kernel.org>
I was trying to find public datasheets of other arasan-5.1 users, but wasn't
sucessful. But I guess this solution should be versatile enough to support the
implementation on other socs anyway, so
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
next prev parent reply other threads:[~2016-06-18 14:15 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-13 23:04 [PATCH v2 0/11] Changes to support 150 MHz eMMC on rk3399 Douglas Anderson
2016-06-13 23:04 ` [PATCH v2 02/11] mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes Douglas Anderson
2016-06-14 0:30 ` Shawn Lin
2016-06-13 23:04 ` [PATCH v2 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Douglas Anderson
2016-06-18 17:59 ` Heiko Stuebner
2016-06-13 23:04 ` [PATCH v2 07/11] mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson
2016-06-15 16:40 ` Doug Anderson
2016-06-13 23:04 ` [PATCH v2 09/11] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_on/off() Douglas Anderson
2016-06-14 0:36 ` Shawn Lin
[not found] ` <1465859076-4868-10-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-20 13:04 ` Kishon Vijay Abraham I
2016-06-16 23:39 ` [PATCH v2 0/11] Changes to support 150 MHz eMMC on rk3399 Heiko Stuebner
[not found] ` <1465859076-4868-1-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-13 23:04 ` [PATCH v2 01/11] phy: rockchip-emmc: Increase lock time allowance Douglas Anderson
2016-06-14 0:28 ` Shawn Lin
[not found] ` <1465859076-4868-2-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-20 13:03 ` Kishon Vijay Abraham I
2016-06-13 23:04 ` [PATCH v2 03/11] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs Douglas Anderson
2016-06-14 0:33 ` Shawn Lin
2016-06-18 14:15 ` Heiko Stübner [this message]
2016-06-13 23:04 ` [PATCH v2 05/11] arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 Douglas Anderson
2016-06-18 12:49 ` Heiko Stübner
2016-06-13 23:04 ` [PATCH v2 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson
2016-06-18 18:02 ` Heiko Stuebner
2016-06-13 23:04 ` [PATCH v2 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported " Douglas Anderson
2016-06-16 18:42 ` Rob Herring
2016-06-18 21:48 ` Heiko Stübner
[not found] ` <1465859076-4868-9-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-20 13:04 ` Kishon Vijay Abraham I
2016-06-13 23:04 ` [PATCH v2 10/11] phy: rockchip-emmc: Set phyctrl_frqsel based on " Douglas Anderson
[not found] ` <1465859076-4868-11-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-18 12:20 ` Heiko Stübner
2016-06-20 16:48 ` Doug Anderson
2016-06-20 13:08 ` Kishon Vijay Abraham I
2016-06-13 23:04 ` [PATCH v2 11/11] arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 Douglas Anderson
2016-06-18 12:07 ` Heiko Stübner
2016-06-17 12:39 ` [PATCH v2 0/11] Changes to support 150 MHz eMMC on rk3399 Kishon Vijay Abraham I
2016-06-17 15:37 ` Doug Anderson
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