From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PATCH v2 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 RX Device Tree bindings Date: Fri, 25 Aug 2017 19:34:55 +0300 Message-ID: <1955840.czSnNPfaK8@avalon> References: <20170720092302.2982-1-maxime.ripard@free-electrons.com> <2518768.foDtbh9bhx@avalon> <20170825144440.beettgwsynics3hs@flea.lan> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Return-path: In-Reply-To: <20170825144440.beettgwsynics3hs@flea.lan> Sender: linux-media-owner@vger.kernel.org To: Maxime Ripard Cc: Cyprian Wronka , Mauro Carvalho Chehab , Mark Rutland , Rob Herring , "linux-media@vger.kernel.org" , "devicetree@vger.kernel.org" , Neil Webb , Richard Sproul , Alan Douglas , Steve Creaney , Thomas Petazzoni , Boris Brezillon , Niklas =?ISO-8859-1?Q?S=F6derlund?= , Hans Verkuil , Sakari Ailus List-Id: devicetree@vger.kernel.org Hi Maxime, On Friday, 25 August 2017 17:44:40 EEST Maxime Ripard wrote: > On Wed, Aug 23, 2017 at 12:03:32AM +0300, Laurent Pinchart wrote: > >>>>>> + - phys: phandle to the external D-PHY > >>>>>> + - phy-names: must contain dphy, if the implementation uses an > >>>>>> + external D-PHY > >>>>> > >>>>> I would move the last two properties in an optional category as > >>>>> they're effectively optional. I think you should also explain a bit > >>>>> more clearly that the phys property must not be present if the phy- > >>>>> names property is not present. > >>>> > >>>> It's not really optional. The IP has a configuration register that > >>>> allows you to see if it's been synthesized with or without a PHY. If > >>>> the right bit is set, that property will be mandatory, if not, it's > >>>> useless. > >>> > >>> Just to confirm, the PHY is a separate IP core, right ? Is the CSI-2 > >>> receiver input interface different when used with a PHY and when used > >>> without one ? Could a third-party PHY be used as well ? If so, would > >>> the PHY synthesis bit be set or not ? > >> > >> The PHY (in our case a D-PHY) is a separate entity, it can be from a 3rd > >> party as the IP interface is standard, the SoC integrator would set the > >> bit accordingly based on whether any PHY is present or not. There is also > >> an option of routing digital output from a CSI-TX to a CSI-RX and in such > >> case a PHY would not need to be used (as in the case of our current > >> platform). > > > > OK, thank you for the clarification. > > > > Maxime mentioned that a bit can be read from a register to notify whether > > a PHY has been synthesized or not. Does it influence the CSI-2 RX input > > interface at all, or is the CSI-2 RX IP core synthesized the same way > > regardless of whether a PHY is present or not ? > > So we got an answer to this, and the physical interface remains the > same. > > However, the PHY bit is set only when there's an internal D-PHY, which > means we have basically three cases: > - No D-PHY at all, D-PHY presence bit not set > - Internal D-PHY, D-PHY presence bit set > - External D-PHY, D-PHY presence bit not set > > I guess that solves our discussion about whether the phys property > should be marked optional or not. It should indeed be optional, and > when it's not there, the D-PHY presence bit will tell whether we have > to program the internal D-PHY or not. Is the internal D-PHY programmed through the register space of the CSI2-RX ? If so I agree with you. -- Regards, Laurent Pinchart