From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 866EDC433EF for ; Tue, 14 Jun 2022 03:06:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353410AbiFNDGg (ORCPT ); Mon, 13 Jun 2022 23:06:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354502AbiFNDF4 (ORCPT ); Mon, 13 Jun 2022 23:05:56 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98DBB289B8; Mon, 13 Jun 2022 20:05:53 -0700 (PDT) X-UUID: 56bc72131ed3433b91a1721f007a7a54-20220614 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:bf3b2a39-4b69-473a-a54e-20ea40242a66,OB:0,LO B:0,IP:0,URL:25,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,AC TION:release,TS:70 X-CID-INFO: VERSION:1.1.6,REQID:bf3b2a39-4b69-473a-a54e-20ea40242a66,OB:0,LOB: 0,IP:0,URL:25,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:70 X-CID-META: VersionHash:b14ad71,CLOUDID:bbbb54c5-c67b-4a73-9b18-726dd8f2eb58,C OID:473988d49414,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 56bc72131ed3433b91a1721f007a7a54-20220614 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 711735860; Tue, 14 Jun 2022 11:05:48 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 14 Jun 2022 11:05:47 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 14 Jun 2022 11:05:47 +0800 Message-ID: <197b586898cad244037cf404cdff2846f5c0e10a.camel@mediatek.com> Subject: Re: [PATCH v11 01/12] dt-bindings: mediatek,dpi: Add DP_INTF compatible From: CK Hu To: Bo-Chen Chen , , , , , , , CC: , , , , , , , , , , Date: Tue, 14 Jun 2022 11:05:47 +0800 In-Reply-To: <20220613064841.10481-2-rex-bc.chen@mediatek.com> References: <20220613064841.10481-1-rex-bc.chen@mediatek.com> <20220613064841.10481-2-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, Bo-Chen: On Mon, 2022-06-13 at 14:48 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann > > DP_INTF is similar to DPI but does not have the exact same feature > set > or register layouts. > > DP_INTF is the sink of the display pipeline that is connected to the > DisplayPort controller and encoder unit. It takes the same clocks as > DPI. > > In this patch, we also do these string replacement: > - s/mediatek/MediaTek/ in title. > - s/Mediatek/MediaTek/ in description. > > Signed-off-by: Markus Schneider-Pargmann > Signed-off-by: Guillaume Ranquet > Signed-off-by: Bo-Chen Chen > --- > .../bindings/display/mediatek/mediatek,dpi.yaml | 13 ++++++++--- > -- > 1 file changed, 8 insertions(+), 5 deletions(-) > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam > l > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam > l > index 77ee1b923991..ca1b48e78581 100644 > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam > l > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam > l > @@ -4,16 +4,16 @@ > $id: > http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > > -title: mediatek DPI Controller Device Tree Bindings > +title: MediaTek DPI and DP_INTF Controller > > maintainers: > - CK Hu > - Jitao shi > > description: | > - The Mediatek DPI function block is a sink of the display subsystem > and > - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a > parallel > - output bus. > + The MediaTek DPI and DP_INTF function blocks are a sink of the > display > + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 > pixel data on a > + parallel output bus. > > properties: > compatible: > @@ -24,6 +24,7 @@ properties: > - mediatek,mt8183-dpi > - mediatek,mt8186-dpi > - mediatek,mt8192-dpi > + - mediatek,mt8195-dp_intf > > reg: > maxItems: 1 > @@ -36,12 +37,14 @@ properties: > - description: Pixel Clock > - description: Engine Clock > - description: DPI PLL > + - description: Clock gate for PLL Why DP_INTF has this additional clock? What is the new hardware block (compared with DPI) need this clock? Why this is different than DPI? Regards, CK > > clock-names: > items: > - const: pixel > - const: engine > - const: pll > + - const: pll_gate > > pinctrl-0: true > pinctrl-1: true > @@ -55,7 +58,7 @@ properties: > $ref: /schemas/graph.yaml#/properties/port > description: > Output port node. This port should be connected to the input > port of an > - attached HDMI or LVDS encoder chip. > + attached HDMI, LVDS or DisplayPort encoder chip. > > required: > - compatible