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[91.157.86.200]) by smtp.gmail.com with ESMTPSA id t10sm1451535lfk.58.2021.04.04.06.37.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 04 Apr 2021 06:37:32 -0700 (PDT) To: Pratyush Yadav , Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmaengine@vger.kernel.org Cc: Vignesh Raghavendra , Tomi Valkeinen References: <20210330173348.30135-1-p.yadav@ti.com> <20210330173348.30135-14-p.yadav@ti.com> From: =?UTF-8?Q?P=c3=a9ter_Ujfalusi?= Subject: Re: [PATCH 13/16] media: ti-vpe: csi2rx: Add CSI2RX support Message-ID: <1983f3dd-d157-900f-b72f-c8e6987f7ec6@gmail.com> Date: Sun, 4 Apr 2021 16:38:30 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.9.0 MIME-Version: 1.0 In-Reply-To: <20210330173348.30135-14-p.yadav@ti.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Pratyush, +1 from me also to the points Tomi raised. few minor comments on the DMAengie side. On 3/30/21 8:33 PM, Pratyush Yadav wrote: > TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate > capture over a CSI-2 bus. > > The Cadence CSI2RX IP acts as a bridge between the TI specific parts and > the CSI-2 protocol parts. TI then has a wrapper on top of this bridge > called the SHIM layer. It takes in data from stream 0, repacks it, and > sends it to memory over PSI-L DMA. > > This driver acts as the "front end" to V4L2 client applications. It > implements the required ioctls and buffer operations, passes the > necessary calls on to the bridge, programs the SHIM layer, and performs > DMA via the dmaengine API to finally return the data to a buffer > supplied by the application. > > Signed-off-by: Pratyush Yadav > --- > MAINTAINERS | 7 + > drivers/media/platform/Kconfig | 11 + > drivers/media/platform/ti-vpe/Makefile | 1 + > drivers/media/platform/ti-vpe/ti-csi2rx.c | 964 ++++++++++++++++++++++ > 4 files changed, 983 insertions(+) > create mode 100644 drivers/media/platform/ti-vpe/ti-csi2rx.c ... > diff --git a/drivers/media/platform/ti-vpe/ti-csi2rx.c b/drivers/media/platform/ti-vpe/ti-csi2rx.c > new file mode 100644 > index 000000000000..355204ae473b > --- /dev/null > +++ b/drivers/media/platform/ti-vpe/ti-csi2rx.c ... > +static int ti_csi2rx_init_vb2q(struct ti_csi2rx_dev *csi) > +{ > + struct vb2_queue *q = &csi->vidq; > + int ret; > + > + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; > + q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ; > + q->drv_priv = csi; > + q->buf_struct_size = sizeof(struct ti_csi2rx_buffer); > + q->ops = &csi_vb2_qops; > + q->mem_ops = &vb2_dma_contig_memops; > + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; > + q->dev = csi->dma->device->dev; q->dev = dmaengine_get_dma_device(csi->dma); > + q->lock = &csi->mutex; > + > + ret = vb2_queue_init(q); > + if (ret) > + return ret; > + > + csi->vdev.queue = q; > + > + return 0; > +} > + > +static int ti_csi2rx_init_dma(struct ti_csi2rx_dev *csi) > +{ > + struct dma_slave_config cfg; > + int ret; > + > + INIT_LIST_HEAD(&csi->dmaq.list); > + > + csi->dma = NULL; > + > + csi->dma = dma_request_chan(csi->dev, "rx0"); > + if (IS_ERR(csi->dma)) > + return PTR_ERR(csi->dma); > + > + memset(&cfg, 0, sizeof(cfg)); > + > + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_16_BYTES; > + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_16_BYTES; No need to set the dst_addr_width as you only support RX. Another note: UDMA with PSI-L native peripherals ignores this cofniguration, only used for PDMAs, but I can remain to future proof the driver and to keep it generic. > + > + ret = dmaengine_slave_config(csi->dma, &cfg); > + if (ret) > + return ret; > + > + return 0; > +} -- Péter