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From: Alexander Stein <alexander.stein@ew.tq-group.com>
To: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	"open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
	<imx@lists.linux.dev>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>,
	open list <linux-kernel@vger.kernel.org>
Cc: imx@lists.linux.dev, hongxing.zhu@nxp.com, Frank Li <Frank.Li@nxp.com>
Subject: Re: [PATCH 4/5] arm64: dts: imx95: add PCIe's msi-map and iommu-map property
Date: Wed, 26 Feb 2025 13:11:37 +0100	[thread overview]
Message-ID: <1995746.PYKUYFuaPT@steina-w> (raw)
In-Reply-To: <20250128211559.1582598-4-Frank.Li@nxp.com>

Hi Frank,

Am Dienstag, 28. Januar 2025, 22:15:58 CET schrieb Frank Li:
> Add PCIe's msi-map and iommu-map property because i.MX95 support smmu and
> its.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx95.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 6b8470cb3461a..2cebeda43a52d 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1573,6 +1573,12 @@ pcie0: pcie@4c300000 {
>  			assigned-clock-parents = <0>, <0>,
>  						 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
>  			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> +			/* pcie0's Devid(BIT[7:6]) is 0x00, stream id(BIT[5:0]) is 0x10~0x17 */
> +			msi-map = <0x0 &its 0x10 0x1>,
> +				  <0x100 &its 0x11 0x7>;

Aren't you missing msi-map-mask = <0x1ff>; here? Similar to pcie1.
Either way, with this change PCIe on pcie0 is not working anymore,
regardless of msi-map-mask.

Without msi-map-mask:
> OF: /soc/pcie@4c300000: iommu-map, using mask 000001ff, id-base: 00000100, out-base: 00000011, length: 00000007, id: 00000300 -> 00000011
> OF: /soc/pcie@4c300000: no msi-map translation for id 0x300 on (null)
> r8169 0000:03:00.0: error -EINVAL: enable failure
> r8169 0000:03:00.0: probe with driver r8169 failed with error -22

With msi-map-mask:
> OF: /soc/pcie@4c300000: iommu-map, using mask 000001ff, id-base: 00000100, out-base: 00000011, length: 00000007, id: 00000300 -> 00000011
> OF: /soc/pcie@4c300000: msi-map, using mask 000001ff, id-base: 00000100, out-base: 00000011, length: 00000007, id: 00000300 -> 00000011
> r8169 0000:03:00.0: enabling device (0000 -> 0003)
> r8169 0000:03:00.0: enabling Mem-Wr-Inval
> r8169 0000:03:00.0: error -EIO: PCI read failed
> r8169 0000:03:00.0: probe with driver r8169 failed with error -5

Without msi-map/iommu-map:
> r8169 0000:03:00.0: enabling device (0000 -> 0003)
> r8169 0000:03:00.0: enabling Mem-Wr-Inval
> r8169 0000:03:00.0 eth0: RTL8168g/8111g, d8:9d:b9:00:16:10, XID 4c0, IRQ 166
> r8169 0000:03:00.0 eth0: jumbo features [frames: 9194 bytes, tx checksumming: ko]
> r8169 0000:03:00.0 enp3s0: renamed from eth0
> r8169 0000:03:00.0: enabling bus mastering
> r8169 0000:03:00.0 enp3s0: Link is Down

pcie1 works as expected. But this is only a single PCIe device, rather than
having a PCIe bridge.
Any idea what's wrong here?

Best regards,
Alexander

> +			iommu-map = <0x000 &smmu 0x10 0x1>,
> +				    <0x100 &smmu 0x11 0x7>;
> +			iommu-map-mask = <0x1ff>;
>  			fsl,max-link-speed = <3>;
>  			status = "disabled";
>  		};
> @@ -1640,6 +1646,14 @@ pcie1: pcie@4c380000 {
>  			assigned-clock-parents = <0>, <0>,
>  						 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
>  			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> +			/* pcie1's Devid(BIT[7:6]) is 0x10, stream id(BIT[5:0]) is 0x18~0x1f */
> +			msi-map = <0x0 &its 0x98 0x1>,
> +				  <0x100 &its 0x99 0x7>;
> +			msi-map-mask = <0x1ff>;
> +			/* smmu have not Devid(BIT[7:6]) */
> +			iommu-map = <0x000 &smmu 0x18 0x1>,
> +				    <0x100 &smmu 0x19 0x7>;
> +			iommu-map-mask = <0x1ff>;
>  			fsl,max-link-speed = <3>;
>  			status = "disabled";
>  		};
> 


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  reply	other threads:[~2025-02-26 12:11 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-28 21:15 [PATCH 1/5] arm64: dts: imx8-ss-hsio: fix indentation in pcie node Frank Li
2025-01-28 21:15 ` [PATCH 2/5] arm64: dts: imx8q: add PCIe EP for i.MX8QM and i.MX8QXP Frank Li
2025-01-28 21:15 ` [PATCH 3/5] arm64: dts: imx8q: add PCIe EP overlay file for i.MX8QXP mek board Frank Li
2025-01-28 21:15 ` [PATCH 4/5] arm64: dts: imx95: add PCIe's msi-map and iommu-map property Frank Li
2025-02-26 12:11   ` Alexander Stein [this message]
2025-02-26 16:31     ` Frank Li
2025-02-26 20:23       ` Frank Li
2025-02-27  7:54       ` Alexander Stein
2025-02-27 16:39         ` Frank Li
2025-02-28  9:08           ` Alexander Stein
2025-02-28 15:32             ` Frank Li
2025-02-28 16:01               ` Alexander Stein
2025-02-28 17:11                 ` Frank Li
2025-03-27 18:48                   ` Frank Li
2025-04-09 10:14                     ` Alexander Stein
2025-04-09 14:59                       ` Frank Li
2025-04-11  6:53                         ` Alexander Stein
2025-04-11 14:42                           ` Frank Li
2025-04-14 12:06                             ` Alexander Stein
2025-01-28 21:15 ` [PATCH 5/5] arm64: dts: imx95: add ref clock for pcie nodes Frank Li
2025-02-22 15:00   ` Shawn Guo
2025-02-24  2:10     ` Hongxing Zhu
2025-02-24 17:11       ` Frank Li
2025-02-25  0:48         ` Hongxing Zhu
2025-01-29 14:38 ` [PATCH 1/5] arm64: dts: imx8-ss-hsio: fix indentation in pcie node Rob Herring (Arm)

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