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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47114429679sm73229585e9.8.2025.10.17.03.55.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Oct 2025 03:55:55 -0700 (PDT) Message-ID: <19a59be0-9b5f-4a93-bdd6-0592f291dca7@linaro.org> Date: Fri, 17 Oct 2025 11:55:52 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/6] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY To: Vijay Kumar Tumati , Hangxiang Ma , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, Jingyi Wang , Atiya Kailany References: <20251014-add-support-for-camss-on-kaanapali-v2-0-f5745ba2dff9@oss.qualcomm.com> <20251014-add-support-for-camss-on-kaanapali-v2-4-f5745ba2dff9@oss.qualcomm.com> <059a2e7b-f399-44d9-9f32-cd01e573d954@linaro.org> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 17/10/2025 00:10, Vijay Kumar Tumati wrote: > > There are three offsets in the picture here wrt the CSIPHY instance base > address > > 1. First offset to the common registers of the PHY, 'regs->offset' (that > follows the lane registers) > > 2. Second offset to the status registers within the common registers . > This has been historically the same and hard coded > in 'CSIPHY_3PH_CMN_CSI_COMMON_STATUSn' to 0xb0 but this is now changing > on Kaanapali. > > 3. Third set of offsets (12, 13, 14 and 15) are to the version registers > within the status registers. > > This change merely generalizes the CSIPHY_3PH_CMN_CSI_COMMON_STATUSn > macro for chip sets with different second offset using "regs- > >common_status_offset". There should not be any impact to the other > chip sets, for which it is set to the same 0xb0 in csiphy_init(). > > Please advise if you still think it requires a patch series for itself > and we can do that. Thanks. This should be a separate patch yes. --- bod