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* [PATCH v8 1/3] dt-bindings: PCI: qcom: ep: Add interconnects path
       [not found] <1689247213-13569-1-git-send-email-quic_krichai@quicinc.com>
@ 2023-07-13 11:20 ` Krishna chaitanya chundru
  2023-07-13 11:20 ` [PATCH v8 2/3] arm: dts: qcom: sdx65: Add PCIe interconnect path Krishna chaitanya chundru
  1 sibling, 0 replies; 3+ messages in thread
From: Krishna chaitanya chundru @ 2023-07-13 11:20 UTC (permalink / raw)
  To: manivannan.sadhasivam
  Cc: helgaas, linux-pci, linux-arm-msm, linux-kernel, quic_vbadigan,
	quic_nitegupt, quic_skananth, quic_ramkri, krzysztof.kozlowski,
	Krishna chaitanya chundru, Manivannan Sadhasivam, Andy Gross,
	Bjorn Andersson, Konrad Dybcio, Bjorn Helgaas, Lorenzo Pieralisi,
	Krzysztof Wilczyński, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS

Some platforms may not boot if a device driver doesn't
initialize the interconnect path. Mostly it is handled
by the bootloader but we have starting to see cases
where bootloader simply ignores them.

Add the "pcie-mem" interconnect path as a required property
to the bindings.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index 8111122..bc32e13 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -71,6 +71,13 @@ properties:
     description: GPIO used as WAKE# output signal
     maxItems: 1
 
+  interconnects:
+    maxItems: 1
+
+  interconnect-names:
+    items:
+      - const: pcie-mem
+
   resets:
     maxItems: 1
 
@@ -98,6 +105,8 @@ required:
   - interrupts
   - interrupt-names
   - reset-gpios
+  - interconnects
+  - interconnect-names
   - resets
   - reset-names
   - power-domains
@@ -167,7 +176,9 @@ examples:
   - |
     #include <dt-bindings/clock/qcom,gcc-sdx55.h>
     #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interconnect/qcom,sdx55.h>
     #include <dt-bindings/interrupt-controller/arm-gic.h>
+
     pcie_ep: pcie-ep@1c00000 {
         compatible = "qcom,sdx55-pcie-ep";
         reg = <0x01c00000 0x3000>,
@@ -194,6 +205,8 @@ examples:
         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
         interrupt-names = "global", "doorbell";
+        interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>;
+        interconnect-names = "pcie-mem";
         reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
         wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
         resets = <&gcc GCC_PCIE_BCR>;
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [PATCH v8 2/3] arm: dts: qcom: sdx65: Add PCIe interconnect path
       [not found] <1689247213-13569-1-git-send-email-quic_krichai@quicinc.com>
  2023-07-13 11:20 ` [PATCH v8 1/3] dt-bindings: PCI: qcom: ep: Add interconnects path Krishna chaitanya chundru
@ 2023-07-13 11:20 ` Krishna chaitanya chundru
  2023-07-15 15:07   ` Konrad Dybcio
  1 sibling, 1 reply; 3+ messages in thread
From: Krishna chaitanya chundru @ 2023-07-13 11:20 UTC (permalink / raw)
  To: manivannan.sadhasivam
  Cc: helgaas, linux-pci, linux-arm-msm, linux-kernel, quic_vbadigan,
	quic_nitegupt, quic_skananth, quic_ramkri, krzysztof.kozlowski,
	Krishna chaitanya chundru, Andy Gross, Bjorn Andersson,
	Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS

Add pcie-mem interconnect path to sdx65 platform.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
---
 arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index 1a35830..77fa97c 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -332,6 +332,9 @@
 				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "global", "doorbell";
 
+			interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
+			interconnect-names = "pcie-mem";
+
 			resets = <&gcc GCC_PCIE_BCR>;
 			reset-names = "core";
 
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH v8 2/3] arm: dts: qcom: sdx65: Add PCIe interconnect path
  2023-07-13 11:20 ` [PATCH v8 2/3] arm: dts: qcom: sdx65: Add PCIe interconnect path Krishna chaitanya chundru
@ 2023-07-15 15:07   ` Konrad Dybcio
  0 siblings, 0 replies; 3+ messages in thread
From: Konrad Dybcio @ 2023-07-15 15:07 UTC (permalink / raw)
  To: Krishna chaitanya chundru, manivannan.sadhasivam
  Cc: helgaas, linux-pci, linux-arm-msm, linux-kernel, quic_vbadigan,
	quic_nitegupt, quic_skananth, quic_ramkri, krzysztof.kozlowski,
	Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS

On 13.07.2023 13:20, Krishna chaitanya chundru wrote:
> Add pcie-mem interconnect path to sdx65 platform.
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
> ---
No CPU - SLAVE_PCIE_0?

Konrad
>  arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> index 1a35830..77fa97c 100644
> --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> @@ -332,6 +332,9 @@
>  				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
>  			interrupt-names = "global", "doorbell";
>  
> +			interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
> +			interconnect-names = "pcie-mem";
> +
>  			resets = <&gcc GCC_PCIE_BCR>;
>  			reset-names = "core";
>  

^ permalink raw reply	[flat|nested] 3+ messages in thread

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     [not found] <1689247213-13569-1-git-send-email-quic_krichai@quicinc.com>
2023-07-13 11:20 ` [PATCH v8 1/3] dt-bindings: PCI: qcom: ep: Add interconnects path Krishna chaitanya chundru
2023-07-13 11:20 ` [PATCH v8 2/3] arm: dts: qcom: sdx65: Add PCIe interconnect path Krishna chaitanya chundru
2023-07-15 15:07   ` Konrad Dybcio

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