Re: [PATCH v3 3/7] dt-bindings: usb: Add qcom,sa8255p-dwc3 for firmware-managed resources

[Faisal Hassan <faisal.hassan@oss.qualcomm.com>]

On 13-10-2026 12:50 pm, Krzysztof Kozlowski wrote:
> On Sat, Oct 10, 2026 at 11:02:42AM +0530, Faisal Hassan wrote:
>> On Qualcomm automotive SoC sa8255p, platform resources like clocks,
>> interconnects, resets, regulators and GDSC are abstracted and managed
>> collectively by firmware.
>>
>> Add a new binding file for firmware-managed USB controllers where
>> access to these resources is exposed as two power domains:
>> - Power domain: Controls power supply (GDSC) to the USB controller
>> - Bus domain: Controls clocks and interconnects for data transfer
>>
>> The binding makes power-domains and power-domain-names properties mandatory
>> for firmware-managed platforms, while excluding the clocks property since
>> clocks are managed through the power domains.
>>
>> Co-developed-by: Sriram Dash <sriram.dash@oss.qualcomm.com>
>> Signed-off-by: Sriram Dash <sriram.dash@oss.qualcomm.com>
>> Signed-off-by: Faisal Hassan <faisal.hassan@oss.qualcomm.com>
>> ---
>>   .../bindings/usb/qcom,sa8255p-dwc3.yaml       | 119 ++++++++++++++++++
>>   1 file changed, 119 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/usb/qcom,sa8255p-dwc3.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/usb/qcom,sa8255p-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,sa8255p-dwc3.yaml
>> new file mode 100644
>> index 000000000000..87f426fdbd70
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/qcom,sa8255p-dwc3.yaml
>> @@ -0,0 +1,119 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/usb/qcom,sa8255p-dwc3.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm SA8255P USB3 Controller with Firmware-Managed Resources
>> +
>> +maintainers:
>> +  - Wesley Cheng <wesley.cheng@oss.qualcomm.com>
>> +  - Faisal Hassan <faisal.hassan@oss.qualcomm.com>
>> +
>> +description:
>> +  USB controller on Qualcomm SA8255P automotive SoC where platform resources
>> +  such as clocks, interconnects, resets, regulators and the GDSC are
>> +  abstracted and managed collectively by firmware through SCMI (System
>> +  Control and Management Interface).
>> +
>> +  Access to these firmware-managed resources is exposed as two power
>> +  domains, one gating the power supply (GDSC) to the controller, and one
>> +  gating the clocks and interconnects used for data transfer.
>> +
>> +properties:
>> +  compatible:
>> +    const: qcom,sa8255p-dwc3
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  interrupts:
>> +    minItems: 5
>> +    maxItems: 6
>> +
>> +  interrupt-names:
>> +    minItems: 5
>> +    items:
>> +      - const: dwc_usb3
>> +      - const: pwr_event
>> +      - const: hs_phy_irq
>> +      - const: dp_hs_phy_irq
>> +      - const: dm_hs_phy_irq
>> +      - const: ss_phy_irq
> 
> That's still unexpectedly flexible.
> 

Ok, I'll drop minItems so the list is fixed at 6 entries:

   interrupts:
     maxItems: 6

   interrupt-names:
     items:
       - const: dwc_usb3
       - const: pwr_event
       - const: hs_phy_irq
       - const: dp_hs_phy_irq
       - const: dm_hs_phy_irq
       - const: ss_phy_irq

>> +
>> +  power-domains:
>> +    minItems: 2
> 
> Drop
> 
>> +    maxItems: 2
>> +
>> +  power-domain-names:
>> +    items:
>> +      - const: power
>> +      - const: bus
> 
> I don't see how did this improve. I asked to use existing bindings as
> reference, so why aren't these power and perf? You wrote that bus
> controls clocks and interconnect, so is this something different than
> perf domain is doing for sa8255?
> 

The sa8255 "perf" domains (e.g. GENI) are SCMI performance-protocol
domains with OPP levels. USB "bus" is a plain SCMI power domain with no
levels, only on/off, so "perf" would be misleading. I'd like to keep
"bus", and will drop the redundant minItems.

>> +
>> +  resets:
>> +    maxItems: 1
>> +
>> +  iommus:
>> +    maxItems: 1
>> +
>> +  phys:
>> +    minItems: 1
>> +    maxItems: 2
> 
> phys should be afixed, constrained.
> 
>> +
>> +  phy-names:
>> +    minItems: 1
>> +    maxItems: 2
> 
> This as well.
> 

Sure, will modify as below.

   phys:
     maxItems: 2

   phy-names:
     items:
       - const: usb2-phy
       - const: usb3-phy

>> +
>> +  dma-coherent: true
>> +
>> +  # Firmware-managed platforms do not use direct clock/interconnect control
>> +  clocks: false
>> +  clock-names: false
>> +  interconnects: false
>> +  interconnect-names: false
> 
> Drop all four above. Not sure why do you need them.
> 

Sure.

>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - interrupts
>> +  - interrupt-names
>> +  - power-domains
>> +  - power-domain-names
>> +  - resets
> 
> I guess phys and phy-names as well.
> 

Sure, will add both.

>> +
>> +allOf:
>> +  - $ref: snps,dwc3-common.yaml#
> 
> Best regards,
> Krzysztof

Let me know if these changes look OK, and I'll send v4 with them.

Thanks,
Faisal