From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Andrew Halaney <ahalaney@redhat.com>,
Mrinmay Sarkar <quic_msarkar@quicinc.com>
Cc: agross@kernel.org, andersson@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
mani@kernel.org, robh+dt@kernel.org, quic_shazhuss@quicinc.com,
quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com,
quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org,
robh@kernel.org, quic_krichai@quicinc.com,
quic_vbadigan@quicinc.com, quic_parass@quicinc.com,
quic_schintav@quicinc.com, quic_shijjose@quicinc.com,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH v1 2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller node
Date: Tue, 7 Nov 2023 22:54:58 +0100 [thread overview]
Message-ID: <19f32f8e-dfe2-410b-9a4d-80e24a888d65@linaro.org> (raw)
In-Reply-To: <i3yum3wbko33jwn7tfbcflpcxe5k5j5ituhyxtucx6gk2bs3gz@7ncewfmepnai>
On 11/7/23 19:37, Andrew Halaney wrote:
> On Tue, Nov 07, 2023 at 06:34:53PM +0530, Mrinmay Sarkar wrote:
>> Add ep pcie dtsi node for pcie1 controller found on sa8775p platform.
>> It supports gen4 and x4 link width. Limiting the speed to Gen3 due to
>> stability issues.
>
> I wouldn't mind a bit more information on what "stability" issues
> entails! I'm a sucker for details in a commit message.
Yep, giving us a bit more than "doesnt work" may help us help you!
>> +
>> + interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
Looks like the indentation is off?
>> +
>> + interrupt-names = "global", "doorbell", "dma";
>> +
>> + interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
>
> I keep seeing Konrad requesting that we use the #define instead of a raw
> number 0, i.e. something like QCOM_ICC_TAG_ALWAYS (although if I'm
> reading that correctly QCOM_ICC_TAG_ALWAYS doesn't evaluate to 0, so
> make sure you pick the appropriate one).
No it doesn't, but if you look at the code, tag being non-existent
assigns QCOM_ICC_TAG_ALWAYS which is a workaround for DTBs from back
when interconnect tags were not a thing
>
>> + interconnect-names = "pcie-mem", "cpu-pcie";
>
> This is nitpicky, but unless someone told you to do the whitespace
> between some of these properties I'd get more consistent. i.e. reg and
> reg-names has no newline between them, but clocks and clock-names does,
> and then interconnects/interconnect-names does not.
:)
Konrad
next prev parent reply other threads:[~2023-11-07 21:55 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-07 13:04 [PATCH v1 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller Mrinmay Sarkar
2023-11-07 13:04 ` [PATCH v1 1/2] phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p Mrinmay Sarkar
2023-11-07 13:10 ` Dmitry Baryshkov
2023-11-07 13:04 ` [PATCH v1 2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller node Mrinmay Sarkar
2023-11-07 18:37 ` Andrew Halaney
2023-11-07 21:54 ` Konrad Dybcio [this message]
2023-11-10 5:03 ` Mrinmay Sarkar
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