[PATCH v1 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller

[PATCH v1 0/2] arm64: qcom: sa8775p: add support for x4 EP PCIe controller

[Mrinmay Sarkar]

This series updates PHY and add EP PCIe node in dtsi file for
ep pcie1 controller that supports gen4 and x4 lane width.

To verify this series we required [1]

[1] https://lore.kernel.org/all/1699361428-12802-1-git-send-email-quic_msarkar@quicinc.com/

Mrinmay Sarkar (2):
  phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p
  arm64: dts: qcom: sa8775p: Add ep pcie1 controller node

 arch/arm64/boot/dts/qcom/sa8775p.dtsi    | 48 ++++++++++++++++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c |  9 +++++-
 2 files changed, 56 insertions(+), 1 deletion(-)

-- 
2.7.4

[PATCH v1 1/2] phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p

[Mrinmay Sarkar]

Add support for x4 lane end point mode PHY found on sa8755p platform.
Reusing existing serdes and pcs_misc table for EP and moved
BIAS_EN_CLKBUFLR_EN register from RC serdes table to common serdes
table as this register is part of both RC and EP.

Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index b64598a..7114b4e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -2099,6 +2099,7 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl[] = {
 };
 
 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
@@ -2125,7 +2126,6 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[]
 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
@@ -3114,6 +3114,13 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = {
 		.pcs_misc_num	= ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
 	},
 
+	.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
+		.serdes		= sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,
+		.serdes_num	= ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),
+		.pcs_misc	= sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
+		.pcs_misc_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
+	},
+
 	.reset_list		= sdm845_pciephy_reset_l,
 	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),
 	.vreg_list		= qmp_phy_vreg_l,
-- 
2.7.4

[PATCH v1 2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller node

[Mrinmay Sarkar]

Add ep pcie dtsi node for pcie1 controller found on sa8775p platform.
It supports gen4 and x4 link width. Limiting the speed to Gen3 due to
stability issues.

Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 48 +++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 7eab458..acd7bd8 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3732,6 +3732,54 @@
 		status = "disabled";
 	};
 
+	pcie1_ep: pcie-ep@1c10000 {
+		compatible = "qcom,sa8775p-pcie-ep";
+		reg = <0x0 0x01c10000 0x0 0x3000>,
+		      <0x0 0x60000000 0x0 0xf20>,
+		      <0x0 0x60000f20 0x0 0xa8>,
+		      <0x0 0x60001000 0x0 0x4000>,
+		      <0x0 0x60200000 0x0 0x100000>,
+		      <0x0 0x01c13000 0x0 0x1000>,
+			  <0x0 0x60005000 0x0 0x2000>;
+		reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
+			    "mmio", "dma";
+
+		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+			 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+			 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+			 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+			 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
+
+		clock-names = "aux",
+			      "cfg",
+			      "bus_master",
+			      "bus_slave",
+			      "slave_q2a";
+
+		interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+
+		interrupt-names = "global", "doorbell", "dma";
+
+		interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
+				<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
+		interconnect-names = "pcie-mem", "cpu-pcie";
+
+		dma-coherent;
+
+		iommus = <&pcie_smmu 0x80 0x7f>;
+		resets = <&gcc GCC_PCIE_1_BCR>;
+		reset-names = "core";
+		power-domains = <&gcc PCIE_1_GDSC>;
+		phys = <&pcie1_phy>;
+		phy-names = "pciephy";
+		max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
+		num-lanes = <4>;
+
+		status = "disabled";
+	};
+
 	pcie1_phy: phy@1c14000 {
 		compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
 		reg = <0x0 0x1c14000 0x0 0x4000>;
-- 
2.7.4

Re: [PATCH v1 1/2] phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p

[Dmitry Baryshkov]

On Tue, 7 Nov 2023 at 15:05, Mrinmay Sarkar <quic_msarkar@quicinc.com> wrote:
>
> Add support for x4 lane end point mode PHY found on sa8755p platform.
> Reusing existing serdes and pcs_misc table for EP and moved
> BIAS_EN_CLKBUFLR_EN register from RC serdes table to common serdes
> table as this register is part of both RC and EP.
>
> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index b64598a..7114b4e 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -2099,6 +2099,7 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl[] = {
>  };
>
>  static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = {
> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
>         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
>         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
>         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> @@ -2125,7 +2126,6 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[]
>         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
>         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
>         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
> -       QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
>         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
>         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
>         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> @@ -3114,6 +3114,13 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = {
>                 .pcs_misc_num   = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
>         },
>
> +       .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
> +               .serdes         = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,
> +               .serdes_num     = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),
> +               .pcs_misc       = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
> +               .pcs_misc_num   = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
> +       },
> +
>         .reset_list             = sdm845_pciephy_reset_l,
>         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
>         .vreg_list              = qmp_phy_vreg_l,
> --
> 2.7.4
>


-- 
With best wishes
Dmitry

Re: [PATCH v1 2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller node

[Andrew Halaney]

On Tue, Nov 07, 2023 at 06:34:53PM +0530, Mrinmay Sarkar wrote:
> Add ep pcie dtsi node for pcie1 controller found on sa8775p platform.
> It supports gen4 and x4 link width. Limiting the speed to Gen3 due to
> stability issues.

I wouldn't mind a bit more information on what "stability" issues
entails! I'm a sucker for details in a commit message.

> 
> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 48 +++++++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 7eab458..acd7bd8 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -3732,6 +3732,54 @@
>  		status = "disabled";
>  	};
>  
> +	pcie1_ep: pcie-ep@1c10000 {
> +		compatible = "qcom,sa8775p-pcie-ep";
> +		reg = <0x0 0x01c10000 0x0 0x3000>,
> +		      <0x0 0x60000000 0x0 0xf20>,
> +		      <0x0 0x60000f20 0x0 0xa8>,
> +		      <0x0 0x60001000 0x0 0x4000>,
> +		      <0x0 0x60200000 0x0 0x100000>,
> +		      <0x0 0x01c13000 0x0 0x1000>,
> +			  <0x0 0x60005000 0x0 0x2000>;
> +		reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
> +			    "mmio", "dma";
> +
> +		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> +			 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> +			 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> +			 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
> +			 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
> +
> +		clock-names = "aux",
> +			      "cfg",
> +			      "bus_master",
> +			      "bus_slave",
> +			      "slave_q2a";
> +
> +		interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
> +					 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> +					 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		interrupt-names = "global", "doorbell", "dma";
> +
> +		interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
> +				<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;

I keep seeing Konrad requesting that we use the #define instead of a raw
number 0, i.e. something like QCOM_ICC_TAG_ALWAYS (although if I'm
reading that correctly QCOM_ICC_TAG_ALWAYS doesn't evaluate to 0, so
make sure you pick the appropriate one).

> +		interconnect-names = "pcie-mem", "cpu-pcie";

This is nitpicky, but unless someone told you to do the whitespace
between some of these properties I'd get more consistent. i.e. reg and
reg-names has no newline between them, but clocks and clock-names does,
and then interconnects/interconnect-names does not.

> +
> +		dma-coherent;
> +
> +		iommus = <&pcie_smmu 0x80 0x7f>;
> +		resets = <&gcc GCC_PCIE_1_BCR>;
> +		reset-names = "core";
> +		power-domains = <&gcc PCIE_1_GDSC>;
> +		phys = <&pcie1_phy>;
> +		phy-names = "pciephy";
> +		max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
> +		num-lanes = <4>;
> +
> +		status = "disabled";
> +	};
> +
>  	pcie1_phy: phy@1c14000 {
>  		compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
>  		reg = <0x0 0x1c14000 0x0 0x4000>;
> -- 
> 2.7.4
> 
> 

Re: [PATCH v1 2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller node

[Konrad Dybcio]

On 11/7/23 19:37, Andrew Halaney wrote:
> On Tue, Nov 07, 2023 at 06:34:53PM +0530, Mrinmay Sarkar wrote:
>> Add ep pcie dtsi node for pcie1 controller found on sa8775p platform.
>> It supports gen4 and x4 link width. Limiting the speed to Gen3 due to
>> stability issues.
> 
> I wouldn't mind a bit more information on what "stability" issues
> entails! I'm a sucker for details in a commit message.
Yep, giving us a bit more than "doesnt work" may help us help you!


>> +
>> +		interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
>> +					 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
>> +					 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
Looks like the indentation is off?

>> +
>> +		interrupt-names = "global", "doorbell", "dma";
>> +
>> +		interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
>> +				<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
> 
> I keep seeing Konrad requesting that we use the #define instead of a raw
> number 0, i.e. something like QCOM_ICC_TAG_ALWAYS (although if I'm
> reading that correctly QCOM_ICC_TAG_ALWAYS doesn't evaluate to 0, so
> make sure you pick the appropriate one).
No it doesn't, but if you look at the code, tag being non-existent
assigns QCOM_ICC_TAG_ALWAYS which is a workaround for DTBs from back
when interconnect tags were not a thing

> 
>> +		interconnect-names = "pcie-mem", "cpu-pcie";
> 
> This is nitpicky, but unless someone told you to do the whitespace
> between some of these properties I'd get more consistent. i.e. reg and
> reg-names has no newline between them, but clocks and clock-names does,
> and then interconnects/interconnect-names does not.
:)

Konrad

Re: [PATCH v1 2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller node

[Mrinmay Sarkar]

On 11/8/2023 3:24 AM, Konrad Dybcio wrote:
>
>
> On 11/7/23 19:37, Andrew Halaney wrote:
>> On Tue, Nov 07, 2023 at 06:34:53PM +0530, Mrinmay Sarkar wrote:
>>> Add ep pcie dtsi node for pcie1 controller found on sa8775p platform.
>>> It supports gen4 and x4 link width. Limiting the speed to Gen3 due to
>>> stability issues.
>>
>> I wouldn't mind a bit more information on what "stability" issues
>> entails! I'm a sucker for details in a commit message.
> Yep, giving us a bit more than "doesnt work" may help us help you!
Actually if I enable gen4 some time I am getting link down and sometime
link getting establish at gen1. I am not getting stable gen4, may be we
need to program some register to get stable gen4 that I am checking.
>>> +
>>> +        interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
>>> +                     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
>>> +                     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
> Looks like the indentation is off?
>
>>> +
>>> +        interrupt-names = "global", "doorbell", "dma";
>>> +
>>> +        interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt 
>>> SLAVE_EBI1 0>,
>>> +                <&gem_noc MASTER_APPSS_PROC 0 &config_noc 
>>> SLAVE_PCIE_1 0>;
>>
>> I keep seeing Konrad requesting that we use the #define instead of a raw
>> number 0, i.e. something like QCOM_ICC_TAG_ALWAYS (although if I'm
>> reading that correctly QCOM_ICC_TAG_ALWAYS doesn't evaluate to 0, so
>> make sure you pick the appropriate one).
> No it doesn't, but if you look at the code, tag being non-existent
> assigns QCOM_ICC_TAG_ALWAYS which is a workaround for DTBs from back
> when interconnect tags were not a thing
>
>>
>>> +        interconnect-names = "pcie-mem", "cpu-pcie";
>>
>> This is nitpicky, but unless someone told you to do the whitespace
>> between some of these properties I'd get more consistent. i.e. reg and
>> reg-names has no newline between them, but clocks and clock-names does,
>> and then interconnects/interconnect-names does not.
> :)
I don't think there is any rule to add those white spaces, in next patch
I will align these white spaces with other pcie nodes.
>
> Konrad

Thanks,
Mrinmay