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Wed, 14 Oct 2026 01:31:58 -0700 (PDT) X-Received: by 2002:a05:620a:27d6:b0:92e:6485:f640 with SMTP id af79cd13be357-93ebd224118mr2789485885a.4.1791966718133; Wed, 14 Oct 2026 01:31:58 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b20383a22dsm876229a12.6.2026.10.14.01.31.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Oct 2026 01:31:57 -0700 (PDT) Message-ID: <1a8f0ef0-303d-4173-bfc2-ec8dd952f367@oss.qualcomm.com> Date: Wed, 14 Oct 2026 10:31:55 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing To: Jie Gan , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jie Gan References: <20260922-fix-etm-probe-issue-on-shikra-v1-1-56d25e9bbe17@oss.qualcomm.com> <3fe1ac52-f69a-4288-88b6-edb5717dd315@oss.qualcomm.com> <2a6b9567-e07e-40ae-a214-2a4d6bcb29d1@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <2a6b9567-e07e-40ae-a214-2a4d6bcb29d1@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: BcaNULoZEkw2qB1nwQDswp4JMPCr2Ctu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE0MDAzMyBTYWx0ZWRfX+iOagFef/dhu /8Us9l+/wXz9G92Lpoudtk+6sUHx4g3A2khRE/nByrAF1m91VoFVBlGKznr/AKf8jyZXtBfx/4D 56z98rmHI/h7NGDk8xvLyfCc+i1J0EKjcr2cLR7z5X/bEof7Q+U0U2Ok6cHPNy8oOSjSAFBJlMa nxLsmSiAeg6jnf2u/JNdnznTA4ugj6hfKu76F7XhpwjfpT/bBrzsJcTUHeBhGH2+IKFbgt6n4oA ZJ03qQo46f1qusLmQYurx9BZ8BOrOA8CEMqIRVw2TgnA8DXaC9IlitXmTlb8QsQRbr8YvQHMMUu wbsN/y2CFvojYzgvT338yPwmPVqazpSaN2d7h2ho8NRa6r4ckPzMO/f9v+OdKRSHYbo7dv9ERed 8fCsaGotAeDlQYQzhjjVKWtyPyb1r7vasvUMEzrDmWtDyiIFNdqsuVr5HjbgjTJm7Fu4Z6yCbB7 eOOeiN7ttZP8OFeD9lw== X-Authority-Analysis: v=2.4 cv=ErZHPicA c=1 sm=1 tr=0 ts=6acf3dff cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=5AA7zoZjs4rQ5UttiagA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE0MDAzMyBTYWx0ZWRfX63gETqw8kDqY HpZGpSGcPMR33tnsndkBFb5sFYVeY2Ovw1hoeWLZccc2dowEuOGjUwug+QHCUhVzLsb8+LukpWT E8yVtuf+644qMPamwqNlYemOMoUaffU= X-Proofpoint-GUID: BcaNULoZEkw2qB1nwQDswp4JMPCr2Ctu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 bulkscore=0 impostorscore=0 adultscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610140033 On 10/14/26 10:19 AM, Jie Gan wrote: > > > On 10/13/2026 8:38 PM, Konrad Dybcio wrote: >> On 9/22/26 5:09 AM, Jie Gan wrote: >>> The etm0-etm3 nodes are declared with "arm,coresight-etm4x-sysreg" >>> but do not implement self-hosted system-register trace access on >>> this SoC: ID_AA64DFR0_EL1.TraceVer reads as 0 on the affected CPUs, >>> so etm4_init_sysreg_access() correctly reports the access mechanism >>> as unavailable and the ETMv4 driver fails to probe with -EINVAL. >>> >>> The CPU ETMs have a memory-mapped aperture, so switch each node to >>> the standard "arm,coresight-etm4x", "arm,primecell" compatible with >>> its MMIO reg range. >>> >>> Fixes: eed738c6dd0c ("arm64: dts: qcom: shikra: Add coresight nodes") >>> Signed-off-by: Jie Gan >>> --- >> >> Do we still need qcom,skip-power-up on new SoCs *with* MMIO access? >> > > Yes, we need qcom,skip-power-up for all ETM device with or w/o MMIO access. > >> GPT has concerns regarding whether we need to add >> arm,coresight-loses-context-with-cpu> > > This logic to be handled by HYP on Shikra SoC, so I didnt enable it in kernel. https://lore.kernel.org/linux-arm-msm/20261005-shikra-el2-v3-0-618f7343695c@oss.qualcomm.com/ We're going to, in parallel, ship Shikra without the Qualcomm hypervisor so please keep that in mind. Should the submitters of the non-Gunyah overlay add these properties there as they respin? Does that concern all Coresight components? Konrad