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Tue, 22 Sep 2026 06:13:21 -0700 (PDT) Message-ID: <1ac16236-284a-4d01-b68a-4b32d5c5287c@riscstar.com> Date: Tue, 22 Sep 2026 08:13:19 -0500 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] dt-bindings: clock: introduce toshiba,tc9564-clock.yaml To: Krzysztof Kozlowski Cc: sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, andersson@kernel.org, konradybcio@kernel.org, abelvesa@kernel.org, kees@kernel.org, gustavoars@kernel.org, p.zabel@pengutronix.de, daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, mfd@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260918165234.687224-1-elder@riscstar.com> <20260918165234.687224-3-elder@riscstar.com> <20260920-messy-successful-caracara-fcdbcd@quoll> Content-Language: en-US From: Alex Elder In-Reply-To: <20260920-messy-successful-caracara-fcdbcd@quoll> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 9/20/26 1:21 PM, Krzysztof Kozlowski wrote: >> diff --git a/include/dt-bindings/clock/toshiba,tc9564.h b/include/dt-bindings/clock/toshiba,tc9564.h >> new file mode 100644 >> index 0000000000000..75732fddd3025 >> --- /dev/null >> +++ b/include/dt-bindings/clock/toshiba,tc9564.h >> @@ -0,0 +1,54 @@ >> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >> + >> +/* >> + * Copyright (C) 2026 by RISCstar Solutions Corporation. All rights reserved. >> + */ >> + >> +#ifndef __ClOCK_TOSHIBA_TC9564_H__ >> +#define __ClOCK_TOSHIBA_TC9564_H__ >> + >> +/* Clock IDs */ >> + >> +#define CLOCK_MCU 0 >> +#define CLOCK_INTC 1 >> +/* #define CLOCK_PCIE 2 */ >> +/* #define CLOCK_I2C 3 */ > Drop both, and SRAM is number 2. Or enable and implement them. I forgot to respond to this. I think you are confused. SRAM is BAR number 2. This is defining clock IDs. And the reason these are commented out is that, while they do exist, we explicitly do not want anyone to disable either of these clocks because PCIe uses them. This clock (and reset) control is accessed via PCIe. I do accept that someone might want me to simply omit these commented-out definitions, and I'd be fine with that. But your suggestion wasn't sensible so I wanted to clear that up before deleting these. -Alex