Re: [PATCH 27/39] dt-bindings: display: bridge: Document NXP i.MX95 pixel link support

[Marek Vasut <marek.vasut@mailbox.org>]

On 10/13/25 9:08 PM, Frank Li wrote:

Hello Frank,

>> +
>> +description: |
> 
> use >

Why not drop the trailing | altogether ?

>> +  The Freescale i.MX95 Display Pixel Link (DPL) forms a standard
>> +  asynchronous linkage between pixel sources (display controller
>> +  or camera module) and pixel consumers(imaging or displays).
>> +  It consists of two distinct functions, a pixel transfer function
>> +  and a control interface. Multiple pixel channels can exist per one
>> +  control channel. This binding documentation is only for pixel links
>> +  whose pixel sources are display controllers.
>> +
>> +  The i.MX95 Display Pixel Link is accessed via syscon.
>> +
>> +properties:
>> +  compatible:
>> +    const: fsl,imx95-dc-pixel-link
>> +
>> +  fsl,dc-stream-id:
>> +    $ref: /schemas/types.yaml#/definitions/uint8
>> +    description: |
> 
> Needn't |
> 
> why need this id

Because the IP is generic and can be attached to either output of the 
DC. We need to figure which one this is attached to, to configure the 
correct bitfields in syscon registers.

>> +      u8 value representing the display controller stream index that the pixel
>> +      link connects to.
>> +    enum: [0, 1]
>> +
>> +  fsl,syscon:
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +    description: |
>> +      A phandle which points to Control and Status Registers (CSR) module.
> 
> Why not use stardard interface, like reset, clock, phy ...

No standard interface fits, this is really a special remote register.

>> +  ports:
>> +    $ref: /schemas/graph.yaml#/properties/ports
>> +
>> +    properties:
>> +      port@0:
>> +        $ref: /schemas/graph.yaml#/properties/port
> 
> video-interfaces.yaml?
None of the properties in video-interfaces.yaml fit , so it makes no 
sense to pull it in here.

The other issues are fixed, thanks !