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[83.9.29.199]) by smtp.gmail.com with ESMTPSA id a22-20020a509b56000000b0054037c6676esm220608edj.69.2023.11.02.15.27.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Nov 2023 15:27:33 -0700 (PDT) Message-ID: <1bdf3b44-8a6f-c6d4-e86b-ec4bc0fc871f@linaro.org> Date: Thu, 2 Nov 2023 23:27:30 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v1 1/3] PCI: qcom: Enable cache coherency for SA8775P RC To: Mrinmay Sarkar , agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, mani@kernel.org, robh+dt@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, robh@kernel.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijjose@quicinc.com, Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <1698767186-5046-1-git-send-email-quic_msarkar@quicinc.com> <1698767186-5046-2-git-send-email-quic_msarkar@quicinc.com> <73a332db-14d3-a5b6-331a-d52ffb27ee63@quicinc.com> From: Konrad Dybcio In-Reply-To: <73a332db-14d3-a5b6-331a-d52ffb27ee63@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 02/11/2023 11:16, Mrinmay Sarkar wrote: > > On 10/31/2023 10:20 PM, Konrad Dybcio wrote: >> On 31.10.2023 16:46, Mrinmay Sarkar wrote: >>> This change will enable cache snooping logic to support >>> cache coherency for SA8755P RC platform. >> 8775 >> >>> Signed-off-by: Mrinmay Sarkar >>> --- >>>   drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++ >>>   1 file changed, 11 insertions(+) >>> >>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c >>> b/drivers/pci/controller/dwc/pcie-qcom.c >>> index 6902e97..6f240fc 100644 >>> --- a/drivers/pci/controller/dwc/pcie-qcom.c >>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >>> @@ -51,6 +51,7 @@ >>>   #define PARF_SID_OFFSET                0x234 >>>   #define PARF_BDF_TRANSLATE_CFG            0x24c >>>   #define PARF_SLV_ADDR_SPACE_SIZE        0x358 >>> +#define PCIE_PARF_NO_SNOOP_OVERIDE        0x3d4 >>>   #define PARF_DEVICE_TYPE            0x1000 >>>   #define PARF_BDF_TO_SID_TABLE_N            0x2000 >>> @@ -117,6 +118,9 @@ >>>   /* PARF_LTSSM register fields */ >>>   #define LTSSM_EN                BIT(8) >>> +/* PARF_NO_SNOOP_OVERIDE register value */ >> override >>> +#define NO_SNOOP_OVERIDE_EN            0xa >> is this actually some magic value and not BIT(1) | BIT(3)? > we need to set 1st and 3rd bit. yes, we can use BIT(1) | BIT(3). It would be great if you could explain what each of these bits means separately, #defining them instead and ORing at usage time. Konrad