* [PATCH 0/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC @ 2023-11-14 11:27 Zev Weiss 2023-11-14 11:27 ` [PATCH 1/2] dt-bindings: arm: aspeed: document ASRock E3C256D4I Zev Weiss 2023-11-14 11:27 ` [PATCH 2/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC Zev Weiss 0 siblings, 2 replies; 11+ messages in thread From: Zev Weiss @ 2023-11-14 11:27 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery Cc: Zev Weiss, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc Hello, These patches add a device-tree (and a tiny bindings update) for the Aspeed BMC on the ASRock E3C256D4I, so that it can be added as a supported OpenBMC platform. Thanks, Zev Zev Weiss (2): dt-bindings: arm: aspeed: document ASRock E3C256D4I ARM: dts: aspeed: Add ASRock E3C256D4I BMC .../bindings/arm/aspeed/aspeed.yaml | 1 + arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-asrock-e3c256d4i.dts | 314 ++++++++++++++++++ 3 files changed, 316 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts -- 2.42.0 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/2] dt-bindings: arm: aspeed: document ASRock E3C256D4I 2023-11-14 11:27 [PATCH 0/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC Zev Weiss @ 2023-11-14 11:27 ` Zev Weiss 2023-11-14 20:34 ` Krzysztof Kozlowski 2023-11-14 11:27 ` [PATCH 2/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC Zev Weiss 1 sibling, 1 reply; 11+ messages in thread From: Zev Weiss @ 2023-11-14 11:27 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery Cc: Zev Weiss, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc Document ASRock E3C256D4I board compatible. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 749ee54a3ff8..c330eba0e869 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -35,6 +35,7 @@ properties: - ampere,mtjade-bmc - aspeed,ast2500-evb - asrock,e3c246d4i-bmc + - asrock,e3c256d4i-bmc - asrock,romed8hm3-bmc - bytedance,g220a-bmc - facebook,cmm-bmc -- 2.42.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm: aspeed: document ASRock E3C256D4I 2023-11-14 11:27 ` [PATCH 1/2] dt-bindings: arm: aspeed: document ASRock E3C256D4I Zev Weiss @ 2023-11-14 20:34 ` Krzysztof Kozlowski 0 siblings, 0 replies; 11+ messages in thread From: Krzysztof Kozlowski @ 2023-11-14 20:34 UTC (permalink / raw) To: Zev Weiss, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc On 14/11/2023 12:27, Zev Weiss wrote: > Document ASRock E3C256D4I board compatible. > > Signed-off-by: Zev Weiss <zev@bewilderbeest.net> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC 2023-11-14 11:27 [PATCH 0/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC Zev Weiss 2023-11-14 11:27 ` [PATCH 1/2] dt-bindings: arm: aspeed: document ASRock E3C256D4I Zev Weiss @ 2023-11-14 11:27 ` Zev Weiss 2023-11-14 20:35 ` Krzysztof Kozlowski 1 sibling, 1 reply; 11+ messages in thread From: Zev Weiss @ 2023-11-14 11:27 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery Cc: Zev Weiss, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc Like the E3C246D4I, this is a reasonably affordable off-the-shelf mini-ITX AST2500/Xeon motherboard with good potential as an OpenBMC development platform. Booting the host requires a modicum of eSPI support that's not yet in the mainline kernel, but most other basic BMC functionality is available with this device-tree. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-asrock-e3c256d4i.dts | 314 ++++++++++++++++++ 2 files changed, 315 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index d3ac20e316d0..3398ee53f034 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-ampere-mtmitchell.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-asrock-e3c246d4i.dtb \ + aspeed-bmc-asrock-e3c256d4i.dtb \ aspeed-bmc-asrock-romed8hm3.dtb \ aspeed-bmc-bytedance-g220a.dtb \ aspeed-bmc-delta-ahe50dc.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts new file mode 100644 index 000000000000..4c55272afd4f --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/i2c/i2c.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/watchdog/aspeed-wdt.h> + +/{ + model = "ASRock E3C256D4I BMC"; + compatible = "asrock,e3c256d4i-bmc", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + + i2c20 = &i2c2mux0ch0; + i2c21 = &i2c2mux0ch1; + i2c22 = &i2c2mux0ch2; + i2c23 = &i2c2mux0ch3; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + system-fault { + gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; + panic-indicator; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <100000000>; /* 100 MHz */ +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; + + nvmem-cells = <ð0_macaddress>; + nvmem-cell-names = "mac-address"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9545"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c2mux0ch0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c2mux0ch1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c2mux0ch2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c2mux0ch3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + vrm@60 { + compatible = "renesas,isl69269", "isl69269"; + reg = <0x60>; + }; +}; + +&i2c12 { + status = "okay"; + + /* FRU eeprom */ + eeprom@57 { + compatible = "st,24c128", "atmel,24c128"; + reg = <0x57>; + pagesize = <16>; + + eth0_macaddress: macaddress@3f80 { + reg = <0x3f80 6>; + }; + }; +}; + +&video { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&peci0 { + status = "okay"; +}; + +&wdt1 { + aspeed,reset-mask = <(AST2500_WDT_RESET_DEFAULT & ~AST2500_WDT_RESET_LPC)>; +}; + +&wdt2 { + aspeed,reset-mask = <(AST2500_WDT_RESET_DEFAULT & ~AST2500_WDT_RESET_LPC)>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default /* CPU */ + &pinctrl_pwm2_default /* rear */ + &pinctrl_pwm4_default>; /* front */ + + /* CPU */ + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + /* rear */ + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + /* front */ + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /* A */ "", "", "NMI_BTN_N", "BMC_NMI", "", "", "", "", + /* B */ "", "", "", "", "", "", "", "", + /* C */ "", "", "", "", "", "", "", "", + /* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON", + "", "", "", "", + /* E */ "", "", "", "", "", "", "", "", + /* F */ "LOCATORLED_STATUS_N", "LOCATORBTN", "", "", + "", "", "BMC_PCH_SCI_LPC", "BMC_NCSI_MUX_CTL", + /* G */ "HWM_BAT_EN", "CHASSIS_ID0", "CHASSIS_ID1", "CHASSIS_ID2", + "", "", "", "", + /* H */ "FM_ME_RCVR_N", "O_PWROK", "", "D4_DIMM_EVENT_3V_N", + "MFG_MODE_N", "BMC_RTCRST", "BMC_HB_LED_N", "BMC_CASEOPEN", + /* I */ "", "", "", "", "", "", "", "", + /* J */ "BMC_READY", "BMC_PCH_BIOS_CS_N", "BMC_SMI", "", "", "", "", "", + /* K */ "", "", "", "", "", "", "", "", + /* L */ "", "", "", "", "", "", "", "", + /* M */ "", "", "", "", "", "", "", "", + /* N */ "", "", "", "", "", "", "", "", + /* O */ "", "", "", "", "", "", "", "", + /* P */ "", "", "", "", "", "", "", "", + /* Q */ "", "", "", "", "", "", "", "", + /* R */ "", "", "", "", "", "", "", "", + /* S */ "PCHHOT_BMC_N", "", "RSMRST", "", "", "", "", "", + /* T */ "", "", "", "", "", "", "", "", + /* U */ "", "", "", "", "", "", "", "", + /* V */ "", "", "", "", "", "", "", "", + /* W */ "", "", "", "", "", "", "", "", + /* X */ "", "", "", "", "", "", "", "", + /* Y */ "SLP_S3", "SLP_S5", "", "", "", "", "", "", + /* Z */ "CPU_CATERR_BMC_N", "", "SYSTEM_FAULT_LED_N", "BMC_THROTTLE_N", + "", "", "", "", + /* AA */ "CPU1_THERMTRIP_LATCH_N", "", "CPU1_PROCHOT_N", "", + "", "", "IRQ_SMI_ACTIVE_N", "FM_BIOS_POST_CMPLT_N", + /* AB */ "", "", "ME_OVERRIDE", "BMC_DMI_MODIFY", "", "", "", "", + /* AC */ "", "", "", "", "", "", "", ""; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default /* 3VSB */ + &pinctrl_adc1_default /* 5VSB */ + &pinctrl_adc2_default /* CPU1 */ + &pinctrl_adc3_default /* VCCSA */ + &pinctrl_adc4_default /* VCCM */ + &pinctrl_adc5_default /* V10M */ + &pinctrl_adc6_default /* VCCIO */ + &pinctrl_adc7_default /* VCCGT */ + &pinctrl_adc8_default /* VPPM */ + &pinctrl_adc9_default /* BAT */ + &pinctrl_adc10_default /* 3V */ + &pinctrl_adc11_default /* 5V */ + &pinctrl_adc12_default /* 12V */ + &pinctrl_adc13_default /* GND */ + &pinctrl_adc14_default /* GND */ + &pinctrl_adc15_default>; /* GND */ +}; -- 2.42.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC 2023-11-14 11:27 ` [PATCH 2/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC Zev Weiss @ 2023-11-14 20:35 ` Krzysztof Kozlowski 2023-11-14 22:21 ` Zev Weiss 2023-11-14 22:37 ` Zev Weiss 0 siblings, 2 replies; 11+ messages in thread From: Krzysztof Kozlowski @ 2023-11-14 20:35 UTC (permalink / raw) To: Zev Weiss, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc On 14/11/2023 12:27, Zev Weiss wrote: > Like the E3C246D4I, this is a reasonably affordable off-the-shelf > mini-ITX AST2500/Xeon motherboard with good potential as an OpenBMC > development platform. Booting the host requires a modicum of eSPI > support that's not yet in the mainline kernel, but most other basic > BMC functionality is available with this device-tree. > > Signed-off-by: Zev Weiss <zev@bewilderbeest.net> > --- > arch/arm/boot/dts/aspeed/Makefile | 1 + > .../aspeed/aspeed-bmc-asrock-e3c256d4i.dts | 314 ++++++++++++++++++ > 2 files changed, 315 insertions(+) > create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts > > diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile > index d3ac20e316d0..3398ee53f034 100644 > --- a/arch/arm/boot/dts/aspeed/Makefile > +++ b/arch/arm/boot/dts/aspeed/Makefile > @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ > aspeed-bmc-ampere-mtmitchell.dtb \ > aspeed-bmc-arm-stardragon4800-rep2.dtb \ > aspeed-bmc-asrock-e3c246d4i.dtb \ > + aspeed-bmc-asrock-e3c256d4i.dtb \ > aspeed-bmc-asrock-romed8hm3.dtb \ > aspeed-bmc-bytedance-g220a.dtb \ > aspeed-bmc-delta-ahe50dc.dtb \ > diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts > new file mode 100644 > index 000000000000..4c55272afd4f > --- /dev/null > +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts > @@ -0,0 +1,314 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/dts-v1/; > + > +#include "aspeed-g5.dtsi" > +#include <dt-bindings/gpio/aspeed-gpio.h> > +#include <dt-bindings/i2c/i2c.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/watchdog/aspeed-wdt.h> > + > +/{ > + model = "ASRock E3C256D4I BMC"; > + compatible = "asrock,e3c256d4i-bmc", "aspeed,ast2500"; > + > + aliases { > + serial4 = &uart5; > + > + i2c20 = &i2c2mux0ch0; > + i2c21 = &i2c2mux0ch1; > + i2c22 = &i2c2mux0ch2; > + i2c23 = &i2c2mux0ch3; > + }; > + > + chosen { > + stdout-path = &uart5; > + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; Drop bootargs. > + }; > + > + memory@80000000 { > + reg = <0x80000000 0x20000000>; > + }; > + > + leds { > + compatible = "gpio-leds"; > + > + heartbeat { It does not look like you tested the DTS against bindings. Please run `make dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ for instructions). > + gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; > + linux,default-trigger = "timer"; Missing function and color. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC 2023-11-14 20:35 ` Krzysztof Kozlowski @ 2023-11-14 22:21 ` Zev Weiss 2023-11-15 12:13 ` Krzysztof Kozlowski 2023-11-14 22:37 ` Zev Weiss 1 sibling, 1 reply; 11+ messages in thread From: Zev Weiss @ 2023-11-14 22:21 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc On Tue, Nov 14, 2023 at 12:35:37PM PST, Krzysztof Kozlowski wrote: >On 14/11/2023 12:27, Zev Weiss wrote: >> Like the E3C246D4I, this is a reasonably affordable off-the-shelf >> mini-ITX AST2500/Xeon motherboard with good potential as an OpenBMC >> development platform. Booting the host requires a modicum of eSPI >> support that's not yet in the mainline kernel, but most other basic >> BMC functionality is available with this device-tree. >> >> Signed-off-by: Zev Weiss <zev@bewilderbeest.net> >> --- >> arch/arm/boot/dts/aspeed/Makefile | 1 + >> .../aspeed/aspeed-bmc-asrock-e3c256d4i.dts | 314 ++++++++++++++++++ >> 2 files changed, 315 insertions(+) >> create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts >> >> diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile >> index d3ac20e316d0..3398ee53f034 100644 >> --- a/arch/arm/boot/dts/aspeed/Makefile >> +++ b/arch/arm/boot/dts/aspeed/Makefile >> @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ >> aspeed-bmc-ampere-mtmitchell.dtb \ >> aspeed-bmc-arm-stardragon4800-rep2.dtb \ >> aspeed-bmc-asrock-e3c246d4i.dtb \ >> + aspeed-bmc-asrock-e3c256d4i.dtb \ >> aspeed-bmc-asrock-romed8hm3.dtb \ >> aspeed-bmc-bytedance-g220a.dtb \ >> aspeed-bmc-delta-ahe50dc.dtb \ >> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts >> new file mode 100644 >> index 000000000000..4c55272afd4f >> --- /dev/null >> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts >> @@ -0,0 +1,314 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/dts-v1/; >> + >> +#include "aspeed-g5.dtsi" >> +#include <dt-bindings/gpio/aspeed-gpio.h> >> +#include <dt-bindings/i2c/i2c.h> >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/watchdog/aspeed-wdt.h> >> + >> +/{ >> + model = "ASRock E3C256D4I BMC"; >> + compatible = "asrock,e3c256d4i-bmc", "aspeed,ast2500"; >> + >> + aliases { >> + serial4 = &uart5; >> + >> + i2c20 = &i2c2mux0ch0; >> + i2c21 = &i2c2mux0ch1; >> + i2c22 = &i2c2mux0ch2; >> + i2c23 = &i2c2mux0ch3; >> + }; >> + >> + chosen { >> + stdout-path = &uart5; >> + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; > >Drop bootargs. > Ack. >> + }; >> + >> + memory@80000000 { >> + reg = <0x80000000 0x20000000>; >> + }; >> + >> + leds { >> + compatible = "gpio-leds"; >> + >> + heartbeat { > >It does not look like you tested the DTS against bindings. Please run >`make dtbs_check W=1` (see >Documentation/devicetree/bindings/writing-schema.rst or >https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ >for instructions). > Au contraire -- I did, and it exited 0 with no output, which I interpreted as a clean pass. Are there particular shortcomings beside what you've already pointed out that you would have expected it to flag? >> + gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; >> + linux,default-trigger = "timer"; > >Missing function and color. > Ack. Thanks, Zev ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC 2023-11-14 22:21 ` Zev Weiss @ 2023-11-15 12:13 ` Krzysztof Kozlowski 0 siblings, 0 replies; 11+ messages in thread From: Krzysztof Kozlowski @ 2023-11-15 12:13 UTC (permalink / raw) To: Zev Weiss Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc On 14/11/2023 23:21, Zev Weiss wrote: >> It does not look like you tested the DTS against bindings. Please run >> `make dtbs_check W=1` (see >> Documentation/devicetree/bindings/writing-schema.rst or >> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ >> for instructions). >> > > Au contraire -- I did, and it exited 0 with no output, which I > interpreted as a clean pass. Are there particular shortcomings beside > what you've already pointed out that you would have expected it to flag? Then paste entire command result here, including the command you used. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC 2023-11-14 20:35 ` Krzysztof Kozlowski 2023-11-14 22:21 ` Zev Weiss @ 2023-11-14 22:37 ` Zev Weiss 2023-11-14 22:55 ` Zev Weiss 2023-11-15 12:13 ` Krzysztof Kozlowski 1 sibling, 2 replies; 11+ messages in thread From: Zev Weiss @ 2023-11-14 22:37 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc On Tue, Nov 14, 2023 at 12:35:37PM PST, Krzysztof Kozlowski wrote: >On 14/11/2023 12:27, Zev Weiss wrote: >> Like the E3C246D4I, this is a reasonably affordable off-the-shelf >> mini-ITX AST2500/Xeon motherboard with good potential as an OpenBMC >> development platform. Booting the host requires a modicum of eSPI >> support that's not yet in the mainline kernel, but most other basic >> BMC functionality is available with this device-tree. >> >> Signed-off-by: Zev Weiss <zev@bewilderbeest.net> >> --- >> arch/arm/boot/dts/aspeed/Makefile | 1 + >> .../aspeed/aspeed-bmc-asrock-e3c256d4i.dts | 314 ++++++++++++++++++ >> 2 files changed, 315 insertions(+) >> create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts >> >> diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile >> index d3ac20e316d0..3398ee53f034 100644 >> --- a/arch/arm/boot/dts/aspeed/Makefile >> +++ b/arch/arm/boot/dts/aspeed/Makefile >> @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ >> aspeed-bmc-ampere-mtmitchell.dtb \ >> aspeed-bmc-arm-stardragon4800-rep2.dtb \ >> aspeed-bmc-asrock-e3c246d4i.dtb \ >> + aspeed-bmc-asrock-e3c256d4i.dtb \ >> aspeed-bmc-asrock-romed8hm3.dtb \ >> aspeed-bmc-bytedance-g220a.dtb \ >> aspeed-bmc-delta-ahe50dc.dtb \ >> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts >> new file mode 100644 >> index 000000000000..4c55272afd4f >> --- /dev/null >> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts >> @@ -0,0 +1,314 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/dts-v1/; >> + >> +#include "aspeed-g5.dtsi" >> +#include <dt-bindings/gpio/aspeed-gpio.h> >> +#include <dt-bindings/i2c/i2c.h> >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/watchdog/aspeed-wdt.h> >> + >> +/{ >> + model = "ASRock E3C256D4I BMC"; >> + compatible = "asrock,e3c256d4i-bmc", "aspeed,ast2500"; >> + >> + aliases { >> + serial4 = &uart5; >> + >> + i2c20 = &i2c2mux0ch0; >> + i2c21 = &i2c2mux0ch1; >> + i2c22 = &i2c2mux0ch2; >> + i2c23 = &i2c2mux0ch3; >> + }; >> + >> + chosen { >> + stdout-path = &uart5; >> + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; > >Drop bootargs. > Ack. >> + }; >> + >> + memory@80000000 { >> + reg = <0x80000000 0x20000000>; >> + }; >> + >> + leds { >> + compatible = "gpio-leds"; >> + >> + heartbeat { > >It does not look like you tested the DTS against bindings. Please run >`make dtbs_check W=1` (see >Documentation/devicetree/bindings/writing-schema.rst or >https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ >for instructions). > As with my spc621d8hm3 dts patch, I did run that and got no output, so if there are other specific problems please let me know what they are. >> + gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; >> + linux,default-trigger = "timer"; > >Missing function and color. > Ack. Thanks, Zev ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC 2023-11-14 22:37 ` Zev Weiss @ 2023-11-14 22:55 ` Zev Weiss 2023-11-15 12:13 ` Krzysztof Kozlowski 1 sibling, 0 replies; 11+ messages in thread From: Zev Weiss @ 2023-11-14 22:55 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc On Tue, Nov 14, 2023 at 02:37:10PM PST, Zev Weiss wrote: >On Tue, Nov 14, 2023 at 12:35:37PM PST, Krzysztof Kozlowski wrote: >>On 14/11/2023 12:27, Zev Weiss wrote: >>>Like the E3C246D4I, this is a reasonably affordable off-the-shelf >>>mini-ITX AST2500/Xeon motherboard with good potential as an OpenBMC >>>development platform. Booting the host requires a modicum of eSPI >>>support that's not yet in the mainline kernel, but most other basic >>>BMC functionality is available with this device-tree. >>> >>>Signed-off-by: Zev Weiss <zev@bewilderbeest.net> >>>--- >>> arch/arm/boot/dts/aspeed/Makefile | 1 + >>> .../aspeed/aspeed-bmc-asrock-e3c256d4i.dts | 314 ++++++++++++++++++ >>> 2 files changed, 315 insertions(+) >>> create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts >>> >>>diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile >>>index d3ac20e316d0..3398ee53f034 100644 >>>--- a/arch/arm/boot/dts/aspeed/Makefile >>>+++ b/arch/arm/boot/dts/aspeed/Makefile >>>@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ >>> aspeed-bmc-ampere-mtmitchell.dtb \ >>> aspeed-bmc-arm-stardragon4800-rep2.dtb \ >>> aspeed-bmc-asrock-e3c246d4i.dtb \ >>>+ aspeed-bmc-asrock-e3c256d4i.dtb \ >>> aspeed-bmc-asrock-romed8hm3.dtb \ >>> aspeed-bmc-bytedance-g220a.dtb \ >>> aspeed-bmc-delta-ahe50dc.dtb \ >>>diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts >>>new file mode 100644 >>>index 000000000000..4c55272afd4f >>>--- /dev/null >>>+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts >>>@@ -0,0 +1,314 @@ >>>+// SPDX-License-Identifier: GPL-2.0+ >>>+/dts-v1/; >>>+ >>>+#include "aspeed-g5.dtsi" >>>+#include <dt-bindings/gpio/aspeed-gpio.h> >>>+#include <dt-bindings/i2c/i2c.h> >>>+#include <dt-bindings/interrupt-controller/irq.h> >>>+#include <dt-bindings/watchdog/aspeed-wdt.h> >>>+ >>>+/{ >>>+ model = "ASRock E3C256D4I BMC"; >>>+ compatible = "asrock,e3c256d4i-bmc", "aspeed,ast2500"; >>>+ >>>+ aliases { >>>+ serial4 = &uart5; >>>+ >>>+ i2c20 = &i2c2mux0ch0; >>>+ i2c21 = &i2c2mux0ch1; >>>+ i2c22 = &i2c2mux0ch2; >>>+ i2c23 = &i2c2mux0ch3; >>>+ }; >>>+ >>>+ chosen { >>>+ stdout-path = &uart5; >>>+ bootargs = "console=tty0 console=ttyS4,115200 earlycon"; >> >>Drop bootargs. >> > >Ack. > >>>+ }; >>>+ >>>+ memory@80000000 { >>>+ reg = <0x80000000 0x20000000>; >>>+ }; >>>+ >>>+ leds { >>>+ compatible = "gpio-leds"; >>>+ >>>+ heartbeat { >> >>It does not look like you tested the DTS against bindings. Please run >>`make dtbs_check W=1` (see >>Documentation/devicetree/bindings/writing-schema.rst or >>https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ >>for instructions). >> > >As with my spc621d8hm3 dts patch, I did run that and got no output, so >if there are other specific problems please let me know what they are. > Whoops, and of course now I realize I also sent the first reply to this thread instead of the spc621d8hm3 one... Zev ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC 2023-11-14 22:37 ` Zev Weiss 2023-11-14 22:55 ` Zev Weiss @ 2023-11-15 12:13 ` Krzysztof Kozlowski 2023-11-16 2:39 ` Zev Weiss 1 sibling, 1 reply; 11+ messages in thread From: Krzysztof Kozlowski @ 2023-11-15 12:13 UTC (permalink / raw) To: Zev Weiss Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc On 14/11/2023 23:37, Zev Weiss wrote: > >>> + }; >>> + >>> + memory@80000000 { >>> + reg = <0x80000000 0x20000000>; >>> + }; >>> + >>> + leds { >>> + compatible = "gpio-leds"; >>> + >>> + heartbeat { >> >> It does not look like you tested the DTS against bindings. Please run >> `make dtbs_check W=1` (see >> Documentation/devicetree/bindings/writing-schema.rst or >> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ >> for instructions). The node names are clearly wrong and you got output. It's easy to spot if your patch worked in the first place: fatal error: dt-bindings/watchdog/aspeed-wdt.h: No such file or directory Best regards, Krzysztof ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC 2023-11-15 12:13 ` Krzysztof Kozlowski @ 2023-11-16 2:39 ` Zev Weiss 0 siblings, 0 replies; 11+ messages in thread From: Zev Weiss @ 2023-11-16 2:39 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc On Wed, Nov 15, 2023 at 04:13:29AM PST, Krzysztof Kozlowski wrote: >On 14/11/2023 23:37, Zev Weiss wrote: > >> >>>> + }; >>>> + >>>> + memory@80000000 { >>>> + reg = <0x80000000 0x20000000>; >>>> + }; >>>> + >>>> + leds { >>>> + compatible = "gpio-leds"; >>>> + >>>> + heartbeat { >>> >>> It does not look like you tested the DTS against bindings. Please run >>> `make dtbs_check W=1` (see >>> Documentation/devicetree/bindings/writing-schema.rst or >>> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ >>> for instructions). > >The node names are clearly wrong and you got output. It's easy to spot >if your patch worked in the first place: > > fatal error: dt-bindings/watchdog/aspeed-wdt.h: No such file or directory > The patch series was based on Linus's tree at the time I sent it; that file was added in commit 9931be2cfca3 ("dt-bindings: watchdog: aspeed-wdt: Add aspeed,reset-mask property"), which was included in the 6.7-rc1 tag, FWIW. After some debugging I discovered that the reason I wasn't getting any output from dtbs_check was that I had neglected to specify ARCH=arm when invoking it, and when that defaulted to x86 it silently did a whole bunch of nothing. It might be nice if something emitted some sort of warning when invoked with nonsensical parameters (especially if I've explicitly specified a dtstree=... argument pointing to arch/arm/...), but oh well. After re-running it with ARCH=arm, it produced a fairly voluminous spew of output, though after combing through it all as best I can tell only one or two lines of it actually pertain to the .dts in question itself (the vast majority being from a .dtsi it #includes). I've fixed the one remaining issue it reported (missing #address-cells and #size-cells on the FRU eeprom node) and will post a v2 in the next few days (and likewise on the spc621d8hm3 series). Zev ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-11-16 2:39 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-11-14 11:27 [PATCH 0/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC Zev Weiss 2023-11-14 11:27 ` [PATCH 1/2] dt-bindings: arm: aspeed: document ASRock E3C256D4I Zev Weiss 2023-11-14 20:34 ` Krzysztof Kozlowski 2023-11-14 11:27 ` [PATCH 2/2] ARM: dts: aspeed: Add ASRock E3C256D4I BMC Zev Weiss 2023-11-14 20:35 ` Krzysztof Kozlowski 2023-11-14 22:21 ` Zev Weiss 2023-11-15 12:13 ` Krzysztof Kozlowski 2023-11-14 22:37 ` Zev Weiss 2023-11-14 22:55 ` Zev Weiss 2023-11-15 12:13 ` Krzysztof Kozlowski 2023-11-16 2:39 ` Zev Weiss
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