From: Randy Dunlap <rdunlap@infradead.org>
To: Palmer Dabbelt <palmer@sifive.com>,
tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com,
robh+dt@kernel.org, mark.rutland@arm.com
Cc: devicetree@vger.kernel.org, aou@eecs.berkeley.edu,
linux-kernel@vger.kernel.org, Michael Clark <mjc@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
shorne@gmail.com, linux-riscv@lists.infradead.org
Subject: Re: [PATCH 3/3] irqchip: RISC-V Local Interrupt Controller Driver
Date: Fri, 22 Jun 2018 17:08:58 -0700 [thread overview]
Message-ID: <1d55b6ee-2fa4-269b-4166-ffd36646f61f@infradead.org> (raw)
In-Reply-To: <20180622232006.12158-4-palmer@sifive.com>
On 06/22/2018 04:20 PM, Palmer Dabbelt wrote:
> From: Palmer Dabbelt <palmer@dabbelt.com>
>
> This patch adds a driver that manages the local interrupts on each
> RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual.
> The local interrupt controller manages software interrupts, timer
> interrupts, and hardware interrupts (which are routed via the
> platform level interrupt controller). Per-hart local interrupt
> controllers are found on all RISC-V systems.
>
> CC: Michael Clark <mjc@sifive.com>
> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
> ---
> drivers/irqchip/Kconfig | 13 +++
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-riscv-intc.c | 215 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 229 insertions(+)
> create mode 100644 drivers/irqchip/irq-riscv-intc.c
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index e9233db16e03..bf7fc86673b1 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -372,3 +372,16 @@ config QCOM_PDC
> IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
>
> endmenu
> +
> +config RISCV_INTC
> + #bool "RISC-V Interrupt Controller"
Hi,
What does the leading '#' do?
> + depends on RISCV
> + default y
> + help
> + This enables support for the local interrupt controller found in
> + standard RISC-V systems. The local interrupt controller handles
> + timer interrupts, software interrupts, and hardware interrupts.
> + Without a local interrupt controller the system will be unable to
> + handle any interrupts, including those passed via the PLIC.
> +
> + If you don't know what to do here, say Y.
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 15f268f646bf..74e333cc274c 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -87,3 +87,4 @@ obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o
> obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o
> obj-$(CONFIG_NDS32) += irq-ativic32.o
> obj-$(CONFIG_QCOM_PDC) += qcom-pdc.o
> +obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o
--
~Randy
next prev parent reply other threads:[~2018-06-23 0:08 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-22 23:20 Driver for the RISC-V Interrupt Controller Palmer Dabbelt
2018-06-22 23:20 ` [PATCH 1/3] RISC-V: Don't include irq-riscv-intc.h Palmer Dabbelt
2018-06-23 7:25 ` Christoph Hellwig
2018-06-22 23:20 ` [PATCH 2/3] dt-bindings: interrupt-controller: RISC-V local interrupt controller docs Palmer Dabbelt
2018-06-25 20:04 ` Christoph Böhmwalder
2018-08-02 20:30 ` Palmer Dabbelt
2018-07-03 20:10 ` Rob Herring
2018-06-22 23:20 ` [PATCH 3/3] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt
2018-06-23 0:08 ` Randy Dunlap [this message]
2018-08-02 18:30 ` Palmer Dabbelt
2018-06-23 7:28 ` Christoph Hellwig
2018-06-23 8:56 ` Thomas Gleixner
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