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Mon, 12 Oct 2026 03:48:53 -0700 (PDT) X-Received: by 2002:a05:6a00:1f06:b0:87a:23b3:1064 with SMTP id d2e1a72fcca58-897c634e069mr7068328b3a.11.1791802132846; Mon, 12 Oct 2026 03:48:52 -0700 (PDT) Received: from [10.64.69.36] ([114.94.8.21]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-89a0724a045sm1581695b3a.45.2026.10.12.03.48.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 12 Oct 2026 03:48:52 -0700 (PDT) Message-ID: <1d764a3d-7935-4e26-b1c2-92537e1d3811@oss.qualcomm.com> Date: Mon, 12 Oct 2026 18:48:42 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH DNM v3 8/8] arm64: dts: qcom: kaanapali: Add MPAM MSC nodes for the L2 caches To: Rob Herring Cc: James Morse , Shanker Donthineni , Ben Horgan , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich , Reinette Chatre , Fenghua Yu , Jonathan Cameron , Bjorn Andersson , Konrad Dybcio , Gavin Shan , Andre Przywara , Drew Fustini , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , Shaopeng Tan , trilok.soni@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, ganapatrao.kulkarni@oss.qualcomm.com, Srivathsa L Rao , Huang Yiwei , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, driver-core@lists.linux.dev, devicetree@vger.kernel.org References: <20261008-mpam-resctrl-dt-knp-support-v3-0-35196c2b43bf@oss.qualcomm.com> <20261008-mpam-resctrl-dt-knp-support-v3-8-35196c2b43bf@oss.qualcomm.com> <20261008210004.GA1318789-robh@kernel.org> Content-Language: en-US From: Yin Li In-Reply-To: <20261008210004.GA1318789-robh@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEyMDA0MiBTYWx0ZWRfX/QzYxKllc5vt ebP83d7rpH+0fp+ka7GjiMeH+mqGotbF/hfADZAp8X0eq8fHWYY6CD7tyO474tKGJYC546dpmxL UcUOdrw4x05u/AI8dF0GnLAlYZV0bKI= X-Proofpoint-GUID: eOI2fq7i0D8wf4SroB1AaLl3DOSpYm8L X-Proofpoint-ORIG-GUID: eOI2fq7i0D8wf4SroB1AaLl3DOSpYm8L X-Authority-Analysis: v=2.4 cv=ePGGH3p1 c=1 sm=1 tr=0 ts=6accbb16 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=Uz3yg00KUFJ2y2WijEJ4bw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=8_2XKLfCnFwK6P8hJhkA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEyMDA0MiBTYWx0ZWRfX25apflbC9W93 0XvAqUs2gUw7ii3UlYJhaKqzfvqUzANGZJKTNCTqU+cHoytVmAlJVENLpIW6oS4j6dCd8akUx9O 287nfcbteiQ4mSSnB8CeumgKnYtNXA2yGM1wlDVZmoAuWppkxaqsu/1NKU2Esj4jh1CsWDQ3TV5 JpWYAaQ0B6o8op9ZcLhgXElRgh6QFzsmxaCt309wmROtw1lHnIhPmwIvWEnLi/zr6QLQWYcTm6X NDdVr++z12AFqyBnQW6HHDsch3lSehjamv2EHpjXxOE3z7xMvVVuARGI0c2ewLp4cz7tnjGVKm+ IP4pqwSrxDS751CYgY8BITebuQ8OfWwKcB2TUGDk1H4GglFZg0/rE8auDPL8RZWfGYVBVXVP1FL evFntVZ1SyGCfGmVVUzw3Krpe2mQW6nLf3Ji2Fa1cX8Tzdxe6LfP0IO8QA6ru6yiarivFyyRJch XYyu+6vJLr0tsPPaZOg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-12_03,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 malwarescore=0 adultscore=0 bulkscore=0 phishscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610120042 On 10/9/2026 5:00 AM, Rob Herring wrote: > On Thu, Oct 08, 2026 at 02:41:17PM +0800, Yin Li wrote: >> Add an MPAM MSC device node for each L2 cache. Each MSC is nested >> directly under its L2 cache node so that the cache node is the MSC's >> parent device and its CPU affinity is derived from that cache. >> >> The L2 cache nodes are placed directly under the root node. The root is >> the root of the physical address space, so each cache node only needs an >> identity 'ranges' property for its nested MSC's 'reg' to be resolved to >> a physical address. The two caches use distinct node names (l2-cache-0 >> and l2-cache-1) since a cache node has no MMIO unit-address of its own. >> >> The nodes are disabled by default. Production firmware does not expose >> MSC register access to the OS, so these nodes can only be enabled on a >> local test setup where firmware permits direct MMIO access to the MSCs. >> This DTS is therefore only an example for other platform DT authors and >> is not intended to be merged. >> >> Co-developed-by: Huang Yiwei >> Signed-off-by: Huang Yiwei >> Signed-off-by: Yin Li >> --- >> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 50 +++++++++++++++++++++++++-------- >> 1 file changed, 38 insertions(+), 12 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi >> index 131fd2a16c54..b1dcb1e9c570 100644 >> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi >> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi >> @@ -48,12 +48,6 @@ cpu0: cpu@0 { >> power-domains = <&cpu_pd0>, <&scmi_perf 0>; >> power-domain-names = "psci", "perf"; >> #cooling-cells = <2>; >> - >> - l2_0: l2-cache { >> - compatible = "cache"; >> - cache-level = <2>; >> - cache-unified; >> - }; >> }; >> >> cpu1: cpu@100 { >> @@ -120,12 +114,6 @@ cpu6: cpu@10000 { >> power-domains = <&cpu_pd6>, <&scmi_perf 1>; >> power-domain-names = "psci", "perf"; >> #cooling-cells = <2>; >> - >> - l2_1: l2-cache { >> - compatible = "cache"; >> - cache-level = <2>; >> - cache-unified; >> - }; >> }; >> >> cpu7: cpu@10100 { >> @@ -531,6 +519,44 @@ soccp_smp2p_in: slave-kernel { >> }; >> }; >> >> + l2_0: l2-cache-0 { > > cache@19870000 > Hi Rob, Thanks for review. Good point, Will update on next version. >> + compatible = "cache"; > > You need a specific compatible here for your implementation. > Will add a vendor-specific compatible:"qcom,kaanapali-l2-cache", "cache". >> + cache-level = <2>; >> + cache-unified; >> + cache-size = <0xc00000>; >> + ranges; > > Are there any other registers for the cache other than the MSC? If not, > then: > > ranges = <0x0 0x19870000 0x10000>; > > If there are, you need 'reg' here. > There are no other registers under the cache node besides the MSC. Will update ranges and the MSC reg accordingly. >> + >> + #address-cells = <2>; >> + #size-cells = <2>; > > You don't need 64 bits of address and size here. > Agreed, will drop to #address-cells = <1> and #size-cells = <1>. >> + >> + msc@19870000 { >> + compatible = "arm,mpam-msc"; >> + reg = <0x0 0x19870000 0x0 0x10000>; > > The MPAM register length is 0x321C. > You are right, the MPAM register space is 0x321c per the specification. Will update accordingly. Thanks, Yin > Rob -- Thx and BRs, Yin