From: Marek Vasut <marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Alexandru Gagniuc
<alex.g-JVBBi1ABkv5Wk0Htik3J/w@public.gmane.org>,
linux-snps-arc-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: David Woodhouse <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
Brian Norris
<computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Boris Brezillon
<boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Richard Weinberger <richard-/L3Ra7n9ekc@public.gmane.org>,
Cyrille Pitchen
<cyrille.pitchen-yU5RGvR974pGWvitb5QawA@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 4/5] mtd: spi-nor: Add driver for Adaptrum Anarion QSPI controller
Date: Tue, 1 Aug 2017 00:43:41 +0200 [thread overview]
Message-ID: <1da97744-bc02-420e-d4e9-5ebf331475e8@gmail.com> (raw)
In-Reply-To: <e1390c36-086b-aeba-848c-f45dcb88b5ce-JVBBi1ABkv5Wk0Htik3J/w@public.gmane.org>
On 08/01/2017 12:20 AM, Alexandru Gagniuc wrote:
> On 07/31/2017 02:33 PM, Marek Vasut wrote:
>> On 07/31/2017 07:17 PM, Alexandru Gagniuc wrote:
>
> Hi Marek,
>
> Thank you again for your feedback. I've applied a majority of your
> suggestions, and I am very happy with the result. I should have v2
> posted within a day or so.
No. You should have v2 out in about a week or so after people have time
to review v1 some more.
> [snip]
>>>>> +/*
>>>>> + * This mask does not match reality. Get over it:
>>>>
>>>> What is this about ?
>>>
>>> Each stage of the QSPI chain has two registers. The second register has
>>> a bitfield which takes in the length of the stage. For example, for
>>> DATA2, we can set the length up to 0x4000, but for ADDR2, we can only
>>> set a max of 4 bytes. I wrote this comment as a reminder to myself to be
>>> careful about using this mask. I'll rephrase the comment for [v2]
>>
>> Please do.
>>
> Staged for [PATCH v2]
>
>>>>> + * DATA2: 0x3fff
>>>>> + * CMD2: 0x0003
>>>>> + * ADDR2: 0x0007
>>>>> + * PERF2: 0x0000
>>>>> + * HI_Z: 0x003f
>>>>> + * BCNT: 0x0007
>>>>> + */
>>>>> +#define CHAIN_LEN(x) ((x - 1) & ASPI_DATA_LEN_MASK)
btw parenthesis around (x) missing, although this is like GEN_MASK() or
something here ...
>>>>> +struct anarion_qspi {
>>>>> + struct spi_nor nor;
>>>>> + struct device *dev;
>>>>> + uintptr_t regbase;
>>>>
>>>> Should be void __iomem * I guess ?
>>>
>>> I chose uintptr_t as opposed to void *, because arithmetic on void * is
>>> not valid in C. What is the right answer hen, without risking undefined
>>> behavior?
>>
>> What sort of arithmetic ? It's perfectly valid in general ...
>
> ISO/IEC 9899:201x, Section 6.5.6, constraint(2) is not met when the one
> of the operands to addition is a void pointer.
> Section 6.2.5 (19) defines void to be an incomplete type.
Is that something new in C 201x draft ? Anyway, this would mean half of
the drivers are broken, so I'm not convinced.
> [snip]
>
>>>> Is this stuff below something like ioread32_rep() ?
>>>>
>>>>> + aspi_write_reg(aspi, ASPI_REG_BYTE_COUNT, sizeof(uint32_t));
>>>>> + while (len >= 4) {
>>>>> + data = aspi_read_reg(aspi, ASPI_REG_DATA1);
>>>>> + memcpy(buf, &data, sizeof(data));
>>>>> + buf += 4;
>>>>> + len -= 4;
>>>>> + }
>>>
>>> That is very similar to ioread32_rep, yes. I kept this as for the
>>> reasons outlined above, but changing this to _rep() seems innocent
>>> enough.
>>
>> What reason ?
>
> Being able to share the code between the different codebases where it is
> used.
Yes, that argument isn't gonna work, it'd make things impossible to
maintain in the kernel.
--
Best regards,
Marek Vasut
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next prev parent reply other threads:[~2017-07-31 22:43 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20170728220707.13960-1-alex.g@adaptrum.com>
2017-07-28 22:07 ` [PATCH 1/5] of: Add vendor prefix for Adaptrum, Inc Alexandru Gagniuc
[not found] ` <20170728220707.13960-2-alex.g-JVBBi1ABkv5Wk0Htik3J/w@public.gmane.org>
2017-07-29 14:48 ` Andreas Färber
2017-08-03 23:25 ` Rob Herring
2017-08-04 19:58 ` [PATCH v2] dt-bindings: " Alexandru Gagniuc
[not found] ` <20170804195833.15286-1-alex.g-JVBBi1ABkv5Wk0Htik3J/w@public.gmane.org>
2017-08-10 19:30 ` Rob Herring
2017-07-28 22:07 ` [PATCH 3/5] net: stmmac: Add Adaptrum Anarion GMAC glue layer Alexandru Gagniuc
[not found] ` <20170728220707.13960-4-alex.g-JVBBi1ABkv5Wk0Htik3J/w@public.gmane.org>
2017-07-29 2:01 ` David Miller
2017-07-31 15:11 ` Alex
2017-08-03 23:22 ` Rob Herring
2017-08-03 23:26 ` Rob Herring
2017-07-28 22:07 ` [PATCH 4/5] mtd: spi-nor: Add driver for Adaptrum Anarion QSPI controller Alexandru Gagniuc
2017-07-29 9:34 ` Marek Vasut
[not found] ` <135fdf95-1029-2d34-2802-1283a73588e5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-07-31 17:17 ` Alexandru Gagniuc
[not found] ` <83a4e27a-b96c-0558-fbb5-10e64f9bf59b-JVBBi1ABkv5Wk0Htik3J/w@public.gmane.org>
2017-07-31 21:33 ` Marek Vasut
[not found] ` <e7c916c4-7b0a-1f76-b91f-5befeb24faf5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-07-31 22:20 ` Alexandru Gagniuc
[not found] ` <e1390c36-086b-aeba-848c-f45dcb88b5ce-JVBBi1ABkv5Wk0Htik3J/w@public.gmane.org>
2017-07-31 22:43 ` Marek Vasut [this message]
[not found] ` <1da97744-bc02-420e-d4e9-5ebf331475e8-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-07-31 22:59 ` Alexandru Gagniuc
2017-07-31 20:54 ` Alexandru Gagniuc
2017-07-31 21:35 ` Marek Vasut
[not found] ` <20170728220707.13960-5-alex.g-JVBBi1ABkv5Wk0Htik3J/w@public.gmane.org>
2017-07-29 19:03 ` kbuild test robot
2017-07-28 22:07 ` [PATCH 5/5] ARC: DTS: Add device-tree for Anarion-based development board Alexandru Gagniuc
2017-07-31 6:32 ` Vineet Gupta
[not found] ` <8576ceb3-036f-6357-fb52-b062dfe5fa57-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
2017-07-31 15:08 ` Alex
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