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[2003:f6:ef1c:c500:ee59:d953:f148:40ba]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8d25a258a3sm344254966b.89.2024.09.09.06.59.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Sep 2024 06:59:08 -0700 (PDT) Message-ID: <1dca9ce52e7c701c7fb6cbbc723e9dff5d0ace8b.camel@gmail.com> Subject: Re: [PATCH v2 1/9] dt-bindings: iio: dac: ad3552r: add io-backend property From: Nuno =?ISO-8859-1?Q?S=E1?= To: Conor Dooley , Jonathan Cameron Cc: Angelo Dureghello , Lars-Peter Clausen , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, David Lechner Date: Mon, 09 Sep 2024 16:03:17 +0200 In-Reply-To: <20240909-dwelled-specimen-949f44c8d04d@wendy> References: <20240905-wip-bl-ad3552r-axi-v0-iio-testing-v2-0-87d669674c00@baylibre.com> <20240905-wip-bl-ad3552r-axi-v0-iio-testing-v2-1-87d669674c00@baylibre.com> <20240908132925.331c5175@jic23-huawei> <20240909-dwelled-specimen-949f44c8d04d@wendy> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mon, 2024-09-09 at 13:46 +0100, Conor Dooley wrote: > On Sun, Sep 08, 2024 at 01:29:25PM +0100, Jonathan Cameron wrote: > > On Thu, 05 Sep 2024 17:17:31 +0200 > > Angelo Dureghello wrote: > >=20 > > > From: Angelo Dureghello > > >=20 > > > There is a version AXI DAC IP block (for FPGAs) that provides > > > a physical bus for AD3552R and similar chips. This can be used > > > instead of a typical SPI controller to be able to use the chip > > > in ways that typical SPI controllers are not capable of. > > >=20 > > > The binding is modified so that either the device is a SPI > > > peripheral or it uses an io-backend. > > >=20 > > > Signed-off-by: Angelo Dureghello > >=20 > > > =C2=A0 > > > =C2=A0required: > > > =C2=A0=C2=A0 - compatible > > > -=C2=A0 - reg > > > -=C2=A0 - spi-max-frequency > > Sort of feels like both reg and spi-max-frequency > > are valid things to specify.=20 > >=20 > > Maybe we have an excellent IP and dodgy wiring so want > > to clamp the frequency (long term - don't need to support > > in the driver today). > >=20 > > Maybe we have an axi_dac IP that supports multiple > > front end devices?=C2=A0 So maybe just keep reg? >=20 > I'd like to be convinced that this incarnation of the AXI DAC IP is not > a spi controller and that a ref to spi-controller.yaml is not out of > place here. It may not be something that you'd ever use generally, given > the "weird" interface to it, but it does seem to be one regardless. >=20 Agreed.. As weird as it get's, it's acting as a spi controller. > I'd also really like to know how this fits in with spi-offloads. It > /feels/, and I'd like to reiterate the word feels, like a rather similar > idea just applied to a DAC instead of an ADC. The offload main principle is to replay a spi transfer periodically given a= n input trigger. I'm not so sure we have that same principle in here. In here= I guess we stream data over the qspi interface based on SCLK which can look similar. The difference is that this IP does not need any trigger for any s= pi transfer replay (I think).=20 - Nuno S=C3=A1