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Mon, 12 Jun 2023 20:46:22 +0000 Received: from DB9PR03MB8847.eurprd03.prod.outlook.com ([fe80::d632:8122:75f7:7b0e]) by DB9PR03MB8847.eurprd03.prod.outlook.com ([fe80::d632:8122:75f7:7b0e%3]) with mapi id 15.20.6455.045; Mon, 12 Jun 2023 20:46:21 +0000 Message-ID: <1dd01fe2-08a8-ec2f-1184-a58b2f55ba85@seco.com> Date: Mon, 12 Jun 2023 16:46:16 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: Re: [PATCH v14 00/15] phy: Add support for Lynx 10G SerDes Content-Language: en-US To: Vladimir Oltean Cc: Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, Madalin Bucur , linux-arm-kernel@lists.infradead.org, Camelia Alexandra Groza , devicetree@vger.kernel.org, Rob Herring , linuxppc-dev@lists.ozlabs.org, Bagas Sanjaya , Krzysztof Kozlowski , Ioana Ciornei , Bartosz Golaszewski , =?UTF-8?B?RmVybuKUnMOtbmRleiBSb2phcw==?= , Jonas Gorski , Jonathan Corbet , Li Yang , Linus Walleij , Michael Turquette , Shawn Guo , Stephen Boyd , linux-clk@vger.kernel.org, linux-doc@vger.kernel.org, linux-gpio@vger.kernel.org References: <20230426105140.t4yqv6irtjcwptm5@skbuf> <7c7ab84b-3c4a-4e44-b5b5-4acf733a0246@seco.com> <7c7ab84b-3c4a-4e44-b5b5-4acf733a0246@seco.com> <20230429172422.vc35tnwkekfieoru@skbuf> <20230522150010.q5zndfwcuvrb6pg2@skbuf> <22a28a6f-2c84-a6b1-bb57-a269af34c993@seco.com> <20230610222123.mzmfjx7zfw4nh2lo@skbuf> <20230612163353.dwouatvqbuo6h4ea@skbuf> From: Sean Anderson In-Reply-To: <20230612163353.dwouatvqbuo6h4ea@skbuf> Content-Type: text/plain; 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X-OriginatorOrg: seco.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2023 20:46:30.6334 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d57c4d5-9fe1-400d-a7fd-08db6b8619dd X-MS-Exchange-CrossTenant-Id: bebe97c3-6438-442e-ade3-ff17aa50e733 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=bebe97c3-6438-442e-ade3-ff17aa50e733;Ip=[20.160.56.86];Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: AM6EUR05FT025.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB7169 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 6/12/23 12:33, Vladimir Oltean wrote: > On Mon, Jun 12, 2023 at 10:35:21AM -0400, Sean Anderson wrote: >> > And if SERDES protocol switching was not physically possible, would this >> > patch set still have value? More to the point, did you make any progress in this area? >> Yes. To e.g. set up SGMII25 or to fix the clocking situation. > > Let me analyze the reasons one by one. > > The clocking situation only exists due to a hope that protocol changing > would be possible. If you were sure it wasn't possible, your board would > have had refclks set up for protocol 3333 via the supported PLL mapping 2222. > In essence, I consider this almost a non-argument, as it fixes a > self-inflicted problem. 2222 also does not work, as outlined above. The clocking is incompatible, and must be fixed by software. The only thing self-inflicted is NXP's conflicting design. > Have you actually tested changing individual lanes from SGMII to SGMII 2.5? > I know it works on LS1028A, but I don't know if that's also true on LS1046A. > Your comments do say "LYNX_PROTO_SGMII25, /* Not tested */". Not yet. This driver would also be a good place to add the KR link training with NXP tried to upstream a few years ago. > Assuming a start from SERDES protocol 3333 with PLL mapping 2222, > this protocol change implies powering on PLL 1 (reset state machine > wants it to be disabled) and moving those lanes from PLL 2 to PLL 1. > > At first sight you might appear to have a point related to the fact that > PLL register writes are necessary, and thus this whole shebang is necessary. > But this can all be done using PBI commands, with the added benefit that > U-Boot can also use those SERDES networking ports, and not just Linux. > You can use the RCW+PBL specific to your board to inform the SoC that > your platform's refclk 1 is 156 MHz (something which the reset state > machine seems unable to learn, with protocol 0x3333). You don't have to > put that in the device tree. You don't have to push code to any open > source project to expose your platform specific details. Then, just like > in the case of the Lynx 28G driver on LX2160, the SERDES driver could > just treat the PLL configuration as read-only, which would greatly > simplify things and eliminate the need for a clk driver. > > Here is an illustrative example (sorry, I don't have a board with the > right refclk on that PLL, to verify all the way): > > ... snip ... (which of course complicates the process of building the PBIs...) > In short, I believe the reasons you have cited do not justify the > complexity of the solution that you propose. The work is done, and it is certainly more flexible than what you propose. E.g. imagine a clock which needs to be configured before it has the correct frequency. Such a thing is difficult to do in a PBI solution, but is trivial in Linux. --Sean