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([2a05:6e02:1041:c10:55a2:c282:5ca3:a855]) by smtp.googlemail.com with ESMTPSA id y11-20020adff6cb000000b0032fc609c118sm4397265wrp.66.2023.11.08.01.10.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Nov 2023 01:10:37 -0800 (PST) Message-ID: <1dd3d765-c583-4db9-a0aa-303bfcf871db@linaro.org> Date: Wed, 8 Nov 2023 10:10:36 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 2/3] clocksource: Add JH7110 timer driver Content-Language: en-US To: Xingyu Wu Cc: Thomas Gleixner , Emil Renner Berthing , Christophe JAILLET , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Walker Chen , Samin Guo , linux-kernel@vger.kernel.org, Conor Dooley References: <20231019053501.46899-1-xingyu.wu@starfivetech.com> <20231019053501.46899-3-xingyu.wu@starfivetech.com> <3f76f965-7c7b-109e-2ee0-3033e332e84b@linaro.org> <540136d4-6f8f-49a6-80ff-cc621f2f462b@starfivetech.com> <65c38717-3e0c-46d3-a124-29cae48f1a2e@linaro.org> <72ad5029-42b2-481a-887f-8f6079d8859b@starfivetech.com> From: Daniel Lezcano In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 08/11/2023 04:45, Xingyu Wu wrote: > On 2023/11/2 22:29, Daniel Lezcano wrote: [ ... ] > Thanks. The riscv-timer has a clocksource with a higher rating but a > clockevent with lower rating[1] than jh7110-timer. I tested the > jh7110-timer as clockevent and flagged as one shot, which could do > some of the works instead of riscv-timer. And the current_clockevent > changed to jh7110-timer. > > Because the jh7110-timer works as clocksource with lower rating and > only will be used as global timer at CPU idle time. Is it necessary > to be registered as clocksource? If not, should it just be registered > as clockevent? Yes, you can register the clockevent without the clocksource. You mentioned the JH7110 has a better rating than the CPU architected timers. The rating is there to "choose" the best timer, so it is up to the author of the driver check against which timers it compares on the platform. Usually, CPU timers are the best. It is surprising the timer-riscv has a so low rating. You may double check if jh7110 is really better. If it is the case, then implementing a clockevent per cpu would make more sense, otherwise one clockevent as a global timer is enough. Unused clocksource, clockevents should be stopped in case the firmware let them in a undetermined state. > [1] > https://git.kernel.org/pub/scm/linux/kernel/git/thermal/linux.git/tree/drivers/clocksource/timer-riscv.c#n45 > > Thanks, Xingyu Wu -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog