From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CF6838D3E0; Fri, 12 Jun 2026 11:14:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781262852; cv=none; b=BxiuIj/8HqvDU522/2nevoUHdAzmA93KNErr2zOpYG/VbnLlWDHObHfM8c/FmE5Xa/ojdEsqKih1P8MNq2Vbo7ETd8AIJc5/iG17KjNFw4fXGUd8L1HOBdqABFbX3d99nufgx9mwX07K544yu4ayNRr+ouX0mYfubWqpG9vA44M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781262852; c=relaxed/simple; bh=NQzWXkEcu6HV2BAhZhYf7mM7q2QTMJqC9HwiVI/8xrg=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=WxDZuFFianNOKoZh0dV/ovulBqY1c0aeA2Q+tSHYrL1dXOvME6rj/nUBSkaUa0heLFDQRvoQzxSuF3zy5vV9XLvk3y1G2bORX1OA8OmbBaNRpeGwrbnluwhpksenXrVg5qWkCTD4nR9l87sa6w59jirP+RvWoUZpeYXgJ7UZhUg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NbY3nnBv; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NbY3nnBv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 379951F000E9; Fri, 12 Jun 2026 11:14:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781262850; bh=PZChMkC0kAP/BeBXhnEtdpKNR5h+zkzjl05C4+3VQCE=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=NbY3nnBvPtC0c76fY6r1x7jGxNbMEWUItTLyhPzrMo8kOPBrajgapqOcnXV+b5sQE 7d27Gf9zBMcB0QT66Fl2VJoF17+vPCENUy6Kd08N1eW+8Ntk3OeJqWSS+oOTGNIZeB CAAn3eJMfz88QKlmg7S/XQVpLXgopFkcUU8nOGu44xaeqIF1HngRhkaf1Z6iQoxVCi sAilo/FxtRvdEleQ1LPGrs5qkBRw/ug8KNvbqK3AMOqxMoNHVAJLuy2Vnir81BNMnr f3lAk/M8sAWYpfTWjqzThFr/n96JL5jXg4R7jOOdJpS3vtAxJCYP8WmZPL8aGtSWev 8tYRXwZdQSz4g== Message-ID: <1de2f9bf-b48c-4acb-882c-9e35a8582d0b@kernel.org> Date: Fri, 12 Jun 2026 12:14:06 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/3] clk: qcom: camcc-glymur: Add camera clock controller driver To: Konrad Dybcio , Jagadeesh Kona , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das References: <20260517-glymur_camcc-v4-0-9d00acffdbf7@oss.qualcomm.com> <20260517-glymur_camcc-v4-2-9d00acffdbf7@oss.qualcomm.com> <8bd4365e-0171-425c-9738-0b186047cb15@kernel.org> <2a496bdf-4728-47b9-84ba-063712a6e5b6@oss.qualcomm.com> <0a197b43-a672-4849-91c7-6e5bfe3175f7@kernel.org> <66335474-d600-45ab-9ac6-e946f24142c8@oss.qualcomm.com> <639c94f9-6f62-4502-ad7e-5ae60f5f6d02@kernel.org> <10c2e008-74fe-4dac-99bf-194a1767bc16@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-US Autocrypt: addr=bod@kernel.org; keydata= xsFNBGRJNSgBEADD7Vm2ZFa+v+JGJ2QYTJqQAkqis/uOHkhdFNXqpBarVBd47QU/DMNU5Rxg jedMQEmHoeDbJ6UOpjbrUQ63c5sgG1JbroHJJctwsEI75OOlekMuebEbjIJBLfgENGwPBMHv piv5TgCWr0VgYaXfp2eh2LINFywzqj823HiDPibQAXDrjzvF1ogksi/6cQZs8d4if8YQkLOr YISFouG+eR0nN1I7mUfIddXOWu6lJeTyqbWVurv58k2ekIXKaOC9ixLHFbcfYV0hOgRaTwQC B8CYF9nfqZla19iItfsN9QxN+ZdQjcRoYipp6HPCMfJlKH7GfaFcW93LKc4DKJ2lVL+pg/OQ lythZbjRPY492NG9kZ65aYstCs90uhMUEVVPuGUw7wBEku+6IEwZfrbMVKeWzLlPyM4Hv9hM 8ktxSmxWsPTPqpBC8eyeAQLalMELAyVcZlkaCtEcbj7w4l/JkYz+4l37obG8ZD+B34udBUUz MsAJ8foDFrBh2MOFA3hxD6G90D23mmWsri7pnKA2tZs92aQX7Ee+FbCyg6g5ln62Sq83ZDbf 53DdBs55EVpBadeInWmXhzCHPQx06H+CwTEjShTYIaMmBfrewvYUDKvFTC5iKQhAEUgt6i94 JsbG7NoeqcxkUMcBOEUQ3uCQG1D70ugspgXc0wd3Rimiq6535wARAQABzSFCcnlhbiBPJ0Rv bm9naHVlIDxib2RAa2VybmVsLm9yZz7CwZEEEwEIADsWIQTmk/sqq6Nt4Rerb7QicTuzoY3I OgUCZ+R+mwIbAwULCQgHAgIiAgYVCgkICwIEFgIDAQIeBwIXgAAKCRAicTuzoY3IOimUD/94 BwVEJX31JRe2sxbB/e1w2p8x1bxvTw5AeIzpV3ox7coJg1bSU2mnGuj1V4o0Yxf/3zmcJzCN VfVjwRF8Ii3GnC7uUXk2t+87piQfKTyJAYQABhZUKgoVJbjJq/S+C3XCKIyBA+EiezoUsgsA jTzwU+FzV7zVWIXFPJNtBERLwboE9w9U3KjAExOa1kSY8eLrsg6kOwlOHWy5UsQqYOjrS96M mzm2xuc1+RCjrndAyYhCnrOKvJ67HsPnBeJCjw7ImGD/U1GchwYbX8o3DO3JNHm3qfC86ZqX 2sCouENg4OzgPTtLKUrueM6xsu6KMM7gj17vxsiR3KQEoJnnMB8D1xtBofN3mFZE0wD9M24m 8yGunZbtntMCUHzIrlJgAPwKWKuGOYtA8UgMTFkccnUJtQrg9KotKtEF/FuftG9zLG9XEkt4 5ZdNgbSoLWgelu3T47mbOJ8LHhiLaCWP7yrovtVAvLUQ1BsiA42u8ECrFCFvQj9nrejE/ICv kP+uqcKtdDvP9HrIGycF1WZyfZLp0RvopKW92FLvI4I1QFWJ+wenk6+LGyJ5bzlrWzevjxmf nHcXE6sJBHrE7eijlbbImDAi3uLYN8Nd9Dm11IDAy4GAIQxSiQn0yblDhPiyGtchy80EVkCm g9k17Wol+2E2mC4DKgVdCkyUtTRSLgsJCs7BTQRkSTUoARAAuTnmWHBS6izRcEE93ajpzI7h dgQO4U3IRvOEsvIKR5NGcNEs0ngGebwsZ/lVULjN4vYU0LleqVhPBidNXUoZCN3A0F0Z2Ov8 NZdef+2EhQPBVWxFO7JBzhe8Z3ALj+wFtlg8akJjBzU56azW/iJzAobqHVrudzKoO2b1/CMg VbiAQ+RXjgfN5kY/HqYDU7mw+hXuUV9PbtX1L8xqQQac95oM9rHzKHHpiVwxTeJnGQsa+THi Kze+YET3rCoGHMvOQEJhdrucTv5FpAakKdkOFNel9FFckLRKEuWgCzhpFsjQ7xbirQgFUxG9 vlk1+q4hMRGNyEqoD6svYEeqbiUSd0oPUJeioiC3rNMRCNHLVrfZ2J6SCPkxfda08uzSdDQU 1/YPjOh8ZtQDMu7WctZ3XO288Z1gyBR49V7fbFs2w4sQxG+h/enlxqP7fdw1mjUlZjU5huCJ ielS0oEaIpmUpkugli7x4WhwLnhK2EbSoz7nLBC0y+ALUOdMlz/Y1l9xRt+bkDhpmf4O4IcI MxgZ0QMLq8rHDkGaEbsgZZHQPS58T0XE3IP30Q9SNxsruCMXtd2hYtBssf/wohc6JVsTtMg2 VYTPDPIFNZFSXupEJB7jlqpDWJ8ooJfJRLBatbjT5+mVQaMYB7Hs/t+zWYWaJKHyc8O6WLEC NUV5Tdt5EkkAEQEAAcLBdgQYAQoAIBYhBOaT+yqro23hF6tvtCJxO7Ohjcg6BQJkSTUoAhsM AAoJECJxO7Ohjcg6LuIQALnXt36OUuK43wqw6UYt0cnN6EbUqJHApAF5eNFn0jCCB2XELjSz JKJwuNAweowBdabiBniJ+501WIW+ewEsz1uby5fUQjZuCEsIkuaIluyfUFPb73qrQyAGuusd 7teA4WT+/jUku9g7lX5sVoRCrKQPkd16f6Bzfztyqyjcn43/X5yQI+wlboQ6HuKe/3I3yiOx OgmCHzOawpC9PvhEcKj79RLM3Zz5Ts5AuHpRX70Jz8Be76LwVFLp5Msx3S24ZTU1lBo2uiJ3 xSkay2lTpyVWRPx9vgcwzxGguOPJQJwsQeLb7wpoJMPpD3ERoaRii7Q7hvmxklpZjhKYWB3d t6nQ497Ek9loCrp3MIjRCSDN5xEGffiHks9yTeGMUQwO4tX8RE04uOJPkUY7uCFzFqN6/qey X3oFfPgkULMdiHofPAL1OskZSTzGPSfTYRE46NCJw8yoZBQ/oOyWeqaUQbK0wmW/g81wm8p7 LKSGEglMpiX07M1AotgvylN5C8fjbouoK+/RAMsXkk8jba6rPfuuXPaDjCyyKn6zSVHETnHW 3AJbgVY50T8STpnxayBQvWbCvu+6NOEjXCbyaOJig+5l0zlGN9XHjdANXC5HnwmyaGRL9YDq Jh2nVXVJDincOdQRdKcJjYLqaOAoWrYWSDi1iZGspHBTDrnOvfMQzzHY In-Reply-To: <10c2e008-74fe-4dac-99bf-194a1767bc16@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 11/06/2026 09:51, Konrad Dybcio wrote: >>> implementation simpler, avoids unnecessary abstraction, and makes debugging—through direct >>> comparison with the hardware spec easier. >> How are hex values in upstream code easier to debug ? >> >> Without the spec you can't change or understand hex values in upstream code, which is the whole point I'm making here. > I get the 'understanding' part, but regarding change, as I said > previously, these must remain as-is - any difference for a PLL > impacts every single clock downstream of it. Some of them also > correspond to specific electrical properties, just like with PHY > init sequences. The existing values are a result of tuning and > silicon validation across presumably many, many chip units. That's an argument against changing the values, not naming the values. Hexwork in upstream code is a public black box and should be avoided where possible. How about, take these fixed hex but someone on the clock-side in qcom agrees to update the script to write defined bitfields not hexwork in future deliveries. AFAIU its a script that mostly spits out these clock descriptors so, it should be possible to fix that script once @ source, without committing to fixing everything _currently_ in flight. Qcom can then at its leisure update old controller descriptors by running the script again. > There may be updates (very rarely post the chip going into > production), but I'd assume these would go through the same > testing procedures > > Konrad --- bod