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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b942ef48267sm494734566b.3.2026.03.10.08.15.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Mar 2026 08:15:02 -0700 (PDT) Message-ID: <1df08447-0ace-4771-bc1c-b0f8c5d0f9b2@oss.qualcomm.com> Date: Tue, 10 Mar 2026 16:15:00 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] clk: qcom: Add Global Clock controller (GCC) driver for Fillmore To: Aelin Reidel , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@mainlining.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht References: <20260308-fillmore-clks-v1-0-976d9a6bebe7@mainlining.org> <20260308-fillmore-clks-v1-3-976d9a6bebe7@mainlining.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260308-fillmore-clks-v1-3-976d9a6bebe7@mainlining.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=c9WmgB9l c=1 sm=1 tr=0 ts=69b03578 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=OuZLqq7tAAAA:8 a=3zzezIjtfV0i2P62deAA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=AKGiAy9iJ-JzxKVHQNES:22 X-Proofpoint-ORIG-GUID: MrVGxMI2xOoy6xUFsWcervN4J9pzVKYP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDEzMiBTYWx0ZWRfXxodn0VMePwXz mS3MqxtqU4XL9pYkyl3N6Cky4rJ2/lGUyd3YEAdAYz9Jgv4Zi3KD/i6A4eiybEm1xMaTdxEAmGH MPT+F2Ov4fxbCD+bWdJABWucIfbKJ1YQ0tOl768FfDz6fNJ0nB8dl/5X6fSPDv9J8VxjD+4kJeQ H9IhOilckaJ1Zdhy6kxkGR5D2rQqiAV8cdEIEejZZlFKSRQrqG72WR/+8XlnnG8L/OgYwwA0076 mNE7U+UYMrUJkir+dS3wTiQBMXx2Xp81yn4o3r1YJPFCjFfCzXTMYM6USM05DOKUzMavsUElANY CDzE6D2Q7YJCn8SBAe+LVVZPXaktnJdbF8MffkT28ww06xBdFn1OCaq3VT5uB0X0jcYZMsKUcAg iWkrvT4vLXE6dP9zR1NEz17UM1bC8o3RfDe0YpuTEWPfpjWPfXaKLldqvPwRWZ7CTT2cIWj+7Go 4mnlF7q6SQ5eOMTQJNw== X-Proofpoint-GUID: MrVGxMI2xOoy6xUFsWcervN4J9pzVKYP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_03,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 clxscore=1015 impostorscore=0 phishscore=0 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603100132 On 3/8/26 1:39 AM, Aelin Reidel wrote: > Add support for the global clock controller found on Fillmore (e.g. SM7450) > based devices. > > Signed-off-by: Aelin Reidel > --- [...] > +static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { This one's a clk_regmap_phy_mux (see other clk drivers for what to change) [...] > +static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { likewise [...] > +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { > + F(400000, P_BI_TCXO, 12, 1, 4), > + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), > + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), > + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), > + F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { > + .cmd_rcgr = 0x24014, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = gcc_parent_map_5, > + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gcc_sdcc2_apps_clk_src", > + .parent_data = gcc_parent_data_5, > + .num_parents = ARRAY_SIZE(gcc_parent_data_5), .flags = CLK_OPS_PARENT_ENABLE, > + .ops = &clk_rcg2_ops, &clk_rcg2_shared_floor_ops [...] > +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { > + .cmd_rcgr = 0x8702c, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = gcc_parent_map_10, > + .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gcc_ufs_phy_axi_clk_src", > + .parent_data = gcc_parent_data_10, > + .num_parents = ARRAY_SIZE(gcc_parent_data_10), > + .ops = &clk_rcg2_ops, > + }, > +}; please check for .enable_safe_parent or something like that in the downstream driver - for all RCGs that have it, use clk_rcg2_shared_ops [...] > +static struct gdsc pcie_0_gdsc = { > + .gdscr = 0x7b004, > + .pd = { > + .name = "pcie_0_gdsc", > + }, > + .pwrsts = PWRSTS_RET_ON, > +}; > + > +static struct gdsc ufs_phy_gdsc = { > + .gdscr = 0x87004, > + .pd = { > + .name = "ufs_phy_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > +}; > + > +static struct gdsc usb30_prim_gdsc = { > + .gdscr = 0x49004, > + .pd = { > + .name = "usb30_prim_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > +}; Your downstream DT also has: HLOS1_VOTE_MMNOC_MMU_TBU_HF[0123] _SF[01] _TBU[01] that all need to be defined and have .flags = VOTABLE Konrad