From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A11CA86330; Tue, 7 Jan 2025 14:56:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736261796; cv=none; b=jx/+mIpGuFvm/YsAO+89A08I1+cQEJ3szw53USNCeCoyfTnqEJMJgjpb1n+TjNxno+amTolRH0JpM43HFOLVnkZ4JfdUzF+KhB4a3fZxc5WQ472bwwBOEazF4pncpyqlIwYHn5bkHyCK+AnugyOGYckPv5QOMvPv/oBzGEqQlFQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736261796; c=relaxed/simple; bh=g3iUuiNiB2bePoFIB2zbdPbAU751FxV8YFxyGzk8bOc=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=g87XXgSmPUUSUkPKI2b6RZagnf8UWOC9iL1swo/8mIgGXPQ9HciYP+BdcfoUiW8hhD2je2CHLt4ZgcqiIEQ5oTcQXk4vPfi0Ma2/xPlqnmfLgOMnjZbxG2BjRKlwnlmJok5Sydf0IFf8GBLVxhoxJqaptHHgMNcYba3IQc2HETA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3DC5E1424; Tue, 7 Jan 2025 06:57:01 -0800 (PST) Received: from [10.57.4.77] (unknown [10.57.4.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 76BCE3F673; Tue, 7 Jan 2025 06:56:31 -0800 (PST) Message-ID: <1e1915eb-0ebb-4afa-94ed-553c455ae24e@arm.com> Date: Tue, 7 Jan 2025 14:56:30 +0000 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities Content-Language: en-GB To: Jessica Clarke Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Linus Walleij , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King References: <20250103181623.1980433-1-vincenzo.frascino@arm.com> <20250103181623.1980433-3-vincenzo.frascino@arm.com> <45E38F12-3585-4AE0-8F05-431DB355FC69@jrtc27.com> From: Vincenzo Frascino In-Reply-To: <45E38F12-3585-4AE0-8F05-431DB355FC69@jrtc27.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 07/01/2025 14:51, Jessica Clarke wrote: > On 7 Jan 2025, at 14:34, Vincenzo Frascino wrote: >> >> Hi Jessica, >> >> Thank you for your review. >> >> On 07/01/2025 12:56, Jessica Clarke wrote: >>> On Fri, Jan 03, 2025 at 04:14:31PM -0600, Rob Herring wrote: >>>> On Fri, Jan 3, 2025 at 12:16 PM Vincenzo Frascino >>>> wrote: >>>>> + cpus { >>>>> + #address-cells = <2>; >>>>> + #size-cells = <0>; >>>>> + >>>>> + cpu0: cpu@0 { >>>>> + compatible = "arm,neoverse-n1"; >>>> >>>> I'm pretty sure the N1 doesn't support CHERI/morello. Perhaps >>>> "arm,neoverse-n1-morello" if we want to capture what it is derived >>>> from and since "arm,morello" is taken already. >>> >>> Rainier is the codename of the core itself, and Morello LLVM recognises >>> -mcpu=rainier not -mcpu=morello (there's -march=morello instead), so >>> perhaps it should really be "arm,rainier". Though SMBIOS reports it as >>> Morello-R0P1 so it may be best to use "arm,morello" here. >>> >> >> We agree on the concept. It should either be "arm,rainier" or "arm,morello-r0p1" > > r0p1 isn’t right. Boards with r0p0 and r0p2 CPUs also exist (although > the former are now only within Arm, but the latter are in the wild in > limited numbers, including a couple here at Cambridge). > Agreed, my proposals were in order of preference. "arm,rainier" seems the best choice. Let's see what Rob thinks. [...] -- Regards, Vincenzo