From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B488C4332B for ; Mon, 23 Mar 2020 11:36:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EF12D206F9 for ; Mon, 23 Mar 2020 11:36:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="jUJqLG6N" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728164AbgCWLgN (ORCPT ); Mon, 23 Mar 2020 07:36:13 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:4416 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728115AbgCWLgN (ORCPT ); Mon, 23 Mar 2020 07:36:13 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 23 Mar 2020 04:35:27 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 23 Mar 2020 04:36:12 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 23 Mar 2020 04:36:12 -0700 Received: from [10.26.73.76] (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Mar 2020 11:36:09 +0000 Subject: Re: [PATCH] pwm: tegra: Add support for Tegra194 To: Sandipan Patra , , , CC: , , , , , References: <1583407653-30059-1-git-send-email-spatra@nvidia.com> From: Jon Hunter Message-ID: <1e40daf7-e5f8-7b79-cabe-8aceef6dda58@nvidia.com> Date: Mon, 23 Mar 2020 11:36:07 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <1583407653-30059-1-git-send-email-spatra@nvidia.com> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584963327; bh=Ax5Luu1Wgx/GtkJPbCn5+KhconBwWEM43/aV+eFmyS0=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=jUJqLG6NJAY/qZCEoFKvpMnAMPHll61DC5NFj9AqYPyzgsFTD0xv2wus1i/vAmlm+ ibI2WfTWY/vZfBNtYniGGZ6vYn8OIyquhxhdV1bccnlZun2XqiZqk0HoA26SweeU+B mIW+sFhuPn8In/WlNxU5j/Dpy2KozDnwd9Z1vD/IhGIUh8snwlMdCYGGbV2A6rPGBp N4Ohqed20b243fzW8a4ohKYsg3Jqx6Q1YtENlXDq3q0aAXGyvopthBHr7sTQWnX+Z1 LZA40P6nTXLa38vFLR1ZPsRenjrWSpZ+Yp+g8XcLhMz8bd7lwi+TJPBAGwKlILUa3w D+TOnrzR1R6OQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 05/03/2020 11:27, Sandipan Patra wrote: > Tegra194 has multiple PWM controllers with each having only one output. > > Also the maxmimum frequency is higher than earlier SoCs. > > Add support for Tegra194 and specify the number of PWM outputs and > maximum supported frequency using device tree match data. > > Signed-off-by: Sandipan Patra > --- > Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 1 + > drivers/pwm/pwm-tegra.c | 6 ++++++ > 2 files changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt > index 0a69ead..74c41e3 100644 > --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt > +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt > @@ -9,6 +9,7 @@ Required properties: > - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132 > - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210 > - "nvidia,tegra186-pwm": for Tegra186 > + - "nvidia,tegra194-pwm": for Tegra194 > - reg: physical base address and length of the controller's registers > - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of > the cells format. > diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c > index aa12fb3..d26ed8f 100644 > --- a/drivers/pwm/pwm-tegra.c > +++ b/drivers/pwm/pwm-tegra.c > @@ -282,9 +282,15 @@ static const struct tegra_pwm_soc tegra186_pwm_soc = { > .max_frequency = 102000000UL, > }; > > +static const struct tegra_pwm_soc tegra194_pwm_soc = { > + .num_channels = 1, > + .max_frequency = 408000000UL, > +}; > + > static const struct of_device_id tegra_pwm_of_match[] = { > { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc }, > { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc }, > + { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc }, > { } > }; > MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); > Acked-by: Jon Hunter Cheers Jon -- nvpublic