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Thu, 17 Jul 2025 04:26:40 +0000 (GMT) From: "Alim Akhtar" To: "'Sowon Na'" , , , , , Cc: , , , In-Reply-To: <20250702013316.2837427-5-sowon.na@samsung.com> Subject: RE: [PATCH 4/5] scsi: ufs: exynos: add support for ExynosAutov920 SoC Date: Thu, 17 Jul 2025 09:56:39 +0530 Message-ID: <1eab01dbf6d2$feed4810$fcc7d830$@samsung.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Content-Language: en-us Thread-Index: AQKcRDJWwAug8EBOlN5S0ESXxoAVsAF9G/OQAkREfl2ylxGNoA== X-CMS-MailID: 20250717042642epcas5p1b1ceebd9abbc906966b63b710d6a2118 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250702013332epcas2p3fc1442b0c8f8b92c9cdc8dd0398ebcb6 References: <20250702013316.2837427-1-sowon.na@samsung.com> <20250702013316.2837427-5-sowon.na@samsung.com> > -----Original Message----- > From: Sowon Na > Sent: Wednesday, July 2, 2025 7:03 AM > To: robh=40kernel.org; krzk=40kernel.org; conor+dt=40kernel.org; > vkoul=40kernel.org; alim.akhtar=40samsung.com; kishon=40kernel.org > Cc: krzk+dt=40kernel.org; linux-kernel=40vger.kernel.org; > devicetree=40vger.kernel.org; linux-samsung-soc=40vger.kernel.org; > sowon.na=40samsung.com > Subject: =5BPATCH 4/5=5D scsi: ufs: exynos: add support for ExynosAutov92= 0 SoC >=20 > Add a dedicated compatible and drv_data with associated hooks for > ExynosAutov920 SoC, Samsung Autotomotive SoC series. >=20 > ExynosAutov920 has the UFSHCI 3.1 compliant UFS controller. >=20 > Signed-off-by: Sowon Na > --- > drivers/ufs/host/ufs-exynos.c =7C 130 > +++++++++++++++++++++++++++++++--- > 1 file changed, 120 insertions(+), 10 deletions(-) >=20 =5Bsnip=5D > struct phy *generic_phy =3D ufs->phy; > int ret =3D 0; >=20 > - if (ufs->avail_ln_rx =3D=3D 0 =7C=7C ufs->avail_ln_tx =3D=3D 0) =7B > - ufshcd_dme_get(hba, > UIC_ARG_MIB(PA_AVAILRXDATALANES), > - &ufs->avail_ln_rx); > - ufshcd_dme_get(hba, > UIC_ARG_MIB(PA_AVAILTXDATALANES), > - &ufs->avail_ln_tx); > - WARN(ufs->avail_ln_rx =21=3D ufs->avail_ln_tx, > - =22available data lane is not equal(rx:%d, tx:%d)=5Cn=22, > - ufs->avail_ln_rx, ufs->avail_ln_tx); > - =7D > - Why you are moving these changes from exynos_ufs_phy_init() to exynos_ufs_p= re_link()?=20 If at all this is needed, this need to be a separate patch, not related to = adding exynosautov920 support.=20 > phy_set_bus_width(generic_phy, ufs->avail_ln_rx); >=20 > if (generic_phy->power_count) =7B > =40=40 -1065,6 +1148,16 =40=40 static int exynos_ufs_pre_link(struct ufs_= hba > *hba) > /* unipro */ > exynos_ufs_config_unipro(ufs); >=20 > + if (ufs->avail_ln_rx =3D=3D 0 =7C=7C ufs->avail_ln_tx =3D=3D 0) =7B > + ufshcd_dme_get(hba, > UIC_ARG_MIB(PA_AVAILRXDATALANES), > + &ufs->avail_ln_rx); > + ufshcd_dme_get(hba, > UIC_ARG_MIB(PA_AVAILTXDATALANES), > + &ufs->avail_ln_tx); > + WARN(ufs->avail_ln_rx =21=3D ufs->avail_ln_tx, > + =22available data lane is not equal(rx:%d, tx:%d)=5Cn=22, > + ufs->avail_ln_rx, ufs->avail_ln_tx); > + =7D > +