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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-44092db2ba6sm39464415e9.31.2025.04.23.15.26.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Apr 2025 15:26:27 -0700 (PDT) Message-ID: <1ed915a1-dd7c-4174-8ea2-07271b47bd21@linaro.org> Date: Wed, 23 Apr 2025 23:26:26 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP To: Vladimir Zapolskiy , Robert Foss , Todor Tomov , Bjorn Andersson , Konrad Dybcio Cc: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20250423221954.1926453-1-vladimir.zapolskiy@linaro.org> <20250423221954.1926453-2-vladimir.zapolskiy@linaro.org> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <20250423221954.1926453-2-vladimir.zapolskiy@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 23/04/2025 23:19, Vladimir Zapolskiy wrote: > Add device tree bindings for Qualcomm SM8650 camera subsystem. > > Signed-off-by: Vladimir Zapolskiy > --- > .../bindings/media/qcom,sm8650-camss.yaml | 394 ++++++++++++++++++ > 1 file changed, 394 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml > > diff --git a/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml > new file mode 100644 > index 000000000000..2a7c243993c4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml > @@ -0,0 +1,394 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/qcom,sm8650-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8650 Camera Subsystem (CAMSS) > + > +maintainers: > + - Vladimir Zapolskiy > + > +description: > + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. > + > +properties: > + compatible: > + const: qcom,sm8650-camss > + > + reg: > + maxItems: 17 > + > + reg-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csid_wrapper > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: csiphy4 > + - const: csiphy5 > + - const: vfe0 > + - const: vfe1 > + - const: vfe2 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + clocks: > + maxItems: 36 > + > + clock-names: > + items: > + - const: camnoc_axi_nrt > + - const: camnoc_axi_rt > + - const: cpas_ahb > + - const: cpas_fast_ahb > + - const: cpas_vfe0 > + - const: cpas_vfe1 > + - const: cpas_vfe2 > + - const: cpas_vfe_lite > + - const: csid > + - const: csiphy0 > + - const: csiphy0_timer > + - const: csiphy1 > + - const: csiphy1_timer > + - const: csiphy2 > + - const: csiphy2_timer > + - const: csiphy3 > + - const: csiphy3_timer > + - const: csiphy4 > + - const: csiphy4_timer > + - const: csiphy5 > + - const: csiphy5_timer > + - const: csiphy_rx > + - const: gcc_ahb_clk > + - const: gcc_axi_hf > + - const: gcc_axi_sf > + - const: qdss_debug_xo > + - const: vfe0 > + - const: vfe0_fast_ahb > + - const: vfe1 > + - const: vfe1_fast_ahb > + - const: vfe2 > + - const: vfe2_fast_ahb > + - const: vfe_lite > + - const: vfe_lite_ahb > + - const: vfe_lite_cphy_rx > + - const: vfe_lite_csid > + > + interrupts: > + maxItems: 16 > + > + interrupt-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: csiphy4 > + - const: csiphy5 > + - const: vfe0 > + - const: vfe1 > + - const: vfe2 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + iommus: > + maxItems: 3 > + > + interconnects: > + maxItems: 2 > + > + interconnect-names: > + items: > + - const: ahb > + - const: hf_0_mnoc > + > + power-domains: > + items: > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. > + > + power-domain-names: > + items: > + - const: ife0 > + - const: ife1 > + - const: ife2 > + - const: top > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + description: > + CSI input ports. > + > + patternProperties: > + "^port@[0-5]$": > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + > + description: > + Input port for receiving CSI data from a CSIPHY. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + bus-type: > + enum: > + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY > + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY > + > + required: > + - clock-lanes > + - data-lanes > + > + vdda-csi01-0p9-supply: > + description: > + Phandle to a 0.9V regulator supply to CSIPHY0 and CSIPHY1 IP blocks. > + > + vdda-csi24-0p9-supply: > + description: > + Phandle to a 0.9V regulator supply to CSIPHY2 and CSIPHY4 IP blocks. > + > + vdda-csi35-0p9-supply: > + description: > + Phandle to a 0.9V regulator supply to CSIPHY3 and CSIPHY5 IP blocks. > + > + vdda-csi01-1p2-supply: > + description: > + Phandle to a 1.2V regulator supply to CSIPHY0 and CSIPHY1 IP blocks. > + > + vdda-csi24-1p2-supply: > + description: > + Phandle to a 1.2V regulator supply to CSIPHY2 and CSIPHY4 IP blocks. > + > + vdda-csi35-1p2-supply: > + description: > + Phandle to a 1.2V regulator supply to CSIPHY3 and CSIPHY5 IP blocks. > + > +required: > + - compatible > + - reg > + - reg-names > + - clocks > + - clock-names > + - interconnects > + - interconnect-names > + - interrupts > + - interrupt-names > + - iommus > + - power-domains > + - power-domain-names > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + isp@acb8000 { > + compatible = "qcom,sm8650-camss"; > + reg = <0 0x0acb8000 0 0x1000>, > + <0 0x0acba000 0 0x1000>, > + <0 0x0acbc000 0 0x1000>, > + <0 0x0accb000 0 0x1000>, > + <0 0x0acd0000 0 0x1000>, > + <0 0x0acb6000 0 0x1000>, > + <0 0x0ace4000 0 0x2000>, > + <0 0x0ace6000 0 0x2000>, > + <0 0x0ace8000 0 0x2000>, > + <0 0x0acea000 0 0x2000>, > + <0 0x0acec000 0 0x2000>, > + <0 0x0acee000 0 0x2000>, > + <0 0x0ac62000 0 0xf000>, > + <0 0x0ac71000 0 0xf000>, > + <0 0x0ac80000 0 0xf000>, > + <0 0x0accc000 0 0x2000>, > + <0 0x0acd1000 0 0x2000>; > + reg-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csid_wrapper", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "csiphy4", > + "csiphy5", > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, > + <&camcc CAM_CC_CPAS_IFE_0_CLK>, > + <&camcc CAM_CC_CPAS_IFE_1_CLK>, > + <&camcc CAM_CC_CPAS_IFE_2_CLK>, > + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, > + <&camcc CAM_CC_CSID_CLK>, > + <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY1_CLK>, > + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY2_CLK>, > + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY3_CLK>, > + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY4_CLK>, > + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY5_CLK>, > + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, > + <&gcc GCC_CAMERA_AHB_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&gcc GCC_CAMERA_SF_AXI_CLK>, > + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>, > + <&camcc CAM_CC_IFE_0_CLK>, > + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_1_CLK>, > + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_2_CLK>, > + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CLK>, > + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; > + clock-names = "camnoc_axi_nrt", > + "camnoc_axi_rt", > + "cpas_ahb", > + "cpas_fast_ahb", > + "cpas_vfe0", > + "cpas_vfe1", > + "cpas_vfe2", > + "cpas_vfe_lite", > + "csid", > + "csiphy0", > + "csiphy0_timer", > + "csiphy1", > + "csiphy1_timer", > + "csiphy2", > + "csiphy2_timer", > + "csiphy3", > + "csiphy3_timer", > + "csiphy4", > + "csiphy4_timer", > + "csiphy5", > + "csiphy5_timer", > + "csiphy_rx", > + "gcc_ahb_clk", > + "gcc_axi_hf", > + "gcc_axi_sf", > + "qdss_debug_xo", > + "vfe0", > + "vfe0_fast_ahb", > + "vfe1", > + "vfe1_fast_ahb", > + "vfe2", > + "vfe2_fast_ahb", > + "vfe_lite", > + "vfe_lite_ahb", > + "vfe_lite_cphy_rx", > + "vfe_lite_csid"; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + interrupt-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "csiphy4", > + "csiphy5", > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; > + > + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, > + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "ahb", > + "hf_0_mnoc"; > + > + iommus = <&apps_smmu 0x800 0x20>, > + <&apps_smmu 0x18a0 0x40>, > + <&apps_smmu 0x1860 0x00>; > + > + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, > + <&camcc CAM_CC_IFE_1_GDSC>, > + <&camcc CAM_CC_IFE_2_GDSC>, > + <&camcc CAM_CC_TITAN_TOP_GDSC>; > + power-domain-names = "ife0", "ife1", "ife2", "top"; > + > + vdda-csi01-0p9-supply = <&vreg_0p9>; > + vdda-csi01-1p2-supply = <&vreg_1p2>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <1>; > + > + csiphy1_ep: endpoint { > + clock-lanes = <4>; > + data-lanes = <0 1>; > + remote-endpoint = <&camera_sensor>; > + }; > + }; > + }; > + }; > + }; Fine by me I have no real objection/concern with extending out the regulator names - as we've discussed, this is a more accurate description of the underlying hardware than we have thus far had. Please add in the csitpg to the description too though. csitpg0 csitpg1 ... csitpgX Then you can add Reviewed-by: Bryan O'Donoghue to this and the dts that accompanies. --- bod