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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9b7ae520c2sm296630666b.21.2026.03.30.06.50.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Mar 2026 06:50:15 -0700 (PDT) Message-ID: <1fcecede-16f0-4ce1-b76c-32f569cb5e41@oss.qualcomm.com> Date: Mon, 30 Mar 2026 15:50:12 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/4] thermal/qcom/lmh: support SDM670 and its CPU clusters To: Dmitry Baryshkov Cc: Richard Acayan , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Amit Kucheria , Thara Gopinath , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org References: <20260328014041.83777-1-mailingradian@gmail.com> <20260328014041.83777-4-mailingradian@gmail.com> <91af3fa3-85ba-44b8-8725-032f77c846de@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: bRJL-XFFtio1a64S6-3yM1yjx6HpdVCs X-Proofpoint-GUID: bRJL-XFFtio1a64S6-3yM1yjx6HpdVCs X-Authority-Analysis: v=2.4 cv=EcXFgfmC c=1 sm=1 tr=0 ts=69ca7f9a cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=pGLkceISAAAA:8 a=wnmJ5AHhSq1Bmg3ccEgA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzMwMDEwNyBTYWx0ZWRfX7bq3qHfU/oak 1RbyYEsCh3E6bD3B9ShPGVnu2rpSLtYFC6aJ2IZspDE3oIBK5j9Ij7OZ0fzimbBugaEAWS9D/Ex z7XrN+qi91uXtN87mDVkf/7Tb3efr4M8jhyHin/WxMYxzAKN8STWwaaPFDdkD0QDTpBH64cKCeS gfiBDD3ejF3ZMTcAL5M1Tpbse9FKFPTQ6vnWm/1hkQwWBDxoO3hLICnKCwKhBVLOWS2Yyn5UVd7 mo3cqj4Gvm09Bzhaoe9+Ed1YNsVSNjr316G9Zb/doWjSfj6Sn0A4hepNFbQvwI/6QDXfrLO1vyE 04x1ssVaJ6cu5GQLITiVn9Fp1sP3a1LSTGc5Tm1FV2eG+S1AZ7iX7mI0xzhEUAVx0x7MFssGpog MH0HxTWjcidB7HpN4XS89j+vL+EOOYZY8k1R+2JPGGE215kHYzr/wmZy/KCMD6HWBHTx1uEynMb Ry/hsvfePhIZMYTI/zg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-29_05,2026-03-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603300107 On 3/30/26 12:59 PM, Dmitry Baryshkov wrote: > On Mon, Mar 30, 2026 at 12:32:29PM +0200, Konrad Dybcio wrote: >> On 3/29/26 12:44 PM, Dmitry Baryshkov wrote: >>> On Fri, Mar 27, 2026 at 09:40:40PM -0400, Richard Acayan wrote: >>>> The LMh driver was made for Qualcomm SoCs with clusters of 4 CPUs, but >>>> some SoCs divide the CPUs into different sizes of clusters. In SDM670, >>>> the first 6 CPUs are in the little cluster and the next 2 are in the big >>>> cluster. Define the clusters in the match data and define the different >>>> cluster configuration for SDM670. >>>> >>>> Currently, this only supports 8 CPUs and tolerates linking to any CPU in >>>> the cluster. >>>> >>>> Signed-off-by: Richard Acayan >>>> --- >>>> drivers/thermal/qcom/lmh.c | 69 +++++++++++++++++++++++++++++++------- >>>> 1 file changed, 56 insertions(+), 13 deletions(-) >>>> >>>> +static const struct lmh_soc_data sdm670_lmh_data = { >>>> + .enable_algos = true, >>>> + .node_ids = { >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER1_NODE_ID, >>>> + LMH_CLUSTER1_NODE_ID, >>>> + }, >>>> +}; >>>> + >>>> +static const struct lmh_soc_data sdm845_lmh_data = { >>>> + .enable_algos = true, >>>> + .node_ids = { >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER1_NODE_ID, >>>> + LMH_CLUSTER1_NODE_ID, >>>> + LMH_CLUSTER1_NODE_ID, >>>> + LMH_CLUSTER1_NODE_ID, >>>> + }, >>>> +}; >>> >>> These tables made me wonder, can we determine this information from the >>> DT? For example, by reading the qcom,freq-domain property. But... >>> >>>> + >>>> +static const struct lmh_soc_data sm8150_lmh_data = { >>>> + .enable_algos = false, >>>> + .node_ids = { >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER0_NODE_ID, >>>> + LMH_CLUSTER1_NODE_ID, >>>> + LMH_CLUSTER1_NODE_ID, >>>> + LMH_CLUSTER1_NODE_ID, >>>> + LMH_CLUSTER1_NODE_ID, >>>> + }, >>>> +}; >>> >>> ... this might be problematic, unless this entry is broken. On SM8150 we >>> have three freq domains, but up to now we were programming two clustern >>> nodes. Of course it is possible to define that node_id is 0 for freq >>> domain 0 and 1 for domains 1 and 2. >> >> The third cluster situation on 8150 is not super good - we e.g. only have >> a single LMH irq that's shared between the big and prime cores. That >> was fixed with later SoCs (which is why it's not wired up in the DT today) > > Thanks! > > Anyway, from your point of view, would it be better to define mappings > in the driver (like it's done with this patch) or parse the DT? Well, we can spend a lot of time trying to be smart about it and handle the odd edge case, or add a simple comparison! Konrad