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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH v2 4/7] LoongArch: dts: DeviceTree for Loongson-2K0500 Content-Language: en-US To: Binbin Zhou , Binbin Zhou , Huacai Chen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org Cc: Huacai Chen , loongson-kernel@lists.loongnix.cn, Xuerui Wang , loongarch@lists.linux.dev, Jiaxun Yang , Hongliang Wang References: From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 15/08/2023 10:51, Binbin Zhou wrote: > Add DeviceTree file for Loongson-2K0500 processor, which integrates one > 64-bit dual emission superscalar LA264 processor core. > > Signed-off-by: Binbin Zhou > --- > arch/loongarch/boot/dts/Makefile | 2 + > .../boot/dts/loongson-2k0500-ref.dts | 115 +++++++++ > arch/loongarch/boot/dts/loongson-2k0500.dtsi | 244 ++++++++++++++++++ > 3 files changed, 361 insertions(+) > create mode 100644 arch/loongarch/boot/dts/loongson-2k0500-ref.dts > create mode 100644 arch/loongarch/boot/dts/loongson-2k0500.dtsi > > diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile > index 1e24cdb5180a..aa0b21d73d4e 100644 > --- a/arch/loongarch/boot/dts/Makefile > +++ b/arch/loongarch/boot/dts/Makefile > @@ -1,3 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0-only > > +dtb-$(CONFIG_MACH_LOONGSON64) = loongson-2k0500-ref.dtb > + > obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME)) > diff --git a/arch/loongarch/boot/dts/loongson-2k0500-ref.dts b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts > new file mode 100644 > index 000000000000..c89662e5a296 > --- /dev/null > +++ b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts > @@ -0,0 +1,115 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2023 Loongson Technology Corporation Limited > + */ > + > +/dts-v1/; > + > +#include "loongson-2k0500.dtsi" > + > +/ { > + compatible = "loongson,ls2k0500-ref", "loongson,ls2k0500"; > + model = "Loongson-2K0500 Reference Board"; > + > + aliases { > + ethernet0 = &gmac0; > + ethernet1 = &gmac1; > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + bootargs = "earlycon"; No earlycon in mainline. It's just development, not for products. > + }; > + > + cpu_clk: cpu-clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <500000000>; Conor already commented on this... > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + compatible = "loongson,la264"; > + device_type = "cpu"; > + reg = <0x0>; > + clocks = <&cpu_clk>; > + }; > + }; > + > + memory@200000 { > + device_type = "memory"; > + reg = <0x0 0x200000 0x0 0xee00000>, /* 238 MB at 2 MB */ > + <0x0 0x90000000 0x0 0x60000000>; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + linux,cma { > + compatible = "shared-dma-pool"; > + reusable; > + size = <0x0 0x2000000>; > + linux,cma-default; > + }; > + }; > +}; > + > +&gmac0 { > + status = "okay"; > + > + phy-mode = "rgmii"; > + bus_id = <0x0>; > +}; > + > +&gmac1 { > + status = "okay"; > + > + phy-mode = "rgmii"; > + bus_id = <0x1>; > +}; > + > +&i2c0 { > + status = "okay"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + eeprom@57{ > + compatible = "atmel,24c16"; > + reg = <0x57>; > + pagesize = <16>; > + }; > +}; > + > +&ehci0 { > + status = "okay"; > +}; > + > +&ohci0 { > + status = "okay"; > +}; > + > +&sata { > + status = "okay"; > +}; > + > +&uart0 { > + status = "okay"; > +}; > + > +&rtc0 { > + status = "okay"; > +}; > diff --git a/arch/loongarch/boot/dts/loongson-2k0500.dtsi b/arch/loongarch/boot/dts/loongson-2k0500.dtsi > new file mode 100644 > index 000000000000..e6f6476ab558 > --- /dev/null > +++ b/arch/loongarch/boot/dts/loongson-2k0500.dtsi > @@ -0,0 +1,244 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2023 Loongson Technology Corporation Limited > + */ > + > +/dts-v1/; > + > +#include > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + > + ref_100m: clock-ref-100m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + clock-output-names = "ref_100m"; > + }; > + > + cpuintc: interrupt-controller { > + compatible = "loongson,cpu-interrupt-controller"; > + #interrupt-cells = <1>; > + interrupt-controller; > + }; > + > + bus@10000000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>, > + <0x0 0x2000000 0x0 0x2000000 0x0 0x2000000>, > + <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>, > + <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>, > + <0xfe 0x0 0xfe 0x0 0x0 0x40000000>; > + > + isa@16400000 { > + compatible = "isa"; > + #size-cells = <1>; > + #address-cells = <2>; > + ranges = <1 0x0 0x0 0x16400000 0x4000>; > + }; > + > + liointc0: interrupt-controller@1fe11400 { > + compatible = "loongson,liointc-2.0"; > + reg = <0x0 0x1fe11400 0x0 0x40>, > + <0x0 0x1fe11040 0x0 0x8>; > + reg-names = "main", "isr0"; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&cpuintc>; > + interrupts = <2>; > + interrupt-names = "int0"; > + > + loongson,parent_int_map = <0xffffffff>, /* int0 */ > + <0x00000000>, /* int1 */ > + <0x00000000>, /* int2 */ > + <0x00000000>; /* int3 */ > + }; > + > + liointc1: interrupt-controller@1fe11440 { > + compatible = "loongson,liointc-2.0"; > + reg = <0x0 0x1fe11440 0x0 0x40>, > + <0x0 0x1fe11048 0x0 0x8>; > + reg-names = "main", "isr0"; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&cpuintc>; > + interrupts = <4>; > + interrupt-names = "int2"; > + > + loongson,parent_int_map = <0x00000000>, /* int0 */ > + <0x00000000>, /* int1 */ > + <0xffffffff>, /* int2 */ > + <0x00000000>; /* int3 */ > + }; > + > + eiointc: interrupt-controller@1fe11600 { > + compatible = "loongson,ls2k0500-eiointc"; > + reg = <0x0 0x1fe11600 0x0 0xea00>; > + interrupt-controller; > + #interrupt-cells = <1>; > + interrupt-parent = <&cpuintc>; > + interrupts = <3>; > + }; > + > + gmac0: ethernet@1f020000 { > + compatible = "snps,dwmac-3.70a"; > + reg = <0x0 0x1f020000 0x0 0x10000>; > + interrupt-parent = <&liointc0>; > + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq"; > + status = "disable"; That's not a valid status. Run some basic checks on your DTS before submitting it (dtbs_check W=1) Best regards, Krzysztof