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Fri, 23 Oct 2026 05:04:02 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b432c96badsm977598a12.14.2026.10.23.05.03.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Oct 2026 05:04:01 -0700 (PDT) Message-ID: <1feb10d8-75f3-4dbf-9fae-807dc5a22c25@oss.qualcomm.com> Date: Fri, 23 Oct 2026 14:03:57 +0200 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH DNM v3 8/8] arm64: dts: qcom: kaanapali: Add MPAM MSC nodes for the L2 caches To: Yin Li , Ben Horgan , Rob Herring Cc: James Morse , Shanker Donthineni , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich , Reinette Chatre , Fenghua Yu , Jonathan Cameron , Bjorn Andersson , Konrad Dybcio , Gavin Shan , Andre Przywara , Drew Fustini , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , Shaopeng Tan , trilok.soni@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, ganapatrao.kulkarni@oss.qualcomm.com, Srivathsa L Rao , Huang Yiwei , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, driver-core@lists.linux.dev, devicetree@vger.kernel.org References: <20261008-mpam-resctrl-dt-knp-support-v3-0-35196c2b43bf@oss.qualcomm.com> <20261008-mpam-resctrl-dt-knp-support-v3-8-35196c2b43bf@oss.qualcomm.com> <20261008210004.GA1318789-robh@kernel.org> <1d764a3d-7935-4e26-b1c2-92537e1d3811@oss.qualcomm.com> <893507ca-b956-474c-9124-92fbfc25e9ab@arm.com> <6e06228b-827a-4321-99c1-3e0e961abd61@arm.com> <86fee017-c9cb-4583-beab-4f29919fb518@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <86fee017-c9cb-4583-beab-4f29919fb518@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=V7LoQuni c=1 sm=1 tr=0 ts=6adb4d34 cx=c_pps a=ULNsgckmlI/WJG3HAyAuOQ==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=u5pNeYj4kXT91oPWfH4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1WsBpfsz9X-RYQiigVTh:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIzMDA0NiBTYWx0ZWRfX2ZE44uT/MhTv mnGWFB6sXtqYwk56L3vSoF5rhDkJ+rdcuW4KIG5k6jSOOzW1Ovkj4OM6g4LjpP9nNbfwBb3/em4 2Em/YURlZac0kWadjoCAZy4mV9D5oJY= X-Proofpoint-GUID: dExkZsSryXT2fCnob-1Hx2k8Pbz83Dw4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIzMDA0NiBTYWx0ZWRfX2RHRoS4nbcjP uOc4HutcSmbecIjDkxNNCJ6W9pWu5MnQgpuVn0b+2wKGgfO1AVtlccHyax2HxIR7LfnX0Wyic/W dyBzHhf+T8ySUtr+40nFLf6DHp1W+rRVMIgtOkV8/1BZL+GxJ/PT3t6MzqdGFb89gt+cuOSgRD/ OOlE5E+DLJ0vhvg+uM1B5S0Xggtrjk7HtUUWmZq4O6/VfTmY+jv63R1B/ZGyS+PiaUMGxGqLyWv qFBgSU8UePBuVG61BviJFXgEfJR/ots7kjmGejzTNRrwW1SUw6O4672JBHYFuCHZh+6FPqixNr0 xtnhxUTXlqRdKfk9VZdUZ52KBs2YQ2x6G2uI7/gcBAZp8UqSt/wh+Hz2oaVsbjqi1Pe6gnVcVhb ESld5uR4PoicF7aMwXnJZn4APEEQ1ETzgyyh2YQEVOyGEqJKGzOHmhV9l+cMeDs18cSq5B7Cv5R 6sV+KtFQAu4QrKp/Xlg== X-Proofpoint-ORIG-GUID: dExkZsSryXT2fCnob-1Hx2k8Pbz83Dw4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-23_03,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 phishscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610230046 On 10/14/26 9:09 AM, Yin Li wrote: > > > On 10/13/2026 6:37 PM, Ben Horgan wrote: >> Hi Yin, [...] > Hi Ben, Konrad, > > The original 0x10000 reflects the per-MSC register block size as > allocated in the KNP hardware — as Konrad noted, Qualcomm DTs tend to > use "how much register space is allocated for this block" rather than > "what the last used register ends" to avoid holes. > > We'd like to update it to 0x321c to give other platform authors a more useful reference, without exposing KNP-internal details such as address holes between blocks. In our case, we don't implement MPAMCFG_MBW_PBM, and — as you noted — the registers from 0x3000 onward are domain-specific; since we have no domains, those aren't used either. So the actual footprint we need is smaller than 0x321c, but showing the full 0x321c gives other authors a complete picture of the allocated register space. > > That said, this patch is marked DNM and is intended as a local > verification example only, not for merging. If you don't intend it to get merged, you can even put 0x12345 in there. But for future submissions that will have the intent to be merged, please stick to the 0x10000 size Konrad