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[82.67.6.57]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ff27eabc1sm58460335e9.15.2026.09.25.05.47.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 05:47:32 -0700 (PDT) From: Jerome Brunet To: Michal Wilczynski , Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Brian Masney , Heiko Stuebner , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mfd@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Andy Yan , Marek Szyprowski , Maud Spierings , Graham Markall , Icenowy Zheng , Michal Wilczynski Subject: Re: [PATCH v3 13/19] clk: starfive: jh7110-vout: Allow pixel clock rate propagation In-Reply-To: <20260904-jh7110-clean-send-v3-13-484f9ae72715@samsung.com> References: <20260904-jh7110-clean-send-v3-0-484f9ae72715@samsung.com> <20260904-jh7110-clean-send-v3-13-484f9ae72715@samsung.com> Date: Fri, 25 Sep 2026 14:47:30 +0200 Message-ID: <1j5wzt8plp.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On ven. 04 sept. 2026 at 15:27, Michal Wilczynski wrote: > The dc8200_pix0 and dc8200_pix1 MUXes feed the display controller, and > the rate they carry is ultimately produced by the HDMI PHY, which > registers hdmitx0_pixelclk as a clock provider. > > Add CLK_SET_RATE_PARENT to both MUXes so a rate requested on them > reaches that parent, instead of being clamped to whatever rate the > parent already happens to run at. > > Co-developed-by: Dominique Belhachemi > Signed-off-by: Dominique Belhachemi > Signed-off-by: Michal Wilczynski > --- > drivers/clk/starfive/clk-starfive-jh7110-vout.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c > index bad20d5d794a72f071b4d547b7304786a8ba9afa..aeba42cd3c44ba205ced52b1826d2d2de82ad78f 100644 > --- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c > +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c > @@ -40,10 +40,12 @@ static const struct jh71x0_clk_data jh7110_voutclk_data[] = { > JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), > JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), > JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB), > - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2, > + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", > + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2, I see that you've added CLK_SET_RATE_NO_REPARENT following a previous sashiko advice. Note that saying it will 'hijack' the parent without it is kind of strong. It is fine to let a mux reparent while setting a rate, as long as you understand the possible consequences for the rest of the tree. Regardless Reviewed-by: Jerome Brunet > JH7110_VOUTCLK_DC8200_PIX, > JH7110_VOUTCLK_HDMITX0_PIXELCLK), > - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2, > + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", > + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2, > JH7110_VOUTCLK_DC8200_PIX, > JH7110_VOUTCLK_HDMITX0_PIXELCLK), > /* LCD */ > > -- > 2.34.1 > -- Jerome